JPH04162760A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH04162760A JPH04162760A JP28939490A JP28939490A JPH04162760A JP H04162760 A JPH04162760 A JP H04162760A JP 28939490 A JP28939490 A JP 28939490A JP 28939490 A JP28939490 A JP 28939490A JP H04162760 A JPH04162760 A JP H04162760A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- lead
- lead wires
- auxiliary
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 30
- 229910000679 solder Inorganic materials 0.000 abstract description 38
- 238000007747 plating Methods 0.000 abstract description 23
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical group [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 abstract 5
- 238000004806 packaging method and process Methods 0.000 abstract 2
- 238000010276 construction Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 10
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000005476 soldering Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 229910001369 Brass Inorganic materials 0.000 description 1
- 244000089486 Phragmites australis subsp australis Species 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 239000010951 brass Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000012811 non-conductive material Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
「産業上の利用分野」
この発明はＩＣ（半導体集積回路）等の半導体装置に用
いられるリードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a lead frame used in a semiconductor device such as an IC (semiconductor integrated circuit).
「従来の技術」
ＩＣなどの半導体装置の実装において、信頼性が高く、
コストのかからない実装方法が望まれている。しかし、
近年の半導体集積回路の大規模化に応じ、それを搭載す
るＩＣパッケージの多ビン化および狭ピッチ化が加速し
ているために、これに対応した精密半田付は技術の進歩
が伴わない状況が生じてきている。“Conventional technology” Highly reliable and reliable in mounting semiconductor devices such as ICs.
An inexpensive implementation method is desired. but,
In response to the recent increase in the scale of semiconductor integrated circuits, the number of bins and narrower pitches of the IC packages in which they are installed are accelerating, and the precision soldering that corresponds to this trend is not accompanied by technological advances. It's starting to happen.
即ち、多ビンおよび狭ピッチ化されたＩＣの端子を半田
付けするに際し、微細な半田付は部に一定量の半田を安
定的に供給することか極めて困難であるために、従来、
これらのＩＣに対し、手付は作業に負っているところか
大きいのが現状である。That is, when soldering the terminals of an IC with a large number of pins and a narrow pitch, it is extremely difficult to stably supply a constant amount of solder to the fine solder parts, so conventionally,
Currently, these ICs require a large amount of manual labor.
ところが手付は作業では、微細な部分に半田を供給する
場合、供給する半田量が一定しない問題がある。このた
め、供給する半田量が少ない場合は、接合部の強度不足
を来し、また、半田量が過多の場合は、隣接する端子ど
うしが半田のブリッジによって接合されて短絡してしま
う不具合を生じていた。However, in manual work, there is a problem that when supplying solder to minute parts, the amount of solder supplied is not constant. Therefore, if the amount of solder supplied is small, the strength of the joint will be insufficient, and if the amount of solder is too large, adjacent terminals will be joined by solder bridges and short circuits will occur. was.
そこで、この種の半導体装置の基板への実装方法として
、予め半導体装置の端子、例えば、ＩＣのリードに半田
メツキを施しておき、基板の回路への接合の際に、接合
部分に半田を外部から供給して接合する方法がとられて
いる。Therefore, as a method for mounting this type of semiconductor device on a board, the terminals of the semiconductor device, for example, the leads of an IC, are soldered in advance, and when joining the board to the circuit, solder is applied externally to the joint part. The method used is to supply the material from the source and join it.
ここで、半導体装置の端子に施されている半田メツキは
、外部から供給される半田との濡れ性を良好にする目的
で設けられたもので、数μｍ程度の厚さで形成される。Here, the solder plating applied to the terminals of the semiconductor device is provided for the purpose of improving wettability with solder supplied from the outside, and is formed to have a thickness of about several μm.
しかし、この程度の厚さの半田メツキのみでは、接合強
度が不足するので、不足となる半田を以下に説明する方
法で外部から供給して接合作業を行っていた。However, solder plating of this thickness alone does not provide enough bonding strength, so the solder that is insufficient is supplied from the outside by the method described below to perform the bonding work.
半田の供給方法には、糸半田を用いる方法、端子が接合
される基板のパッドに予めスクリーン印刷などによって
半田ペーストを塗布しておく方法、デイスペンサーによ
って基板のパッドに半田ペーストを塗布する方法、溶融
半田槽に基板を浸漬する方法などがある。Solder supply methods include a method using thread solder, a method in which solder paste is applied in advance to the pad of the board to which the terminal is to be bonded by screen printing, etc., a method in which the solder paste is applied to the pad of the board with a dispenser, There is a method of immersing the board in a molten solder bath.
しかし、ＱＦＰなどの多ビンで、リードの間隔が狭い本
体部を有するＩＣ，例えば、リード間隔か０．６５ｍｚ
以下のＩＣなどでは、供給半田量が僅かでも過剰である
と、リフロー（溶融）後にリード間の半田によるブリッ
ジか発生し、また、少しでも不足すると、接合強度の不
足か生じるために、適正な量の半田を供給することか極
めて困難であった。However, for ICs such as QFP that have multiple bins and have a main body with narrow lead spacing, for example, the lead spacing is 0.65 mz.
For the following ICs, if the amount of solder supplied is even slightly excessive, solder bridges will occur between the leads after reflow (melting), and if it is even slightly insufficient, the bonding strength will be insufficient, so It was extremely difficult to supply enough solder.
そこで、本願出願人は以下説明するように、ＩＣのリー
ドに厚膜半田メツキを施すことにより適量な半田をリー
ドに付着させる方法を提案するに至った。Therefore, as will be explained below, the applicant of the present application has proposed a method of attaching an appropriate amount of solder to the leads of an IC by applying thick film solder plating to the leads.
第３図はＱＦＰなどに多ビンパッケージＩＣの多数のリ
ート６に電気半田メツキを施すための治具１を示すもの
である。この治具ｌは黄銅などの金属からなる４角形状
の上枠３と非導電体の下枠２とネジ４・・・とから構成
されている。FIG. 3 shows a jig 1 for electrically soldering a large number of reeds 6 of a multi-bin package IC such as a QFP. This jig 1 is composed of a rectangular upper frame 3 made of metal such as brass, a lower frame 2 made of a non-conductive material, and screws 4 .
そして、第４図に示すように、その下枠２と上枠３との
間にＱＦＰなどの多ビンパッケージＩＣの本体部５のリ
ード６．６．・・・を挾み、ネジ４・・で固定したのち
、この治具１を半田メツキ浴へに浸漬し、リート６．６
．・・・の大部分が半田メツキ浴Ａ中に浸されるように
配置し、治具１を陰極に、半田インゴット７を陽極とし
て電気メツキすることによって行なわれる。As shown in FIG. 4, between the lower frame 2 and the upper frame 3 are leads 6.6. ... and fix it with screws 4..., then immerse this jig 1 in a solder plating bath, and
．． . . . are arranged so that most of them are immersed in the solder plating bath A, and electroplating is carried out by using the jig 1 as a cathode and the solder ingot 7 as an anode.
「発明が解決しようとする課題」
ところで、上述したようにしてＱＦＰのリードの半田メ
ツキを行った場合、ＱＦＰの４隅においてリードの配列
の規則性が失われるため、４隅近傍のリードが他のリー
ドよりもメッキ厚が厚くなる傾向にある。このため、Ｑ
ＦＰをプリント基板に実装す、る際にＱＦＰの４隅の近
傍における各リードの間か半田によって橋絡される恐れ
があるという問題かあった。また、リートのメッキ厚が
一定でないため、ＱＦＰを実装する際の実装強度が安定
性に欠けるという問題かあった。また、ＱＦＰに限らず
、他のパッケージにおいても、リード間隔が等間隔でな
い部分があると、その部分においてメツキ厚か変化して
しまうという問題があった。"Problem to be Solved by the Invention" By the way, when the leads of the QFP are soldered as described above, the regularity of the arrangement of the leads is lost at the four corners of the QFP, so the leads near the four corners are The plating thickness tends to be thicker than that of lead. For this reason, Q
When mounting the FP on a printed circuit board, there was a problem in that the leads near the four corners of the QFP could be bridged by solder. Furthermore, since the plating thickness of the REIT is not constant, there is a problem that the mounting strength when mounting the QFP is unstable. In addition, not only QFP but also other packages have a problem in that if there is a portion where the lead spacing is not equal, the plating thickness will change in that portion.
この発明は上述した事情に鑑みてなされたものであり、
各リードに対し均一な厚さの半田メツキ層を電析させる
ことかできるリードフレームを提供することを目的とす
る。This invention was made in view of the above circumstances,
It is an object of the present invention to provide a lead frame in which a solder plating layer of uniform thickness can be deposited on each lead.
「課題を解決するための手段」
この発明は、半導体素子搭載部と、一端か該半導体搭載
部に搭載される半導体素子の電極と電気的に接続され、
他端か半導体装置本体の外部に延出する複数のり−トと
、を備えたリードフレームにおいて、前記複数のリード
に加えて補助リードを備え、前記複数のリードの各々と
該リードの隣のリードとの間隔を一様にしたことを特徴
とする。"Means for Solving the Problems" The present invention provides a semiconductor element mounting section, one end of which is electrically connected to an electrode of a semiconductor element mounted on the semiconductor mounting section,
A lead frame having a plurality of leads extending from the other end to the outside of the semiconductor device main body, further comprising an auxiliary lead in addition to the plurality of leads, each of the plurality of leads and a lead adjacent to the lead. It is characterized by uniform spacing between the two.
「作用」
上記構成によれば、当該半導体装置において使用される
複数のリートの各々は、隣のリードとの間隔が一様にな
る。従って、上記構成のリードフレームに半田メツキを
施した場合、各リードに対して均一な膜厚の半田メツキ
層が電析される。"Operation" According to the above configuration, each of the plurality of leads used in the semiconductor device has a uniform distance from the adjacent lead. Therefore, when solder plating is applied to the lead frame having the above structure, a solder plating layer having a uniform thickness is deposited on each lead.
「実施例」 以下、図面を参照し、本発明の一実施例を説明する。"Example" Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図はこの発明の一実施例によるＱＦＰ用リードフレ
ーム１０を用いた半導体集積回路を示す平面図である。FIG. 1 is a plan view showing a semiconductor integrated circuit using a QFP lead frame 10 according to an embodiment of the present invention.
この図においては、リードフレーム１０の図示しないア
イランド（半導体チップ搭載部）への半導体チップの搭
載、および半導体チップの各電極パッドとリード６．６
．・−とのワイヤボンディングを終え、さらにモールド
レジンによる本体部５か形成された状態か示されている
。In this figure, a semiconductor chip is mounted on an island (semiconductor chip mounting portion) (not shown) of the lead frame 10, and each electrode pad and lead 6.6 of the semiconductor chip is shown.
．． It is shown that the wire bonding with - has been completed and the main body part 5 has been formed using molded resin.
本実施例によるリードフレーム１０は、ＱＦＰの角部に
位置する８個のリード６．６．＝−のさらにその外側に
、半導体チップの電極パッドとは接続されない８個の補
助リード６ａ〜６ｈを有している。ユニで、補助リード
６ａ〜６ｈとその隣のリード６との間隔は、他のリード
６．６．−・の配置間隔と同一間隔になっている。すな
わち、４隅のリード６．６．−についても、他の箇所に
おけるリード６．６．・と同様、隣接するリードとの間
隔が一定になっている。第１図において下方に図示され
た１辺に配列する補助リード６ａ、リード６．６．・・
、補助リード６ｂは、それらの先端部が隣のリードと分
離されずに一体となっている。The lead frame 10 according to this embodiment has eight leads 6.6. located at the corners of the QFP. Eight auxiliary leads 6a to 6h, which are not connected to the electrode pads of the semiconductor chip, are provided further outside of =-. In Uni, the distance between the auxiliary leads 6a to 6h and the lead 6 next to it is the same as that of the other leads 6.6. The spacing is the same as that of -. That is, the four corner leads 6.6. - also in other places lead 6.6.・Similar to , the distance between adjacent leads is constant. Auxiliary leads 6a, leads 6.6, .・・・
The tips of the auxiliary leads 6b are not separated from the adjacent leads but are integrated.
他の辺についても同様であり、両端の補助リードおよび
それらに挟まれたリード６．６．−の各先端部が分離さ
れず一体となっている。本体部５の４隅の各々において
、補助リード６ｂおよび６ｃのい各基部は連結部１１を
介して外周フレーム１０ｂに接続され、補助リード６ｄ
および６ｅの各基部は連結部１２を介して外周フレーム
１０ａに接続され、補助リート６ｆおよび６ｇの各基部
は連結部１３を介して外周フレーム１０ａに接続され、
さらに補助リード６ｈおよび６ａの各基部はモールドレ
ジンゲート１４を介して外周フレーム１０ｂに接続され
ている。すなわち、すべてのリード６．６．−１補助リ
ード６ａ〜６ｈおよびリードフレーム１０は電気的に短
絡された状態となっている。The same goes for the other sides, including the auxiliary leads at both ends and the leads 6, 6, and 6 sandwiched between them. The tips of - are not separated but are integrated. At each of the four corners of the main body part 5, the bases of the auxiliary leads 6b and 6c are connected to the outer peripheral frame 10b via the connecting part 11, and the auxiliary leads 6d
and 6e are connected to the outer peripheral frame 10a via the connecting part 12, and each base of the auxiliary REETs 6f and 6g is connected to the outer peripheral frame 10a through the connecting part 13,
Further, the bases of the auxiliary leads 6h and 6a are connected to the outer peripheral frame 10b via a molded resin gate 14. That is, all leads 6.6. -1 auxiliary leads 6a to 6h and lead frame 10 are electrically short-circuited.
リードに対する厚膜半田メツキを行う前に、リードフォ
ーミングが行われ、第２図に示すようにリード６．６．
・および補助リード６ａ〜６ｈか所定の形状に曲げられ
る。その後、リードフレーム１０に陰極を接続すると共
に各リード６．６゜および補助リート６ａ〜６ｈに対向
するように陽極を配置させた状態にて電気メツキ液中に
浸し、電気メツキを行う。この結果、リード６．６．−
および補助リード６ａ〜６ｈに半田メツキ層が電析され
る。ここで、各辺の最も端に位置する補助リード６ａ〜
６ｈは、メツキ厚か他よりも厚くなるが、補助リードで
ないすべてのリード６．６゜−・・・は均一のメッキ厚
となる。Before applying thick film solder plating to the leads, lead forming is performed to form the leads 6.6.6 as shown in FIG.
-The auxiliary leads 6a to 6h are bent into a predetermined shape. Thereafter, a cathode is connected to the lead frame 10, and the anode is placed so as to face each lead 6.6° and the auxiliary leads 6a to 6h, and the lead frame 10 is immersed in an electroplating solution to perform electroplating. As a result, lead 6.6. −
A solder plating layer is then electrodeposited on the auxiliary leads 6a to 6h. Here, the auxiliary leads 6a to 6a located at the end of each side
6h has a plating thickness that is thicker than the others, but all the leads 6.6°, which are not auxiliary leads, have a uniform plating thickness.
半田メツキが終了すると、リード６．６．・・および補
助リード６ａ〜６ｈの先端部が切断されることにより各
リード間が分離される。また、連結部１１〜１３および
モールドレジンゲート１４の各々が本体部５との境界部
において切断される。When the solder plating is completed, the lead is 6.6. ...and the tips of the auxiliary leads 6a to 6h are cut to separate the leads. Further, each of the connecting portions 11 to 13 and the molded resin gate 14 is cut at the boundary with the main body portion 5.
この結果、リード６．６．−のみを本体部５の４辺に有
する半導体集積回路がリードフレーム１０から分離され
る。このようにして、すべてのり一層６，６．−に均一
な厚さの厚膜半田メツキの施された半導体集積回路か得
られる。As a result, lead 6.6. The semiconductor integrated circuit having - only on the four sides of the main body portion 5 is separated from the lead frame 10. In this way, all the glue layers 6, 6. - A semiconductor integrated circuit with thick film solder plating of uniform thickness can be obtained.
「発明の効果」
以上説明したように、この発明によれば、半導体素子搭
載部と、一端か該半導体搭載部に搭載される半導体素子
の電極と電気的に接続され、他端か半導体装置本体の外
部に延出する複数のリードと、を備えたリードフレーム
において、前記複数のリードに加えて補助リードを備え
、前記複数のリードの各々と該リードの隣のリードとの
間隔を−様にしたので、半導体装置のリードフレームと
して用いた場合に各リードに−様な膜厚の半田メツキ層
を形成することができ、実装時において安定した実装強
度の得られる半導体装置を製造することができるという
効果が得られる。"Effects of the Invention" As explained above, according to the present invention, one end of the semiconductor element mounting part is electrically connected to the electrode of the semiconductor element mounted on the semiconductor mounting part, and the other end is electrically connected to the semiconductor device main body. a plurality of leads extending to the outside of the lead frame, further comprising an auxiliary lead in addition to the plurality of leads, and an interval between each of the plurality of leads and a lead adjacent to the lead in a different manner. Therefore, when used as a lead frame for a semiconductor device, it is possible to form a solder plating layer with a varying thickness on each lead, and it is possible to manufacture a semiconductor device that provides stable mounting strength during mounting. This effect can be obtained.
第１図はこの発明の一実施例によるリードを用いた半導
体集積回路を示す平面図、第２図は同実施例のリードフ
ォーミング後の形状を示す斜視図、第３図は従来の半田
メツキ治具の構成を示す斜視図、第４図は第３図の従来
の半田メツキ治具を用いた半田メツキを説明する図であ
る。
１０−−リードフレーム、６・・−・リード、６ａ〜６
ｈ−−補助リード。FIG. 1 is a plan view showing a semiconductor integrated circuit using leads according to an embodiment of the present invention, FIG. 2 is a perspective view showing the shape of the same embodiment after lead forming, and FIG. 3 is a conventional solder plating treatment. FIG. 4 is a perspective view showing the structure of the tool, and is a diagram illustrating solder plating using the conventional solder plating jig shown in FIG. 3. 10--Lead frame, 6...Lead, 6a-6
h--Auxiliary lead.
Claims (1)
電気的に接続され、他端が半導体装置本体の外部に延出
する複数のリードと、 を備えたリードフレームにおいて、 前記複数のリードに加えて補助リードを備え、前記複数
のリードの各々と該リードの隣のリードとの間隔を一様
にしたことを特徴とするリードフレーム。[Scope of Claims] A semiconductor element mounting section; a plurality of leads having one end electrically connected to an electrode of a semiconductor element mounted on the semiconductor mounting section and the other end extending outside a semiconductor device main body; A lead frame comprising: an auxiliary lead in addition to the plurality of leads, the distance between each of the plurality of leads and the lead adjacent to the lead being uniform.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2289394A JPH0787234B2 (en) | 1990-10-26 | 1990-10-26 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2289394A JPH0787234B2 (en) | 1990-10-26 | 1990-10-26 | Lead frame |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7053051A Division JP2616571B2 (en) | 1995-03-13 | 1995-03-13 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04162760A true JPH04162760A (en) | 1992-06-08 |
| JPH0787234B2 JPH0787234B2 (en) | 1995-09-20 |
Family
ID=17742657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2289394A Expired - Fee Related JPH0787234B2 (en) | 1990-10-26 | 1990-10-26 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0787234B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541447A (en) * | 1992-04-22 | 1996-07-30 | Yamaha Corporation | Lead frame |
| JP2016018821A (en) * | 2014-07-04 | 2016-02-01 | 新電元工業株式会社 | Method of manufacturing semiconductor device, semiconductor device, and lead frame |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IL127569A0 (en) | 1998-09-16 | 1999-10-28 | Comsense Technologies Ltd | Interactive toys |
| US6607136B1 (en) | 1998-09-16 | 2003-08-19 | Beepcard Inc. | Physical presence digital authentication system |
| CA2345745A1 (en) | 1998-10-02 | 2000-04-13 | Comsense Technologies, Ltd. | Card for interaction with a computer |
| US8019609B2 (en) | 1999-10-04 | 2011-09-13 | Dialware Inc. | Sonic/ultrasonic authentication method |
| US9219708B2 (en) | 2001-03-22 | 2015-12-22 | DialwareInc. | Method and system for remotely authenticating identification devices |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02220468A (en) * | 1989-02-21 | 1990-09-03 | Oki Electric Ind Co Ltd | Lead frame for semiconductor device |
-
1990
- 1990-10-26 JP JP2289394A patent/JPH0787234B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02220468A (en) * | 1989-02-21 | 1990-09-03 | Oki Electric Ind Co Ltd | Lead frame for semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541447A (en) * | 1992-04-22 | 1996-07-30 | Yamaha Corporation | Lead frame |
| JP2016018821A (en) * | 2014-07-04 | 2016-02-01 | 新電元工業株式会社 | Method of manufacturing semiconductor device, semiconductor device, and lead frame |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0787234B2 (en) | 1995-09-20 |
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| LAPS | Cancellation because of no payment of annual fees |