JP2616571B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device such as an IC (semiconductor integrated circuit).

[0002]

2. Description of the Related Art In mounting semiconductor devices such as ICs,
A highly reliable and inexpensive mounting method is desired. However, with the recent increase in the scale of semiconductor integrated circuits, the increase in the number of pins and the narrower pitch of IC packages on which they are mounted is accelerating, and the situation is not accompanied by the advancement of precision soldering technology corresponding to this. Is emerging. That is, when soldering multi-pin and narrow-pitch IC terminals, it is extremely difficult to stably supply a fixed amount of solder to a fine soldering portion. On the other hand, at present, much of the work is done by hand.

[0003] However, when solder is supplied to a fine portion in a manual mounting operation, there is a problem that the amount of supplied solder is not constant. For this reason, if the amount of supplied solder is small, the strength of the joint is insufficient.If the amount of solder is excessive, there is a problem that adjacent terminals are joined by a solder bridge and short-circuited. I was Therefore, as a method of mounting this type of semiconductor device on a substrate, a terminal of the semiconductor device, for example, a lead of an IC is subjected to solder plating in advance, and when the substrate is joined to a circuit, the solder is externally applied to the joint portion. And joining them. Here, the solder plating applied to the terminals of the semiconductor device is provided for the purpose of improving the leakability with the solder supplied from the outside, and is formed with a thickness of about several μm. However, with only the solder plating having such a thickness, the bonding strength is insufficient, so that the insufficient solder is supplied from the outside by the method described below to perform the bonding operation. The solder can be supplied by a method using thread solder, a method in which a solder paste is applied in advance to a pad of a substrate to which a terminal is to be joined by screen printing or the like, a method in which a solder paste is applied to a pad in a substrate with a dispenser, There is a method of immersing the board in a solder bath.

However, in the case of an IC such as a QFP having a multi-pin body having a narrow lead interval, for example, an IC having a lead interval of 0.65 mm or less, a reflow ( After melting), solder bridging between the leads will occur, and if any shortage occurs,
Because of insufficient bonding strength, it was extremely difficult to supply an appropriate amount of solder. Therefore, as described below, the applicant of the present application has proposed a method of applying an appropriate amount of solder to a lead of an IC by applying a thick film solder plating to the lead.

FIG. 3 shows a multi-pin package I for a QFP or the like.
Jig 1 for applying electric solder plating to many leads 6 of C
It shows. The jig 1 includes a rectangular upper frame 3 made of a metal such as brass, a non-conductive lower frame 2 and screws 4. Then, as shown in FIG. 4, the leads 6, 6,... Of the main body 5 of the multi-pin package IC such as QFP are sandwiched between the lower frame 2 and the upper frame 3, and are fixed with screws 4. This jig 1 is immersed in a solder plating bath A,
Most of the leads 6, 6,... Are arranged so as to be immersed in the solder plating bath A, and electroplating is performed using the jig 1 as a cathode and the solder ingot 7 as an anode.

[0006]

By the way, when the lead of the QFP is solder-plated as described above,
Since the regularity of the arrangement of the leads is lost at the four corners of the FP, the plating near the four corners tends to be thicker than the other leads. For this reason, when mounting the QFP on the printed circuit board, there is a problem that the lead may be bridged between the leads near the four corners of the QFP by solder. Also, since the lead plating thickness is not constant, QFP
There is a problem that the mounting strength at the time of mounting is lacking in stability. Further, not only in QFP but also in other packages, if there is a portion where the lead interval is not equal, there is a problem that the plating thickness changes at that portion. The present invention has been made in view of the above circumstances, and has as its object to provide a manufacturing method capable of depositing a solder plating layer having a uniform thickness on each lead.

[0007]

To achieve the above object, a first aspect of the present invention is a method of manufacturing a semiconductor device having a mounting portion for mounting a semiconductor element on a lead frame having leads and auxiliary leads. A main body forming step of forming a main body having a chip, a forming step of bending the lead and the auxiliary lead into a predetermined shape, a plating step of plating a solder for mounting on the lead and the auxiliary lead, and the plating step Separating the outer peripheral frame and the auxiliary lead from the lead frame. Claim 2
Is characterized in that the distance between the auxiliary lead and the lead adjacent thereto is equal to the distance between each of these leads. Further, a plurality of leads are provided along at least one side of the semiconductor device , and the auxiliary leads are both ends of a plurality of leads along the side.
The lead is arranged adjacent to and outside the lead .

[0008]

According to the above construction, since the auxiliary lead is provided in addition to the original lead, it is possible to prevent the lead at a specific position from being plated with an excessive thickness.
Further, by making the interval between the lead and the auxiliary lead uniform, the plating thickness can be made constant. In addition, stable plating strength can be obtained as a result of uniform plating of an appropriate thickness.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a QF used in one embodiment of the present invention.
FIG. 2 is a plan view showing a semiconductor integrated circuit using a P lead frame 10. In this figure, the lead frame 10
Of the semiconductor chip on the island (semiconductor chip mounting portion) and the wire bonding between the electrode pads of the semiconductor chip and the leads 6, 6,..., And the main body 5 is formed by a mold range. It is shown. The lead frame 10 according to the present embodiment includes:
Further, outside the eight leads 6, 6,... Located at the corners of the QFP, eight auxiliary leads 6a to 6h that are not connected to the electrode pads of the semiconductor chip are provided. Here, the interval between the auxiliary leads 6a to 6h and the adjacent lead 6 is the same as the arrangement interval of the other leads 6, 6,.... That is, the leads 6 at the four corners have a constant interval between adjacent leads, similarly to the leads 6 at the other locations. The auxiliary leads 6a, the leads 6, 6,..., And the auxiliary leads 6b arranged on one side shown in the lower part of FIG. 1 have their tips integrated with the adjacent leads without being separated.

[0010] The same applies to the other sides, in which the auxiliary leads at both ends and the tips of the leads 6, 6, ... sandwiched therebetween are integrated without being separated. At each of the four corners of the main body 5, the bases of the auxiliary leads 6b and 6c are connected to the outer peripheral frame 10b via the connecting portion 11, and the bases of the auxiliary leads 6d and 6e are connected via the connecting portion 12 to the outer peripheral frame 10a. And the bases of the auxiliary leads 6f and 6g are connected to the outer peripheral frame 10a via the connecting portion 13.
The bases of the auxiliary leads 6h and 6a are connected to the outer peripheral frame 10 via a mold resin gate 14.
b. That is, all leads 6,
6,..., The auxiliary leads 6a to 6h and the lead frame 10 are electrically short-circuited.

Before the lead is subjected to thick film solder plating, lead forming is performed, and the leads 6, 6,... And the auxiliary leads 6a to 6h are bent into a predetermined shape as shown in FIG. After that, the cathode is connected to the lead frame 10 and the electrode is immersed in an electroplating solution in a state where the anode is arranged so as to face each of the leads 6, 6, ... and the auxiliary leads 6a to 6h, and electroplating is performed. As a result, a solder plating layer is deposited on the leads 6, 6,... And the auxiliary leads 6a to 6h. Here, the auxiliary leads 6a to 6h located at the end of each side are thicker than the others, but all the leads 6, 6,.
... has a uniform plating thickness.

When the solder plating is completed, the leads 6, 6,
By cutting off the tips of the auxiliary leads 6a to 6h, the leads are separated from each other. Also, the connecting portion 11
13 and the mold range gate 14 are cut off at the boundary with the main body 5. As a result, the semiconductor integrated circuit having only the leads 6, 6,... On the four sides of the main body 5 is separated from the lead frame 10. In this way, a semiconductor integrated circuit in which all the leads 6, 6,...

[0013]

As is apparent from the above description, according to the present invention, plating is performed in a state where auxiliary leads are provided in addition to the original leads, so that a lead at a specific position has an excessive thickness. Can be prevented from being applied.
In addition, plating can be performed at a constant thickness by plating with uniform spacing between the lead and the auxiliary lead. In particular, by arranging the auxiliary leads at the ends of the leads arranged in a predetermined arrangement, a thick solder is applied to the auxiliary leads, and the solder thickness of the inner leads can be made constant. By removing the lead, a certain thickness of solder plating can be applied to the original lead, and a certain mounting strength can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor integrated circuit using leads according to an embodiment of the present invention.

FIG. 2 is a perspective view showing a shape after lead forming of the embodiment.

FIG. 3 is a perspective view showing a configuration of a conventional solder plating jig.

FIG. 4 is a view for explaining solder plating using the conventional solder plating jig of FIG. 3;

[Explanation of symbols]

10: Lead frame, 6: Lead, 6a to 6h
…… Auxiliary lead.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Atsushi Ota 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Yamaha Corporation (56) References JP-A-63-234551 (JP, A)

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a mounting portion on which a semiconductor element is mounted, wherein: a main body portion forming step of forming a main body portion having a semiconductor chip on a lead frame having leads and auxiliary leads; A forming step of bending the lead and the auxiliary lead into a solder for mounting, and a step of separating the outer peripheral frame and the auxiliary lead from the lead frame after the plating step. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a distance between the auxiliary lead and a lead adjacent thereto is made equal to a distance between each of these leads. Wherein said lead plurality arranged along at least one side of said semiconductor device, wherein the auxiliary lead before
Of the multiple leads along the marked side, the leads
Adjacent to de 請, characterized in that disposed on the outside
3. The method for manufacturing a semiconductor device according to claim 1 or 2 .