JPH0786589A - Manufacture of laminated-diffused-layer type mos semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the parasitic capacitance between a gate electrode and source/drain and to achieve high speed, low power dissipation and the improvement of the performance of a MOS transistor by removing an offset layer and a side wall after the molding of the gate electrode. CONSTITUTION:In the manufacturing method of a laminated-diffused-layer type MOS semiconductor device, a side wall 7a existing between a gate electrode 10 and a laminated diffused layer 3 is removed. Therefore, the part between the electrode 10 and the layer 3 becomes the air-filled part of the vacuum part, and the dielectric constant of the part becomes small. Thus, the parasitic capacitance between the gate electrode and t source/drain can be made small. Furthermore, the laminated-diffused-layer MOS semiconductor device having the excellent high speed and the high performance can be obtained. It is not always necessary that a hollow part 15 is tightly closed to the outside completely with an insulating film 14. It is satisfactory that the part where the side wall 7a is removed is filled with gas such as air or in the vacuum state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a stacked diffusion layer type MO.
S semiconductor device manufacturing method, in particular, new stacking capable of obtaining a stacked diffusion layer type MOS semiconductor device excellent in high speed and capable of reducing parasitic capacitance between the stacked diffusion layer and gate electrode The present invention relates to a method of manufacturing a diffusion layer type MOS semiconductor device.

[0002]

2A to 2D and 3A to 3C are cross-sectional views showing one conventional example of a method for manufacturing a stacked diffusion layer type MOS semiconductor device in the order of steps. Two
3A to 3D show the first half, and FIGS. 3A to 3C show the second half. First, FIGS. 2A to 2D
The first half will be described below. (A) After the selective oxidation film 2 is formed by selective oxidation of the surface portion of the semiconductor substrate 1, the diffusion layer 3 is stacked on the semiconductor substrate 1.
Then, the offset layer 4 which also functions as an interlayer insulating film is formed. FIG. 2A shows a state after the offset layer 4 is formed.

(B) Next, as shown in FIG. 2B, the offset layer 4 and the stacked diffusion layer type 3 are selectively etched using the resist film 5 as a mask. Reference numeral 6 is a concave portion formed at a position where a gate electrode should be formed by this etching. (C) Next, as shown in FIG. 2C, a sidewall forming insulating film 7 is formed by CVD. (D) Next, as shown in FIG. 2D, a sidewall 7a is formed on the inner side surface of the recess 6 by RIE with respect to the sidewall forming insulating film 7.

Next, the latter half of the conventional example will be described with reference to FIGS. (A) Next, as shown in FIG. 3A, the impurity 8 is ion-implanted to adjust Vth. (B) Next, the gate insulating film 9 is formed by heating and oxidizing the surface portion of the semiconductor substrate 1, and then the gate electrode 10 having a T-shaped cross section is formed, and impurities in the stacked diffusion layer 3 are removed. The source 11 is diffused on the surface of the semiconductor substrate 1.
s, the drain 11d is formed, and thereafter, the interlayer insulating film 1 is formed.
Form 2. FIG. 3B shows a state after the interlayer insulating film 12 is formed. (C) After that, contact holes are formed by selective etching on the interlayer insulating films 12 and 4, and thereafter, the wiring film 13 is formed. FIG. 3C shows a stacked diffusion layer type MOS semiconductor device in which the formation of the wiring film 13 has been completed.

[0005]

By the way, FIG. 2 and FIG.
Stacked diffusion layer type MO manufactured by the conventional method shown in FIG.
In the S semiconductor device, the facing area between the gate electrode 10 having a T-shaped cross section and the stacked diffusion layer 3 is large, and therefore the parasitic capacitance therebetween, that is, the parasitic capacitance between the gate and the source / drain is large. Therefore, there is a problem that improvement in performance, particularly high speed is restricted, and low power consumption is also restricted.

The present invention has been made to solve such a problem, and in a method of manufacturing a stacked diffusion layer type MOS semiconductor device, parasitic capacitance between a gate electrode and a source / drain is reduced, Furthermore, it is intended to achieve higher speed, lower power consumption, and improved performance of MOS transistors.

[0007]

A method of manufacturing a stacked diffusion layer type MOS semiconductor device according to the present invention is characterized by including a step of removing an offset layer and a sidewall after forming a gate electrode.

[0008]

According to the method of manufacturing the stacked diffusion layer type MOS semiconductor device of the present invention, the sidewall existing between the gate electrode and the stacked diffusion layer is removed, so that air or vacuum is formed between them and the dielectric constant thereof is reduced. . Therefore, it is possible to reduce the parasitic capacitance between the gate and the source / drain, and thus it is possible to obtain a stacked diffusion layer type MOS semiconductor device having a high speed and a high performance.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a stacked diffusion layer type MOS semiconductor device of the present invention will be described in detail below with reference to the illustrated embodiments.
1A to 1D are stacked diffusion layer type MOSs according to the present invention.
FIG. 6 is a cross-sectional view showing the main parts of one embodiment of a method for manufacturing a semiconductor device in the order of steps. It should be noted that, in describing the method of manufacturing the stacked diffusion layer type MOS semiconductor device, steps up to forming the offset layer 7a on the inner surface of the recess 6 formed in the stacked diffusion layer 3 and the offset layer 4 will be described with reference to FIGS. Since it is exactly the same as the step shown in FIG. 3D, the illustration and description thereof will be omitted, and the subsequent steps will be described. Further, common parts are denoted by common reference numerals throughout the drawings.

(A) After formation of the side wall 7a, FIG.
Impurity 8 is ion-implanted in the same manner as in (A), and V
Then, the gate insulating film 9 is formed by adjusting the th and then heating and oxidizing the surface portion of the semiconductor substrate 1. Then, the gate electrode 10 having a T-shaped cross section is formed, and the stacked diffusion layer 3 is formed. The impurities are diffused into the surface of the semiconductor substrate 1 to form the source 11s and the drain 11d. Figure 1 (A)
Shows the state after forming the sources 11s and 11d.

(B) Next, as shown in FIG. 1B, the offset layer 4 and the sidewall 7b are removed by etching. (C) Next, the interlayer insulating film 14 is formed as shown in FIG. 1C by a film forming method having poor step coverage, for example, sputtering. Then, the interlayer insulating film 14 does not enter the portion between the gate electrode 10 and the stacked diffusion layer 3, that is, the portion 15 where the sidewall 7a is removed, and seals the portion 15 from the outside. Therefore, the portion 15 where the sidewall 7a is removed becomes a hollow portion made of vacuum or air.

The side wall 7a made of SiO ₂ has a relative dielectric constant of about 3.9, but since the side wall 7a is replaced with vacuum or air, the dielectric constant is
It will be drastically reduced to 1 / 3.9. Therefore, the parasitic capacitance between the gate electrode and the source / drain is also very small. That is, it is about 1 / 3.9. (D) After that, contact holes are formed by selective etching on the interlayer insulating films 12 and 4, and thereafter, the wiring film 13 is formed. FIG. 1D shows a stacked diffusion layer type MOS semiconductor device in which the formation of the wiring film 13 has been completed.

According to such a method of manufacturing the stacked diffusion layer type MOS semiconductor device, since the sidewall existing between the gate electrode and the stacked diffusion layer is removed, air or vacuum is formed between them and the dielectric constant thereof is small. Become. Therefore, it is possible to reduce the parasitic capacitance between the gate and the source / drain, and thus it is possible to obtain a stacked diffusion layer type MOS semiconductor device having excellent high speed and high performance. The hollow part 15 does not necessarily need to be completely sealed from the outside by the insulating film 14. The part where the sidewall 7a is removed may be filled with a gas such as air or may be in a vacuum.

[0014]

The method of manufacturing the stacked diffusion layer type MOS semiconductor device of the present invention is characterized by including a step of removing the offset layer and the sidewall after forming the gate electrode. Therefore, the stacked diffusion layer type MO of the present invention
According to the method for manufacturing an S semiconductor device, the sidewall existing between the gate electrode and the stacked diffusion layer is removed, so that air or vacuum is provided between them and the dielectric constant thereof is reduced. Therefore, it is possible to reduce the parasitic capacitance between the gate and the source / drain, and thus it is possible to obtain a stacked diffusion layer type MOS semiconductor device having a high speed and a high performance.

[Brief description of drawings]

1A to 1D are stacked diffusion layer types M according to the present invention.
FIG. 6 is a cross-sectional view showing the main parts of one embodiment of a method for manufacturing an OS semiconductor device.

2A to 2D are cross-sectional views showing, in the order of steps, the first half of a conventional example of a method for manufacturing a stacked diffusion layer type MOS semiconductor device.

3A to 3C are cross-sectional views showing, in the order of steps, the latter half of a conventional example of a method for manufacturing a stacked diffusion layer type MOS semiconductor device.

[Explanation of symbols]

 1 Semiconductor Substrate 3 Stacked Diffusion Layer 4 Offset Layer 6 Recess 7a Sidewall 10 Gate Electrode 15 Hollow

Claims (1)

[Claims] 1. A step of forming a stacked diffusion layer and an offset layer covering the stacked diffusion layer on a semiconductor substrate, an etching step of removing at least a portion of the stacked diffusion layer and the offset layer where a gate electrode is to be formed, and the stacked diffusion. And a step of forming a sidewall on the inner side surface of the recess formed in the portion to be the gate electrode by removing the offset layer, and a step of forming the gate electrode on the inner side of the sidewall. A method of manufacturing a stacked-type MOS semiconductor device, comprising the step of removing the offset layer and the sidewall after forming the gate electrode.