JPH0786155A - Fabrication of semiconductor device - Google Patents

Fabrication of semiconductor device

Info

Publication number
JPH0786155A
JPH0786155A JP25357193A JP25357193A JPH0786155A JP H0786155 A JPH0786155 A JP H0786155A JP 25357193 A JP25357193 A JP 25357193A JP 25357193 A JP25357193 A JP 25357193A JP H0786155 A JPH0786155 A JP H0786155A
Authority
JP
Japan
Prior art keywords
glass plate
resist
semiconductor substrate
substrate
main surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25357193A
Other languages
Japanese (ja)
Inventor
Tomoyuki Ookubo
倫之 大久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Eneos Corp
Original Assignee
Japan Energy Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Energy Corp filed Critical Japan Energy Corp
Priority to JP25357193A priority Critical patent/JPH0786155A/en
Publication of JPH0786155A publication Critical patent/JPH0786155A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To secure a semiconductor substrate flatly without contaminating the surface thereof by forming a positive resist layer on a supporting body, heating the main surface of an opaque semiconductor substrate while applying pressure onto the resist layer, exposing the semiconductor substrate from the main rear surface thereof and developing the resist layer. CONSTITUTION:A holding body, i.e., a fixing glass plate 21, and a retaining glass plate 31 are spin coated with positive resists 22, 32. An opaque semiconductor substrate 11 is then applied to the resist 22 while opposing the main surface side 14 thereto. It is further spin coated with a positive resist 23. The semiconductor substrate 11 is then sandwiched between the fixing glass plate 21 and the retaining glass plate 31 while opposing the rear surface side 15 of the semiconductor substrate 11 to the resist 32 on the retaining glass plate 31. The laminate is then pressed and baked. It is then exposed from the rear side and developed thus removing the resist entirely except the resist region 24. This method allows flat securing of the semiconductor substrate and the fixing glass plate without leaving any bubble therebetween.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ガンダイオードなどの
半導体装置の製造において、製造プロセスを施すために
半導体基板の表面をガラス板などの保持体の表面に固定
する方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fixing a surface of a semiconductor substrate to a surface of a holder such as a glass plate for performing a manufacturing process in manufacturing a semiconductor device such as a Gunn diode.

【0002】[0002]

【従来の技術】従来の半導体装置の製造工程の一例とし
て、図1を用いてPHS(Plated HeatSink)構造のガン
ダイオードの製造工程を説明する。
2. Description of the Related Art As an example of a conventional process for manufacturing a semiconductor device, a process for manufacturing a gun diode having a PHS (Plated Heat Sink) structure will be described with reference to FIG.

【0003】図1(a)に示すように、GaAs、In
Pなどからなる厚さ約400μmの基板1の表主面上に
活性層とそれをはさむ高濃度不純物層とからなる厚さ1
0μm程度の動作層2をエピタキシャル成長する。動作
層2上にAuGe/Ti/Pt/めっきAuを順次積層
し金属層3を形成する。
As shown in FIG. 1A, GaAs, In
A thickness 1 consisting of an active layer and a high-concentration impurity layer sandwiching the active layer on the front main surface of a substrate 1 made of P or the like and having a thickness of about 400 μm.
The operating layer 2 having a thickness of about 0 μm is epitaxially grown. AuGe / Ti / Pt / plating Au is sequentially laminated on the operating layer 2 to form the metal layer 3.

【0004】次に、図1(b)に示すように、金属層3
側を保持板4にワックス5により固定し、基板1の裏主
面側から削り、ほぼ動作層2の厚みとする。その後、図
1(c)に示すように、目的とする素子形状に対応した
(例えば直径80μmの円形の)電極6を基板1の削ら
れた裏主面上に形成し、電極6が形成されていない動作
層2部分をRIE(反応性イオンエッチング)などの異
方性エッチングにより除去し、メサ状の素子部を形成す
る。そして、保持板4から外した金属層3を切断して各
素子に分解し、その後各素子をパッケージングしてい
た。
Next, as shown in FIG. 1B, the metal layer 3
The side is fixed to the holding plate 4 with the wax 5, and is scraped from the back main surface side of the substrate 1 to have almost the thickness of the operating layer 2. After that, as shown in FIG. 1C, an electrode 6 corresponding to a target element shape (for example, a circular shape having a diameter of 80 μm) is formed on the scraped back main surface of the substrate 1 to form the electrode 6. The portion of the operating layer 2 that has not been formed is removed by anisotropic etching such as RIE (reactive ion etching) to form a mesa-shaped element portion. Then, the metal layer 3 removed from the holding plate 4 was cut and disassembled into each element, and then each element was packaged.

【0005】[0005]

【発明が解決しようとする課題】このような工程におい
て、基板1の裏主面側を削るなどのその後の工程を行う
ため、基板1の金属層3側を保持板4にワックス5によ
り固定している。しかしながら、このような固定では、
ワックスにより基板の固定されていない面が汚染され
る、ワックスに気泡がはいるために基板が平坦に固定で
きない、また、ワックスが軟化、溶解するためその後の
洗浄用溶剤、処理温度などの工程条件が限定されるなど
の問題があった。
In such a process, the metal layer 3 side of the substrate 1 is fixed to the holding plate 4 with the wax 5 in order to carry out the subsequent processes such as cutting the back main surface side of the substrate 1. ing. However, with such fixation,
The non-fixed surface of the substrate is contaminated by the wax, the substrate cannot be fixed flat due to the presence of air bubbles in the wax, and the wax is softened and dissolved, so that the subsequent cleaning solvent, process temperature and other process conditions There was a problem such as being limited.

【0006】本発明は、上記欠点を解決したもので、本
発明の目的は、その後の工程条件が限定されることな
く、半導体基板の表面を汚染せず、平坦に固定すること
のできる方法を提供するものである。
The present invention solves the above-mentioned drawbacks, and an object of the present invention is to provide a method capable of fixing the surface of a semiconductor substrate flat without contamination of the subsequent process conditions. It is provided.

【0007】[0007]

【課題を解決するための手段】本発明による半導体装置
の製造方法は、半導体基板の一主面に製造工程を施すた
めに該半導体基板の他の主面を保持体に固定する工程に
おいて、(a)該保持体上にポジ型レジスト層を形成し、
(b)不透明な前記半導体基板の他の主面を前記レジスト
層に加圧しながら加熱し、(c)前記半導体基板の一主面
上から露光して前記レジスト層を現像するものである。
According to the method of manufacturing a semiconductor device of the present invention, in the step of fixing the other main surface of the semiconductor substrate to the holder in order to perform the manufacturing process on one main surface of the semiconductor substrate, a) forming a positive resist layer on the holder,
(b) The other main surface of the opaque semiconductor substrate is heated while applying pressure to the resist layer, and (c) the resist layer is developed by exposing from one main surface of the semiconductor substrate.

【0008】[0008]

【発明の作用及び効果】本発明によれば、ポジ型レジス
ト層を加圧しながら加熱しているので、そのレジスト層
内に気泡が残ることなく、同時に、不透明な基板をレジ
スト層の逆側から露光してレジスト層を現像することで
基板と保持体間以外のレジスト層を選択的に除去するこ
とができる。
According to the present invention, since the positive type resist layer is heated under pressure, no air bubbles remain in the resist layer and at the same time, the opaque substrate is removed from the opposite side of the resist layer. By exposing and developing the resist layer, the resist layer other than between the substrate and the holder can be selectively removed.

【0009】したがって、簡単な工程により、基板の固
定されていない面には何ら残留せず、保持体上に基板を
平坦に固定することが可能となり、半導体装置の量産工
程に最適である。
Therefore, by a simple process, the substrate does not remain on the unfixed surface of the substrate and the substrate can be flatly fixed on the holder, which is most suitable for the mass production process of semiconductor devices.

【0010】[0010]

【実施例】本発明の一実施例であるガンダイオードの製
造工程を図2乃至図5を用いて説明する。図2に示すよ
うに、InPからなる厚さ400μmの基板11の表主
面上に活性層とそれをはさむ高濃度不純物層とからなる
厚さ10μm程度の動作層12をエピタキシャル成長す
る。動作層12上にAuGe/Ti/Pt/めっきAu
を順次積層した金属層13を形成する。めっきAu層は
30μm以上の厚さであり、紫外および可視の光を遮蔽
することができる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing process of a Gunn diode which is an embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 2, an operating layer 12 of about 10 μm in thickness composed of an active layer and a high-concentration impurity layer sandwiching the active layer is epitaxially grown on the front main surface of a substrate 11 of InP having a thickness of 400 μm. AuGe / Ti / Pt / plated Au on the operating layer 12
To sequentially form a metal layer 13. The plated Au layer has a thickness of 30 μm or more and can block ultraviolet and visible light.

【0011】この基板11の表主面側14を保持体であ
る固定用ガラス板21の平坦な表面に固定する。まず、
固定用ガラス板21とそれと同等な押さえ用ガラス板3
1を用意し、それらの表面にノボラック樹脂系のポジ型
フォトレジスト(マイクロポジット社製、MP1400
−27)を厚さ3.5μmになるようにスピンコート
(回転数:3000rpm)する。図3に示すように、固定用
ガラス板21のレジスト22上に、基板11の表主面側
14を対向させて貼付る。さらに、同じポジ型フォトレ
ジストをレジスト22上および基板11の側面部および
裏主面15上に厚さ3.5μmのレジスト23をスピン
コート(回転数:3000rpm)する。なお、この際、基板
11と固定用ガラス板21上のレジスト22との間に気
泡が入ってもよい。その後、基板11の裏主面側15に
押さえ用ガラス板31上のレジスト32を対向させて、
基板11を固定用ガラス板21と押さえ用ガラス板31
の間にはさみ込む。
The front main surface side 14 of the substrate 11 is fixed to a flat surface of a fixing glass plate 21 which is a holder. First,
Fixing glass plate 21 and pressing glass plate 3 equivalent thereto
1 are prepared, and novolak resin-based positive photoresists (MP1400, manufactured by Microposit Co., Ltd.) are provided on their surfaces.
-27) is spin-coated (rotation speed: 3000 rpm) so that the thickness becomes 3.5 μm. As shown in FIG. 3, the front main surface side 14 of the substrate 11 is attached to the resist 22 of the fixing glass plate 21 so as to face it. Further, the same positive photoresist is spin-coated (rotation speed: 3000 rpm) on the resist 22 and on the side surface of the substrate 11 and the back main surface 15 with a resist 23 having a thickness of 3.5 μm. At this time, bubbles may enter between the substrate 11 and the resist 22 on the fixing glass plate 21. After that, the resist 32 on the pressing glass plate 31 is opposed to the back main surface side 15 of the substrate 11,
The glass plate 21 for fixing and the glass plate 31 for pressing the substrate 11
Sandwich between them.

【0012】図4に示すように、基板11を固定用ガラ
ス板21と押さえ用ガラス板31の間にはさみ込み、押
さえ用ガラス板31上に錘(図示せず)を置くことで、
500〜600g/cm2の圧力で加圧し、そのまま、
80℃で30分間ベーキングする。この工程によりレジ
スト22と基板11間の気泡が抜け、平坦に基板11が
固定できる。押さえ用ガラス板31側からレジスト2
2、23、32を500mJ/cm2の条件で露光する。レジス
ト22、23、32を現像液(マイクロポジット社製、
MP450を希釈したもの)により現像することによ
り、基板11と固定用ガラス板21間のレジスト領域2
4以外の部分のすべてのレジストを除去することができ
る。同時に押さえ用ガラス板31も外される。その後、
基板11と固定用ガラス板21間のレジスト領域24に
よる固定を強固なものとするために100℃30分間の
ポストべークを行う。
As shown in FIG. 4, the substrate 11 is sandwiched between the fixing glass plate 21 and the pressing glass plate 31, and a weight (not shown) is placed on the pressing glass plate 31,
Pressurize at a pressure of 500-600 g / cm 2 ,
Bake at 80 ° C for 30 minutes. By this step, bubbles between the resist 22 and the substrate 11 are removed, and the substrate 11 can be fixed flat. The resist 2 from the pressing glass plate 31 side
2 , 23 and 32 are exposed under the condition of 500 mJ / cm 2 . The resists 22, 23, 32 are developed by a developing solution (manufactured by Microposit,
The resist region 2 between the substrate 11 and the fixing glass plate 21 is developed by developing with MP450 diluted).
It is possible to remove all the resist except for the portion 4 in FIG. At the same time, the pressing glass plate 31 is also removed. afterwards,
Post-baking is performed at 100 ° C. for 30 minutes in order to strengthen the fixation by the resist region 24 between the substrate 11 and the fixing glass plate 21.

【0013】その後、基板11の裏主面側15から削
り、ほぼ動作層12の厚みとする。図5に示すように、
直径80μmの円形の電極16を基板11の削られた裏
主面上に形成し、電極15が形成されていない動作層1
2部分をRIE(反応性イオンエッチング)による異方
性エッチングにより除去し、メサ状の素子部17を形成
する。そして、金属層13と固定用ガラス板21間のレ
ジスト領域24を剥離剤(アセトン)で除去すことで、
固定用ガラス板21から外した金属層13を切断して各
素子に分解し、ガンダイオードが完成する。
After that, the back main surface side 15 of the substrate 11 is ground to obtain almost the thickness of the operating layer 12. As shown in FIG.
An operating layer 1 in which a circular electrode 16 having a diameter of 80 μm is formed on the scraped back main surface of the substrate 11 and the electrode 15 is not formed
The two portions are removed by anisotropic etching by RIE (reactive ion etching) to form a mesa-shaped element portion 17. Then, by removing the resist region 24 between the metal layer 13 and the fixing glass plate 21 with a release agent (acetone),
The metal layer 13 removed from the fixing glass plate 21 is cut and disassembled into each element, and the Gunn diode is completed.

【0014】以上の工程によれば、簡単な工程により、
基板11の表面のレジストは露光・現像によりすべて除
去され、また、基板11と固定用ガラス板21との間に
気泡が残ることもないので平坦に固定することができ
る。したがって、固定後の基板11の裏主面側の削りお
よび異方性エッチングにおいても各素子間の厚さバラツ
キなどがなく、また、ワックスによる固定と比べて、温
度、化学的に安定なため、異方性エッチングの温度条件
や表面の汚染を考慮する必要もなく、最良の条件での製
造が可能となる。
According to the above steps, the simple steps are as follows:
The resist on the surface of the substrate 11 is completely removed by exposure and development, and since no bubbles remain between the substrate 11 and the fixing glass plate 21, the resist can be fixed flat. Therefore, even when the back main surface of the substrate 11 is fixed and the anisotropic etching is performed, there is no variation in the thickness between the elements, and the temperature and the chemical stability are stable as compared with fixing by wax. It is possible to manufacture under the best conditions without considering the temperature conditions of anisotropic etching and surface contamination.

【図面の簡単な説明】[Brief description of drawings]

【図1】従来技術であるPHS構造ガンダイオードの製
造工程を説明するための断面図である。
FIG. 1 is a cross-sectional view for explaining a manufacturing process of a PHS structure Gunn diode which is a conventional technique.

【図2】本発明の実施例における基板11の表主面側の
工程を説明するための断面図である。
FIG. 2 is a cross-sectional view for explaining a process on the front main surface side of the substrate 11 in the example of the present invention.

【図3】本発明の実施例における固定用ガラス板21上
への基板11の配置の工程を説明するための断面図であ
る。
FIG. 3 is a cross-sectional view for explaining a step of disposing the substrate 11 on the fixing glass plate 21 in the example of the present invention.

【図4】本発明の実施例における固定用ガラス板21と
押さえ用ガラス板31の間に基板11をはさみ込む工程
を説明するための断面図である。
FIG. 4 is a cross-sectional view for explaining a step of sandwiching the substrate 11 between the fixing glass plate 21 and the pressing glass plate 31 in the example of the present invention.

【図4】本発明の実施例におけるレジスト22、23、
32の露光工程を説明するための断面図である。
FIG. 4 shows resists 22 and 23 according to an embodiment of the present invention.
It is sectional drawing for demonstrating the exposure process of 32.

【図5】本発明の実施例における固定用ガラス板21に
基板11が固定された後の工程を説明するための断面図
である。
FIG. 5 is a cross-sectional view for explaining a step after the substrate 11 is fixed to the fixing glass plate 21 in the example of the present invention.

【符号の説明】[Explanation of symbols]

11 基板 12 動作層 13 金属層 14 表主面側 15 裏主面側 16 電極 17 素子部 21 固定用ガラス板 22 レジスト 23 レジスト 24 レジスト領域 31 押さえ用ガラス板 32 レジスト 11 substrate 12 operation layer 13 metal layer 14 front main surface side 15 back main surface side 16 electrode 17 element part 21 fixing glass plate 22 resist 23 resist 24 resist region 31 pressing glass plate 32 resist

─────────────────────────────────────────────────────
─────────────────────────────────────────────────── ───

【手続補正書】[Procedure amendment]

【提出日】平成5年11月22日[Submission date] November 22, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】図4[Name of item to be corrected] Fig. 4

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図4】 [Figure 4]

【手続補正書】[Procedure amendment]

【提出日】平成6年4月22日[Submission date] April 22, 1994

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】明細書[Document name to be amended] Statement

【補正対象項目名】図面の簡単な説明[Name of item to be corrected] Brief description of the drawing

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図面の簡単な説明】[Brief description of drawings]

【図1】従来技術であるPHS構造ガンダイオードの製
造工程を説明するための断面図である。
FIG. 1 is a cross-sectional view for explaining a manufacturing process of a PHS structure Gunn diode which is a conventional technique.

【図2】本発明の実施例における基板11の表主面側の
工程を説明するための断面図である。
FIG. 2 is a cross-sectional view for explaining a process on the front main surface side of the substrate 11 in the example of the present invention.

【図3】本発明の実施例における固定用ガラス板21上
への基板11の配置の工程を説明するための断面図であ
る。
FIG. 3 is a cross-sectional view for explaining a step of disposing the substrate 11 on the fixing glass plate 21 in the example of the present invention.

【図4】本発明の実施例における固定用ガラス板21と
押さえ用ガラス板31の間に基板11をはさみ込む工程
を説明するための断面図である。
FIG. 4 is a cross-sectional view for explaining a step of sandwiching the substrate 11 between the fixing glass plate 21 and the pressing glass plate 31 in the example of the present invention.

【図5】本発明の実施例における固定用ガラス板21に
基板11が固定された後の工程を説明するための断面図
である。
FIG. 5 is a cross-sectional view for explaining a step after the substrate 11 is fixed to the fixing glass plate 21 in the example of the present invention.

【符号の説明】 11 基板 12 動作層 13 金属層 14 表主面側 15 裏主面側 16 電極 17 素子部 21 固定用ガラス板 22 レジスト 23 レジスト 24 レジスト領域 31 押さえ用ガラス板 32 レジスト[Explanation of reference numerals] 11 substrate 12 operation layer 13 metal layer 14 front main surface side 15 back main surface side 16 electrode 17 element portion 21 fixing glass plate 22 resist 23 resist 24 resist region 31 pressing glass plate 32 resist

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板の一主面に製造工程を施すた
めに該半導体基板の他の主面を保持体に固定する工程に
おいて、 (a)該保持体上にポジ型レジスト層を形成し、 (b)不透明な前記半導体基板の他の主面を前記レジスト
層に加圧しながら加熱し、 (c)前記半導体基板の一主面上から露光して前記レジス
ト層を現像することを特徴とする半導体装置の製造方
法。
1. In a step of fixing another main surface of the semiconductor substrate to a holder so as to perform a manufacturing process on one main surface of the semiconductor substrate, (a) forming a positive resist layer on the holder. (B) heating the other major surface of the opaque semiconductor substrate while applying pressure to the resist layer, and (c) exposing the one major surface of the semiconductor substrate to develop the resist layer. Of manufacturing a semiconductor device.
JP25357193A 1993-09-17 1993-09-17 Fabrication of semiconductor device Pending JPH0786155A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25357193A JPH0786155A (en) 1993-09-17 1993-09-17 Fabrication of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25357193A JPH0786155A (en) 1993-09-17 1993-09-17 Fabrication of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0786155A true JPH0786155A (en) 1995-03-31

Family

ID=17253230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25357193A Pending JPH0786155A (en) 1993-09-17 1993-09-17 Fabrication of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0786155A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498129B1 (en) * 2001-10-03 2005-07-01 다이닛뽕스크린 세이조오 가부시키가이샤 Substrate Processing Apparatus and Substrate Processing Method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498129B1 (en) * 2001-10-03 2005-07-01 다이닛뽕스크린 세이조오 가부시키가이샤 Substrate Processing Apparatus and Substrate Processing Method

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