JPH0785586B2 - Digital type phase lock circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase lock circuit of a digital video device for digitally processing a video signal.

[Prior Art] FIG. 3 shows, for example, the 1980 Television Society National Convention Proceedings.
16-5 (P367,368) shows an example of a digital phase lock circuit in a conventional digital video device.

In the figure, (1) is an A / D conversion circuit for converting an analog video signal into digital data, (2) is a digital signal processing circuit for processing a video signal converted into digital data by the A / D conversion circuit (1), (3) is a sync separation circuit that generates a burst gate pulse in a burst signal period from an analog video signal, and (4) is a burst gate pulse from the sync separation circuit (3), and takes in data of a burst signal portion to calculate a phase error Phase error calculation circuit,
(5) is an integration circuit that compensates for the phase locked loop, (6) is a D / A conversion circuit that converts the phase error data into an analog voltage, and (7) is oscillated by the output error voltage of the D / A conversion circuit (6). Conversion clock generator (VCX that can change frequency)
O) and (8) are wobbling circuits that change the conversion clock phase.

FIG. 4 is a diagram showing the internal configuration of the phase error calculation circuit (4). (9a) to (9d) are cumulative adders for cumulatively adding digital data of burst signal portions, and (10a) to (10c).
Is a subtracter, and (11) is a tangent ROM (RE that outputs the product of the operation result of the subtractor (10b) and the tangent of the target phase θ ₀ (tan θ ₀ ).
AD ONLY MEMORY).

FIG. 5 is a diagram showing the quantization range of the video signal, and FIG. 6 is a diagram showing sampling points in the burst signal portion of the video signal. FIG. 7 is a diagram showing a phase comparison characteristic without wobbling, and FIG. 8 is a diagram showing a phase comparison characteristic with wobbling.

Next, the operation will be described. In FIG. 3, the input video signal is converted by the A / D conversion circuit (1), for example, the conversion clock is four times as large as the color subcarrier fsc (4fsc = 14.3MHz).
And the reference voltage (reference voltage) of the A / D conversion circuit (1) is RefV, and the horizontal sync signal (H SYN
The C level from the lowest level (SYNC TIP) of C) to the peak level including the color signal is quantized by 8 bits.
Here, in order to match the sampling points in each horizontal scan, the conversion clock phase is generally controlled so as to have a constant phase difference with respect to the burst phase. This method will be described below.

As shown in FIG. 6, there are always 4 sampling points in the burst period, such as P _{1 to} P _4K , in one burst period. This data is taken into the phase error calculation circuit (4) by the burst gate pulse from the sync separation circuit (3). From SYNC TIP to zero level is a, burst amplitude level is b, phase difference between burst signal and conversion clock is θ,
Assuming that the target value of the phase difference is θ ₀ , the phase error calculation circuit (4) performs the following calculation.

However, P _4j-3 = a + b sin θ (2) P _4j-2 = a + b cos θ (3) P _4j-1 = a−b sin θ (4 P _4j = a−b cos θ) (5) Therefore, the error calculation result is as in the following expression (6).

The above calculation is performed with the circuit configuration shown in FIG. First, the digital data of the burst signal portion is taken into the cumulative adders (9a) to (9d) for each cycle of the burst signal and added for K cycles. After that, the calculation result of the cumulative adder (9b) is subtracted from the calculation result of the cumulative adder (9a) by the subtracter (10
a) and subtract the result of cumulative adder (9d) from that of cumulative adder (9c) with subtractor (10b). The result of subtracter (10b) is tangent ROM (11 ) is multiplied by the tangent of the target phase θ ₀ (tanθ _0), the result and the phase error E between the target phase theta ₀ is calculated by obtaining the difference between the subtracter (10a) by the subtractor (10c) It

However, as shown in FIG. 7, the phase comparison characteristic has a dead zone Δθ ₀ due to the quantization accuracy of A / D conversion. Therefore, in order to reduce the dead zone Δθ ₀ , the wobbling circuit (8) wobbles only the phase of the exchange clock corresponding to the burst signal portion by Δθ ₀ / k for each cycle of the burst signal, and the error calculation is performed for each K cycle. To do. Therefore, the phase characteristic shifts in the phase axis direction by the following equation (7) for each cycle of the burst signal and becomes an added value from j = 1 to K.

That is, the calculation of the phase error is given by the following equation (8), The dead zone is Δθ ₀ / K. Therefore, the phase error calculation circuit (4) obtains the phase error E from the equation (8), the integration circuit (6) integrates the phase error E, and the D / A conversion circuit (6) determines the phase error voltage. The converted clock transmission circuit (VCXO) (7) is controlled by.

[Problems to be Solved by the Invention] Since the conventional digital phase-locked loop circuit is configured as described above, in consideration of the influence of the wobbling waveform on the image signal, the dead band width Δθ that is practically sufficient with 8-bit quantization. _In order to obtain _j , a burst signal for two horizontal scanning periods is required, phase synchronization cannot be achieved within one horizontal scanning period, and there is a problem in that image quality is deteriorated due to jitter or the like.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a digital phase lock circuit capable of establishing phase lock within one horizontal scanning period.

[Means for Solving the Problem] A digital phase lock circuit according to the present invention quantizes an analog video signal with a conversion clock having a predetermined frequency.
A / D conversion circuit, a phase error detection means for detecting a phase error between the phase of the color burst signal and the phase of the conversion clock input to the A / D conversion circuit from the data of the quantized color burst signal portion, A conversion clock generation circuit that can change the phase of the conversion clock and a wobbling circuit that shifts the phase of the conversion clock every predetermined period are provided, and the phase of the conversion clock is reduced so that the phase error detected by the phase error detection means is reduced. In the digital phase synchronization circuit that controls the phase error detection means during the wobbling by the wobbling circuit every half cycle of the color burst signal,
The black level data quantized by the A / D conversion circuit is latched, and the sampling data and the latched black level data in the periods 0 to π / 2 and π to 3π / 2 of the color burst signal are latched. The cumulative addition data obtained by cumulatively adding the differences during the color bust period, the difference between the sampling data in the period of π / 2 to π and 3π / 2 to 2π of the color burst signal and the latched black level data are calculated as the color bust period. The difference between the tangent of the target phase (TAN Θ) and the multiplied data is calculated as the phase error after the medium cumulative addition.

[Operation] The phase error calculating means in the present invention calculates the phase difference from the cumulative data for the positive half cycle and the cumulative data for the negative half cycle of the burst signal of the difference between the data of the burst signal portion and the data of the black level. The detected phase error is added and the phase error for the entire period of the burst signal is detected.

Therefore, the phase difference can be detected within one horizontal scanning period, and the phases can be synchronized.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block circuit diagram showing a configuration of a phase error calculation circuit (4) which is an essential part of this embodiment. (12) is a latch circuit which holds digital data P ₀ of black level, (9)
e) to (9h) are digital data P _{1 of the} burst signal part
~ Adder for cumulatively adding the difference between P _4K and P ₀ , (13a),
(13b) is an adder.

FIG. 2 is a diagram showing sampling points in the burst signal portion of this embodiment.

Next, the operation of this embodiment will be described assuming that the conversion clock is 4fsc as in the conventional example.

The digital phase locked loop circuit according to the present invention has the same configuration and operation as the conventional circuit shown in FIG.
The phase error calculation circuit (4) has a different configuration and performs the following calculation operation. In FIG. 2, assuming that black level digital data is P ₀ and burst signal portion digital data is P _{1 to} P _4K , the positive side phase error E ₁ and the negative side phase error E ₂ of the burst signal are as follows. It can be calculated by a formula.

In equations (9) and (10), equations (2) to (5) and P ₀ = a
Substituting Therefore, E = E ₁ + E ₂ = 2E ₁ (12), which is equal to the equation (6).

The above calculation is performed with the circuit configuration shown in FIG. First, digital data of burst signal P _4j-3 , P _4j-2 ,
The difference between P _4j-1 and P _4j and P ₀ is taken into the cumulative adders (9e), (9f), (9g), and (9h) every half cycle, and the data for K cycles of the burst signal is acquired. to add. After that, the results of the cumulative adder (9e) and the cumulative adder (9g) are added by the adder (13a), and also the cumulative adder (9
The results of f) and (9h) are added by the adder (13b), and the addition result is tangent (tan θ of the target phase θ _{0 in} the tangent ROM (11).
₀ ) and the difference between this result and the adder (13a) is obtained by the subtractor (10c) to calculate the phase error E with respect to the target phase θ ₀ .

Here, in the wobbling of the conversion clock for reducing the dead zone Δθ ₀ of the phase comparison characteristic, since the phase error is determined in a half cycle of the burst signal, the wobbling is carried out by Δθ ₀ / 2k for each half cycle of the burst signal to calculate the error. Every K / 2 cycles. Therefore, the wobbling for half the period of the conventional one can provide practically sufficient performance, and the phase synchronization can be performed every horizontal scanning period.

As described above, according to the present invention, black level data is latched in the phase error calculation while wobbling is performed for each half cycle of the color burst signal, and the positive side of the color burst signal is detected. Since the phase error with the conversion clock is calculated for each half cycle and every half cycle on the negative side, phase synchronization is possible for each horizontal scanning period, and digital phase synchronization that does not cause image quality deterioration due to jitter etc. There is an effect that a circuit can be obtained.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a phase error detection circuit which is an essential part of one embodiment of the present invention, and FIG. 2 is a diagram showing sampling points in a burst signal portion of this embodiment. FIG. 3 is a block circuit diagram of a digital phase lock circuit according to a conventional example and an embodiment of the present invention, FIG. 4 is a block circuit diagram of a conventional phase error detection circuit, and FIG. 5 is a video signal quantization of a conventional example. FIG. 6 is a diagram showing a range, FIG. 6 is a diagram showing sampling points in a burst signal portion of a conventional example, and FIG.
The figure shows the phase comparison characteristics when not wobbling. FIG. 8 is a phase comparison characteristic diagram in the case of wobbling. (1) …… A / D conversion circuit, (3) …… Synchronous separation circuit,
(4) ... Phase error calculation circuit, (7) ... Conversion clock generation circuit, (8) ... Wow ring circuit, (9e), (9
f), (9g), (9h) ... Cumulative adder, (10c) ... Subtractor, (11) ... ROM, (12) ... Latch circuit, (13a),
(13b) …… Adder. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. An A / D conversion circuit for quantizing an analog video signal with a conversion clock having a predetermined frequency, and a phase of the color burst signal from the quantized color burst signal data and an input to the A / D conversion circuit. Phase error detecting means for detecting a phase error with the phase of the converted clock, and a conversion clock generating circuit capable of varying the phase of the conversion clock,
In a digital phase synchronization circuit that comprises a wobbling circuit that shifts the phase of the conversion clock every predetermined period, and that controls the phase of the conversion clock so that the phase error detected by the phase error detection means decreases. While performing the wobbling by the wobbling circuit for each half cycle of the color burst signal, the phase error detection means latches the black level data quantized by the A / D conversion circuit to obtain 0 of the color burst signal. .About..pi. / 2 and .pi..about.3.pi. / 2 periods and cumulative addition data obtained by cumulatively adding the difference between the latched black level data during the color burst period, and .pi. / 2 to .pi. The difference between the sampling data and the latched black level data in the period of 3π / 2 to 2π is determined by the color bus. A digital phase-locked loop circuit characterized by calculating the difference between the tangent of the target phase (TAN Θ) and the multiplied data as a phase error after cumulative addition during the period.