JPH0782470B2 - Bus arbitration circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a bus that grants an occupancy permission to one of the devices when a plurality of devices request the use of the bus and suppresses the use of the other device. The present invention relates to an arbitration circuit, and more particularly, to an improvement for increasing flexibility of an arbitration function.

(Prior Art) FIG. 5 is a configuration block diagram of a conventionally known bus arbitration circuit, and FIG. 6 is a relationship diagram of an input signal and an output signal. In the figure, REQ
Is a request to use the bus, GRANT is permission to use the bus, SYSTEMCLO
CK is a clock that serves as a guide for the operation of the flip-flops that form the bus arbitration circuit. A and B are independent bus users.

In such a device, whichever of the devices A and B issues a usage request earlier gets the right to use the bus, and when there is a delay, the bus waits. In the case of arrival at the same place, the bus usage right was given priority over a predetermined one (device A in this example).

(Problems to be Solved by the Invention) However, in the case of controlling a plurality of devices in parallel like an industrial control device, in some applications, it is desired to set the priority of A> B, but in other applications, B> In some cases, the priority of A may be desired, and it has been desired that the priority can be changed.

In addition, when the memory is shared by multiple processors and burst transfer is performed by both processors,
Frequent arrival of bus use requests. At this time, if the priority is fixed, if the tasks of both processors are intertwined, one of them will finish earlier, but the other will be delayed because of waiting, and as a result, the processing of the entire system will be delayed. It was

The present invention solves such a problem, and an object of the present invention is to provide a bus arbitration circuit capable of variably setting priorities when bus use requests are made simultaneously.

(Means for Solving Problems) The present invention that achieves such an object includes a plurality of devices (A,
In the bus arbitration circuit that allows one of the devices to occupy the bus and makes the other device stand by when there is a request for use of the bus from B), the receiving circuit that receives the bus request signal from the plurality of devices. (11), this reception circuit outputs the same arrival signal when the bus request signal is received at the same time (12), the same arrival recognition circuit (12), when the same arrival occurs, the priority switching signal specifies the time When there is a bus request signal before and after, the arbiter means (10) having a grant signal circuit (13) for outputting a bus occupancy permission signal to the requesting side, a storage means for storing a certain value, and an addition means An adder circuit for adding the value stored in the storage means to a value obtained by weighting a predetermined value with a distribution factor coefficient designated from the outside when the same-arrival signal is transmitted. And add this value An addition circuit (21) for storing a value obtained by subtracting the predetermined value from the added value in the storage means when the value exceeds a predetermined value, and when the value added by the addition means exceeds the predetermined value. A priority switching means (20) including a switching circuit (22) for outputting a priority switching signal and switching a device designated by the priority switching signal.

(Operation) Each component of the present invention has the following operation. The arbiter means outputs a bus use permission signal to a single device when a bus use request is made. When the same arrival occurs, the priority switching signal is designated. The priority switching means distributes to a predetermined value that fills the adder circuit when the arrival signal occurs so that each device can preferentially use the bus at a rate determined by the distribution rate coefficient. Accumulate sequentially with weighting of the coefficient,
Every time the adder circuit is full, the priority side device designated by the priority switching signal is switched.

(Example) The present invention will be described below with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In the figure, 10 is an arbiter means for giving a bus occupancy permission signal to a bus request signal, and 20 is a priority switching means for adjusting the frequency of giving a bus occupancy permission signal by a priority switching signal when there is a co-arrival. is there.

The details of these are as follows. Reference numeral 11 is a receiving circuit that receives a bus request signal from a plurality of devices connected to the bus, and 12 is a same arrival recognition circuit that outputs the same arrival signal when the receiving circuit 11 simultaneously receives the bus request signal. The same arrival means that there is a request within the time provided for receiving one bus request signal. Reference numeral 13 is a grant signal circuit that outputs a bus occupancy permission signal, and outputs it to the side that specifies the priority switching signal when a ringing occurs and to the side that requests it earlier if there is a bus request signal after a certain time. Then, it outputs to the requesting side after the bus of the previously requested device is used.

Reference numeral 21 is an addition circuit that substantially determines the number of times each device can use the bus based on the same arrival signal generated by the same arrival recognition circuit 12. Here, the distribution ratio coefficient and addition circuit specified by an external device such as a CPU are added. Is multiplied by the maximum value that can be accumulated. Reference numeral 22 denotes a circuit for switching the device designated as the priority side by the priority switching signal, and switches the priority switching signal when the value added by the adding circuit 21 overflows the maximum value that can be accumulated by the adding circuit. When this switching occurs, a value obtained by subtracting the maximum value that can be accumulated by the adder circuit from the added value of the adder circuit 21 is stored in the adder circuit 21.

FIG. 2 is a specific circuit diagram of the device shown in FIG. In the figure,
Reference numerals 111 and 112 denote flip-flops that receive one bus request signal, and configure the reception circuit 11. Reference numeral 121 is a gate circuit for ANDing the flip-flops 111 and 112, and reference numeral 122 is a flip-flop which inputs the output signal of the gate circuit 121 and outputs the arrival signal when the arrival of the bus request signal is recognized. 131 and 132 are gate circuits that suppress the output of the bus occupancy permission signal when other devices have a high priority and arrive at the same place, and output the bus occupancy permission signal even when the other device occupies the bus. Is being deterred. 133 and 134 are flip-flops that output a bus occupancy permission signal, and 135 is a switch that determines the priority of occupying the bus, and switches in conjunction with the priority switching signal.

Reference numeral 211 denotes a register that stores the weighting value transmitted from the CPU, and this value is called a distribution rate coefficient. 212 is a match recognition circuit 12
At the timing of receiving the same arrival signal transmitted from, a value obtained by multiplying the previously stored value (for example, 0.7) by the maximum value (for example, 1.0) that can be accumulated by the addition register 221 by the distribution rate coefficient (for example, 0.4) is added. And an error register that stores a value less than the maximum value that can be integrated. A value 221 is a value obtained by multiplying the value stored in the error register 212 by the distribution rate coefficient stored in the register 211 and the maximum value that can be accumulated in the addition register 221 (for example, 0.4 ×
1.0 = 0.4) is added, and carry signal CY is output when the maximum value that can be accumulated overflows.
When the carry signal CY is output, the bus request signal
When both REQA and B are turned off and the bus is not used, the designation of the device on the priority side of the priority switching signal is switched. Therefore, the device A,
The bus usage frequency of B is determined, and if it is 0.5, the usage frequency of both will be 1: 1.

FIG. 3 is a waveform diagram for explaining the relationship between the arrival signal and the bus occupation permission signal. The system clock runs at a fairly high frequency. When the arrival signal is generated, the priority switching signal is switched by the operation of the switching circuit 22.

FIG. 4 is a waveform diagram for explaining the operation of the apparatus shown in FIG.
In this case, it is assumed that the device A side has a priority at first, the setting value of the register 211 is 0.4, and the predetermined threshold value is 1.
The initial value of 0 and the error register 212 is 0.7. When the same arrival signal is first generated, the bus occupancy permission signal is given to the device A, the addition value of the error register 212 becomes 1.1, the carry of the register 221 is raised, and the priority switching signal is output and the error register The value of 212 is 0.1. When the same arrival signal is generated next, the priority switching signal is switched, so that the device B is given the bus occupation permission signal and the value of the error register 212 becomes 0.5. Since the carry signal of the register 221 does not rise, the priority switching signal returns to the original. Then, when the same arrival signal is generated, the priority switching signal is returned to the original state, so that the bus occupation permission signal is given to the device A and the value of the error register 212 becomes 0.9.

In this way, if the value of register 211 is 0.4, 4 times in 10 times
The device B side is prioritized for the times, and the device A side is prioritized for the sixth time.

In the above embodiment, the case where two bus request signals are received has been described, but the same can be applied even when the number is 3 or more.

(Effect of the invention) As described above, according to the present invention, the priority of bus occupation is determined by the weighting set from the outside.
If the value is adapted to the situation, the frequency of bus use will be the fastest in the entire system.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention, and FIG.
1 is a concrete circuit diagram of the device of FIG. 1, FIG. 3 is a waveform diagram for explaining the relationship between the arrival signal and the bus occupation permission signal, and FIG. 4 is a waveform diagram for explaining the operation of the device of FIG. Is. FIG. 5 is a block diagram of the configuration of a conventionally known bus arbitration circuit, and FIG. 6 is a relationship diagram of an input signal and an output signal. 10 ... Arbiter means, 11 ... Reception circuit, 12 ... Destination recognition circuit, 13 ... Grant signal circuit, 20 ... Priority switching means, 21 ... Adding circuit, 22 ... Switching circuit.

Claims (1)

[Claims] 1. A bus arbitration circuit for permitting one of the devices to occupy the bus and waiting for the other device when a plurality of devices (A, B) request the use of the bus. A receiving circuit (11) that receives a bus request signal from a device, an identical arrival recognition circuit (12) that outputs an identical arrival signal when this receiving circuit simultaneously accepts a bus request signal, and when an identical arrival occurs A grant signal circuit (13) that outputs a bus occupancy permission signal to the requesting side if there is a bus request signal before or after the specified time of the priority switching signal.
An arbiter means (10) provided with, a storage means for storing a certain value, and an adder circuit having an adder means, when the same arrival signal is transmitted, a predetermined distribution rate coefficient is specified from the outside. The value weighted with the value and the value stored in the storage means are added by the adding means, and when the added value exceeds the predetermined value, the predetermined value is subtracted from the added value. An adding circuit (21) for storing a value in the storage means, and a switching circuit for outputting the priority switching signal when the value added by the adding means is equal to or larger than the predetermined value and switching the device designated by the priority switching signal ( A bus arbitration circuit comprising: a priority switching means (20) provided with 22).