JPH10105509A - Method and device for controlling memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change priority when DMA request compete corresponding to conditions by varying the priority to DMA requests when there are these DMA requests simultaneously from plural units to a memory unit. SOLUTION: An arbitration circuit AC is composed of respective circuits 1-14 and when there are DMA requests simultaneously from plural units A and B to the memory unit in the case of performing the access control of the memory unit corresponding to the DMA requests from the plural units A and B, the priority to these DMA requests can be varied. Namely, the priority to the DMA requests are varied based on plural threshold values for judging the conditions of the plural units A and B. When a signal THB is at a high level, for example, it means the throughput of the unit B does not exceed the threshold value and the priority in case of competition between the DMA requests of the units A and B is set to 1:1 but when the signal THB is at low level, the priority in case of competition between the DMA requests is set to 1:2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA (Direct Memory Access) from a plurality of units.
s; direct memory access) to a memory control method and apparatus for controlling access to a memory unit having a factor.

[0002]

2. Description of the Related Art An arbitration circuit in a conventional DMA controller is configured as shown in FIG. 2 when there are two types of DMA factors. That is, FIG. 2 shows an arbitration circuit A in a conventional DMA controller.
FIG. 2 is a block diagram showing a configuration of C. In FIG.
1, 22, 23 are NOT circuits, 24, 25 are AND circuits, 26, 27, 28 are OR circuits, 29 is a three-state buffer circuit, and 30 is a memory that stores which was prioritized when a previous DMA request competed. This is a flip-flop circuit. An arbitration circuit AC is constituted by these circuits 21 to 30. In FIG. 2, REQA and REQB are DMA request signals from units A and B, respectively, and ACKA and ACKB are DMA permission signals to units A and B, respectively.

Next, the operation of the arbitration circuit AC in the conventional DMA controller will be described. First, REQA and REQB are both high level (High
Level), one input of each of the OR circuits 26 and 27 becomes a high level, so that ACKA and ACK are output.
B are both at a high level. When REQA is at a high level and REQB is at a low level, one input of the OR circuit 26 is at a high level, so that ACKA is at a high level. On the other hand, the output of the NOT circuit 21 goes low, so that the output of the AND circuit 25 goes low.
Therefore, the inputs of the OR circuit 27 are all at low level, and ACKB is at low level. When REQA is at a low level and REQB is at a high level, one input of the OR circuit 27 is at a high level, so that ACKB is at a high level. On the other hand, the output of the NOT circuit 22 goes low, so that the output of the AND circuit 24 goes low.
Therefore, the inputs of the OR circuit 26 are all at low level, and ACKA is at low level.

Here, when both REQA and REQB are at the low level, DMA requests are competing, and a DMA permission signal is given to either A or B unit in accordance with a predetermined priority. . In the arbitration circuit AC having the configuration shown in FIG. 2, the priority of the units A and B is 1: 1, and the DMA request which was not prioritized when the previous DMA request competed has priority. Assuming that the unit B has been given priority last time, the output of the D flip-flop circuit 30 becomes low level. Then, one input of the AND circuit 24 goes low, so that the output of the AND circuit 24 goes low. Therefore, the OR circuit 2
6 are all low level, and ACKA is low level. On the other hand, since the outputs of the NOT circuits 21 and 23 are both at a high level, the output of the AND circuit 25 is at a high level. Then, one input of the OR circuit 27 becomes high level, so that ACKB becomes high level. Assuming that the unit A has been given priority last time, the output of the D flip-flop circuit 30 goes high. At this time, since the output of the NOT circuit 22 is at the high level, the inputs of the AND circuit 24 are all at the high level, and the output of the AND circuit 24 is at the high level. Then, one input of the OR circuit 26 becomes high level, so that ACKA becomes high level. On the other hand, NOT circuit 2
The output of the AND circuit 25 goes low because one output of the AND circuit 25 goes low and one input of the AND circuit 25 goes low. Therefore, all inputs of the OR circuit 27 are at low level, and ACKB is at low level.

As described above, the conventional arbitration circuit AC performs access control according to a predetermined priority.

[0006]

However, in the above-mentioned conventional example, priorities when DMA requests compete are determined in advance, and therefore, for example, in FIG. There is a problem that the priority of the unit A cannot be raised when it becomes necessary to do so.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to change the priority at the time of conflicting DMA requests depending on the situation. It is an object of the present invention to provide a memory control method and apparatus capable of performing the above.

[0008]

According to a first aspect of the present invention, there is provided a memory control method for controlling a memory unit having a DMA (direct memory access) factor from a plurality of units. When a DMA request is issued from the plurality of units to the memory unit at the same time, the priority for the DMA request is made variable.

[0009] In order to achieve the above object, a second aspect is provided.
The memory control method according to claim 1, wherein the priority for the DMA request is variable based on a plurality of thresholds for determining a status of the plurality of units. Things.

[0010] Further, in order to achieve the above object, a third aspect is provided.
According to a second aspect of the present invention, in the memory control method according to the second aspect, the determining factor of the threshold value is a processing amount of the unit.

[0011] In order to achieve the above object, the present invention provides a fourth aspect.
The memory control method according to claim 1 or 2, wherein the priority for the DMA request is made variable by an arbitration circuit.

[0012] In order to achieve the above object, the present invention provides a semiconductor device comprising:
The described memory controller is capable of DMA transfer from multiple units.
(Direct memory access) In a memory control device for controlling access to a memory unit having a factor, the plurality of units simultaneously access the memory unit from the plurality of units.
Priority changing means for changing the priority of the DMA request when an MA request is issued is provided.

[0013] In order to achieve the above object, a sixth aspect of the present invention is provided.
5. The memory control device according to claim 4, wherein the priority variable unit changes a priority for the DMA request based on a plurality of thresholds for determining a status of the plurality of units. It is characterized by the following.

According to another aspect of the present invention, there is provided a computer system comprising:
The memory control device according to the sixth aspect is characterized in that, in the memory control device according to the sixth aspect, the determining factor of the threshold value is a processing amount of the unit.

According to another aspect of the present invention, there is provided a computer system comprising:
The memory control device according to claim 5 or 6, wherein the priority changing means is an arbitration circuit.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. FIG. 1 is a block diagram showing a configuration of an arbitration circuit AC in a memory control device according to an embodiment of the present invention.
3 is a NOT circuit, 4 and 5 are AND circuits, 6, 7, 8, 9
Is an OR circuit, 10 and 11 are 3-state buffer circuits, 1
Reference numerals 2 and 13 denote D flip-flop circuits for storing which of the DMA requests has been prioritized when the DMA request competed last time and two times before, respectively.
3 is a selector circuit that outputs any one of the signals. An arbitration circuit AC is constituted by these circuits 1 to 14.

In FIG. 1, REQA, REQB
Are the DMA request signals from the units A and B, respectively.
KA and ACKB are DMA permission signals to units A and B, respectively, and THB is a signal for determining a threshold value for processing of unit B. When THB is at a high level, the processing amount of unit B exceeds the threshold value. Means that the priority is set to 1: 1 when the DMA requests of the units A and B conflict, and when THB is low level, the processing amount of the unit B exceeds the threshold value. , The priority when the DMA requests of the units A and B conflict with each other is set to 1: 2.

Next, the arbitration circuit AC in the memory control device according to the present embodiment having the above configuration will be described.
Will be described. First, when THB is at the high level, the selector circuit 14 selects the output of the OR circuit 9.
Here, if both REQA and REQB are at a high level, one input of each of the OR circuits 6 and 7 is at a high level, and both ACKA and ACKB are at a high level. When REQA is at a high level and REQB is at a low level, one input of the OR circuit 6 is at a high level, so that ACKA is at a high level. On the other hand, the output of the NOT circuit 1 goes low, so that the output of the AND circuit 5 goes low. Therefore, the inputs of the OR circuit 7 are all at low level, and ACKB is at low level. When REQA is at a low level and REQB is at a high level, one input of the OR circuit 7 is at a high level, so that ACKB is at a high level. On the other hand, NOT circuit 2
Is at a low level, the output of the AND circuit 4 is at a low level. Therefore, the inputs of the OR circuit 6 are all at low level, and ACKA is at low level.

Here, when REQA and REQB are both at low level, DMA requests are competing and THB is at low level, so that the priority of units A and B is 1: 2. Assuming that the unit B has priority both in the last time and the last two times, the D flip-flop circuits 12, 1
3 are both at the low level, and the output of the OR circuit 9 is also at the low level. Therefore, the output of the selector circuit 14 becomes low level. Then, the output of the AND circuit 4 goes low and the inputs of the OR circuit 6 go low, so that ACKA goes low. on the other hand,
Since both outputs of the NOT circuits 1 and 3 become high level,
The output of the AND circuit 5 also goes high. Then, OR
Since one input of the circuit 7 becomes high level, ACKB
Becomes high level. In other words, if the unit B has priority in both the previous and previous rounds, the unit A has priority this time, and the units A and B satisfy the priority of 1: 2.

If it is assumed that the unit A has the priority last time and the unit B has the priority two times before, the outputs of the D flip-flop circuits 12 and 13 are high level and low level, respectively, and the output of the OR circuit 9 is high level. Become. Therefore, the output of the selector 14 becomes high level. Then, the output of the NOT circuit 3 becomes low level, and the output of the AND circuit 5 also becomes low level. This allows OR
Both inputs of the circuit 7 become low level, and ACKB becomes low level. On the other hand, the output of the NOT circuit 2 goes high, so that the output of the AND circuit 4 goes high.
Then, one input of the OR circuit 6 becomes high level, so that ACKA becomes high level. As described above, also in this case, the priorities 1: 2 of the units A and B are satisfied.

Assuming that the unit B has the priority last time and the unit A has the priority two times before, the outputs of the D flip-flop circuits 12 and 13 are low level and high level, respectively, and the output of the OR circuit 9 is high level. Become. Then, ACKA becomes high level and ACKB becomes low level for the same reason as when unit A was prioritized last time and unit B was prioritized two times before. Therefore, also in this case, the priorities 1: 2 of the units A and B are satisfied.

As described above, the arbitration circuit AC that can change the access priority when the DMA requests of the units A and B compete with each other according to the processing amount of the unit B can be configured.

In the above-described embodiment, D
The arbitration circuit AC has a configuration in which there are two types of units that make MA requests, and the access priority when a DMA request conflicts is changed in two ways depending on the processing amount of one of the units. The present invention is not limited to this, and various changes can be made without departing from the gist of the present invention. For example, there are a plurality of units that issue a DMA request, and for each of them, a plurality of thresholds for each processing amount are set, and the arbitration circuit AC in which the access priority at the time of DMA contention changes variously by them. Can also be configured. Further, the determining factor of the threshold does not have to be the processing amount of the unit.

[0024]

As described above, according to the memory control method and apparatus of the present invention, there are a plurality of DMA factors,
When the MA requests conflict, the access priority can be changed according to the situation of the DMA factor.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an arbitration circuit in a memory control device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an arbitration circuit in a conventional memory control device.

[Explanation of symbols]

 AC arbitration circuit 1 NOT circuit 2 NOT circuit 3 NOT circuit 4 AND circuit 5 AND circuit 6 OR circuit 7 OR circuit 8 OR circuit 9 OR circuit 10 3 state buffer circuit 11 3 state buffer circuit 12 D flip-flop circuit 13 D flip-flop circuit 14 Selector circuit

Claims (8)

[Claims] In a memory control method for controlling access to a memory unit having a DMA (direct memory access) factor from a plurality of units, when a DMA request is issued from the plurality of units to the memory unit at the same time, the DMA request is issued. A memory control method characterized by making the priority for a variable variable. 2. The memory control method according to claim 1, wherein the priority for said DMA request is made variable based on a plurality of thresholds for judging the status of said plurality of units. 3. The memory control method according to claim 2, wherein the determining factor of the threshold value is a processing amount of the unit. 4. An arbitration circuit for controlling said D
3. The memory control method according to claim 1, wherein the priority for the MA request is variable. 5. A memory control device for controlling access to a memory unit having a DMA (direct memory access) factor from a plurality of units, wherein when a DMA request is issued from said plurality of units to said memory unit at the same time, said DMA request is A memory control device comprising a priority changing means for changing the priority. 6. The apparatus according to claim 5, wherein said priority changing means changes the priority for said DMA request based on a plurality of thresholds for judging a status of said plurality of units. Memory controller. 7. The memory control device according to claim 6, wherein the determining factor of the threshold value is a processing amount of the unit. 8. The memory control device according to claim 5, wherein said priority changing means is an arbitration circuit.