JP4282297B2 - Device having bus arbitration function and numerical control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a device having a bus arbitration function for arbitrating bus use of each device in a multi-master bus in which a plurality of devices that can be bus masters are connected to a bus, and more particularly to a numerical control device having the bus arbitration function.
[0002]
[Prior art]
When a plurality of devices are connected to the bus and a bus use request is issued from a plurality of devices, it is necessary to determine which device has priority. Usually, many of the methods for determining the priority for using the bus are determined based on a predetermined priority order. In this case, when bus use requests are issued one after another from devices with high priority, bus use rights are given to these devices with high priority one after another, and bus use rights are given to devices with low priority. There is a problem of fewer cases.
[0003]
Therefore, a method is known in which a device that has obtained the right to use the bus temporarily lowers its priority and avoids that one device continuously obtains the right to use the bus. However, in a specific device such as a communication device, it may be necessary to perform control so that a bus can be acquired within a certain time. In such a case, the prior art arbitration method described above can change the priority of acquiring the bus use right, but there is a problem that the acquisition of the bus use right within a certain time cannot be guaranteed.
[0004]
Also, timing is started based on the bus use request signal from the device, and after the set time has elapsed, the bus use priority of the device is increased and the preset bus use priority is low. An arbitration method is also known in which a bus can be used for a device (see, for example, Patent Document 1).
When a timer is provided for each device (bus master), the allowable time set in each timer is set, and when a bus use request is issued from the device, it counts down and the bus becomes usable A bus adjustment method is also known in which a bus use permission is given to a device having a small timer value, the down counter is stopped, and the timer is returned to the initial value (see, for example, Patent Document 2).
[0005]
[Patent Document 1]
JP-A-2-27461 [Patent Document 2]
Japanese Patent Laid-Open No. 3-263158 [0006]
[Problems to be solved by the invention]
Even if the timer starts timing from the time when the bus use request signal is generated and the priority is determined based on this time, the device starts counting the time after the bus use request signal is generated. It takes time until the priority of bus use increases after a device requests bus use, resulting in a time loss. It is also difficult to use the bus within a certain time.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to make it possible to suppress the interval of device bus use to a certain value or less.
[0008]
[Means for Solving the Problems]
In the present invention, a plurality of devices are connected to one bus, and a bus use permission signal is received from each device and a bus use permission signal is sent to each device based on the priority of acquiring the bus use right of each device. In the apparatus having the bus arbitration function by connecting the bus arbitration means to be provided to the bus arbitration means, the bus arbitration means is provided with the bus use permission signal to one or more specific devices of the plurality of devices. After a predetermined time has elapsed, a means for raising the priority of acquiring the bus usage right of the specific device is provided to perform bus arbitration. Further, the means for setting and storing the predetermined time for the specific device is provided in the bus arbitration means or in the specific device.
[0009]
In particular, the bus arbitration means gives priority to the specific device when the predetermined time has elapsed since the bus use permission signal was given to the specific device and the bus use request signal of the specific device has been output. I got to get a bus. Further, an interrupt signal is transmitted via the bus, and the interrupt function can be implemented by setting the predetermined time to a time for achieving the interrupt function. Further, the numerical control device is provided with this bus arbitration function.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a principal block diagram of an embodiment of the present invention. Master devices 2-0, 2-1, 2-2,..., 2-n having a function of controlling the bus are connected to the bus 3, and the arbitration unit 1 is connected to the bus 3. Yes.
The arbitration unit 1 and each master device 2-0, 2-1,..., 2-n are connected by a communication line, and a bus use request signal is transmitted from each master device 2-0, 2-1,. S1n is output to the arbitration unit 1, and the bus use permission signals S20, S21,... S2n are output from the arbitration unit 1 to the multi devices 2-0, 2-1,. It has become so.
[0011]
FIG. 2 is a detailed block diagram of the arbitration unit 1 described above. The arbitration unit includes priority determination circuits 4-0, 4-1,..., 4-n that determine the priority of bus use for each master device 2-0, 2-1,. It is configured.
Each of the priority determination circuits 4-0, 4-1,..., 4-n has a time setting register 41, a timer 42, and a comparison as described in detail in the priority determination circuit 4-0 corresponding to the master device 2-0. The circuit 43 and the AND gate 44 are included. Since the priority determination circuits 4-0, 4-1,..., 4-n have the same configuration, the other priority determination circuits 4-1, ..., 4-n correspond to the priority determination circuit 4- corresponding to the master device 2-0. Same configuration as 0.
[0012]
The comparison circuit 43 compares the time set in the time setting register 41 with the time measured by the timer 42, and outputs an output signal when the time measured by the timer 42 becomes larger than the time set in the time setting register 41. .
The bus use request signals S10, S11, S1n input from the master devices 2-0, 2-1,..., 2-n to the arbitration unit 1 are input to the priority order determination circuit 5 and corresponding priority levels. Input to the AND gates 44 of the determination circuits 4-0, 4-1,. The bus use permission signals S20, S21,... S2n output from the priority determining circuit 5 are also input to the timers 42 of the corresponding priority determining circuits 4-0, 4-1,. .
[0013]
The time setting register 41 of each priority determination circuit 4-0, 4-1,..., 4-n can set an arbitrary time by setting means (not shown). Depending on the system configuration of the entire apparatus, the type of master device, and the operation mode, a master device that executes this priority control function for a master device that wants to execute processing of the master device within a certain maximum cycle interval ( For example, the time setting register 41 of the priority determination circuit (master device 4-0) corresponding to the master device 2-0) has a time slightly shorter than the desired maximum cycle interval time for the master device (2-0). Set it. That is, a time slightly shorter than the maximum time that the bus use permission signal is generated and the bus can be used by the next bus use request signal is set. Also, the time does not have to be set in the time setting register 41. In this case, as will be described later, since the priority determination circuit 5 does not receive signals from the priority determination circuits 4-0, 4-1,..., 4-n, the priority determination circuit 5 has a predetermined priority as in the conventional arbitration unit. Outputs bus use permission signal.
[0014]
Starting the operation of the apparatus, the arbitration unit 1 determines the priority order determined in advance for the bus use request signals S10, S11, S1n output from the respective master devices 2-0, 2-1,. To output bus use permission signals S20, S21,... S2n. On the other hand, a bus use permission signal (a bus permission signal S20 to the master device 2-0) to a certain master device (for example, the master device 2-0) is a priority determination circuit corresponding to the master device (2-0) ( 4-0) is also input to the timer 42, and the timer 42 is reset and started. The comparison circuit 43 compares the time measured by the timer 42 with the time set in the time setting register 41, and outputs a signal when the time measured by the timer 42 increases. If the time is not set in the time setting register 41, no signal is output from the comparison circuit 43.
[0015]
The bus use request signal (S10) from the master device (for example, master device 2-0 in the above example) corresponding to the output of the comparison circuit 43 is ORed by the AND gate 44, and the bus use request signal (S10). When there is an output signal from the comparison circuit 43, an output signal is output from the AND gate 44 and input to the priority determination circuit 5. In this way, when a signal is output from the AND gate 44 of the priority determination circuit (priority determination circuit 4-0 in the above example), when the bus use is released and the next bus use arbitration timing is reached, the priority order is determined. The decision circuit 5 gives priority to the bus use right to the master device (2-0) to which the output signal from the priority determination circuit (4-0) is input, and outputs a bus use permission signal (S20).
[0016]
That is, the priority determination circuit 5 outputs all output signals from the priority determination circuits 4-0, 4-1,..., 4-n corresponding to the master devices 2-0, 2-1,. If not, the bus use permission signals S20, S21,... S2n are output based on a predetermined priority order, and an output signal is output from the priority determination circuit corresponding to one of the master devices ( When the time measured by the timer 42 of the priority determination circuit exceeds the time set in the time setting register), a bus use permission signal is output with priority over the master device. When output signals are output from a plurality of priority determination circuits, arbitration is performed based on a preset priority order, and a bus use permission signal is output from the master device with the higher priority order.
[0017]
As a result, for the master device that sets the time in the time setting register 41 and executes the priority control, the bus use permission signal is given a little later than the time set in the time setting register 41 so that the bus can be used. Become. The bus use right is given at an interval approximately equal to the set time at the maximum, and the operation process can be executed in this cycle.
[0018]
In particular, in a device configured to transmit an interrupt signal using a bus without providing an interrupt signal line, a priority level is set at regular intervals such as a timer interrupt for notifying a unit time in the device. For a master device that causes a high processing cycle, if the time corresponding to this fixed time interval for achieving the interrupt function is set in the time setting register, as described above, this master device is given higher priority. The bus use permission signal is given to the master device almost coincident with the fixed time interval set in the time setting register, enabling the master device to perform operation processing and interrupt processing.
[0019]
In the above-described embodiment, the time setting register 41 is provided in the priority determination circuits 4-0, 4-1, and 4-n of the arbitration unit 1. However, the master devices 2-0, 2-1, and 2-n are provided. It may be provided in the priority determination circuits 4-0, 4-1, and 4-n. Furthermore, priority determination circuits 4-0, 4-1, and 4-n themselves are provided in the respective master devices 2-0, 2-1, and 2-n, and the arbitration unit 1 may be configured as the priority order determination circuit 5 alone. Good.
[0020]
【The invention's effect】
The present invention starts the timing after giving the bus use permission to a certain device, and if the measured time exceeds the set time, the bus can be used in preference to the device. Even in a crowded situation, the right to use the bus can be acquired within a certain time. Since the time can be set for each device, the right to use the bus of the device can be differentiated depending on the setting value set for the device.
[Brief description of the drawings]
FIG. 1 is a block diagram of a main part in an embodiment of the present invention.
FIG. 2 is a detailed block diagram of an arbitration unit according to the embodiment.
[Explanation of symbols]
1 Arbitration unit 2-0, 2-1, 2-n Master device 3 Bus 4-0, 4-1, 4-n Priority determination circuit 5 Priority determination circuit S10, S11, S1n Bus use request signals S20, S21, S2n bus use permission signal

Claims (7)

A bus in which a plurality of devices are connected to one bus, a bus use request signal from each device is received, and a bus use permission signal is given to each device based on the priority of acquiring the bus use right of each device. In an apparatus having a bus arbitration function by connecting arbitration means,
The bus arbitration means includes means for raising the priority of acquiring the bus use right of the specific device when a predetermined time has elapsed after the bus use permission signal is given to the specific device of the plurality of devices. A device having a bus arbitration function. The apparatus having a bus arbitration function according to claim 1, wherein there are a plurality of the specific devices, and the predetermined time is set for each specific device. The apparatus comprising the bus arbitration function according to claim 1, wherein means for setting and storing the predetermined time for the specific device is provided in the bus arbitration unit. The apparatus provided with the bus arbitration function according to claim 1, wherein means for setting and storing the predetermined time is provided in the specific device. When the predetermined time has elapsed since the bus use permission signal was given to the specific device and the bus use request signal of the specific device has been output, the bus arbitration means has priority over the specific device. The apparatus provided with the bus arbitration function according to any one of claims 1 to 4. 6. The bus arbitration according to claim 1, wherein the bus arbitration is configured to transmit an interrupt signal via a bus, and the predetermined time is set to a time for achieving an interrupt function. A device with functions. A numerical controller comprising a device having the bus arbitration function according to any one of claims 1 to 6.

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