JP2006259842A - Data transfer processing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve flexible and proper arbitration of bus, and to prevent complication of a device constitution, the increase of device cost and the like. <P>SOLUTION: This data transfer processing device comprises a common bus 1, a plurality of bus masters A-Z transferring data by using the common bus 1, a bus arbiter 2 arbitrating requests for using the common bus from the plurality of bus masters A-Z with a predetermined order of priority, and a request switching means 4 selecting one of the plurality of different orders of priority as the order of priority of one bus master among the plurality of bus masters A-Z, and periodically switching the selection. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer processing device having a function of arbitrating for common buses shared by a plurality of bus masters when use requests compete with each other.

  In general, when multiple bus masters share a common bus, if common bus use requests from these multiple bus masters compete, it is necessary to perform arbitration (bus arbitration) to which bus master is given the bus use right. As a typical method of arbitration, a fixed priority method and a round robin method are known. In the fixed priority method, the priority order of bus masters to which a bus use right is given is determined in advance, and a bus master having a higher priority always obtains the bus use right. On the other hand, the round robin method is such that the priority order of each bus master is updated (rounded) every arbitration, and the order of the bus masters to which the bus use right is given changes. At present, a method combining both is also common.

  However, if the data transfer using the common bus becomes very crowded, the fixed bus priority method and the round robin method will use the bus for low-level bus masters with low priority. There is a risk that it will be difficult to acquire the right. For example, when data transfer becomes congested, there is a possibility that a low-level bus master cannot obtain the right to use the bus in the fixed priority method. Further, in the round robin method, the turn goes to the low-level bus master, but there is no guarantee that the bus master can execute the data transfer because the data transfer is overcrowded.

  Therefore, in recent years, the followings have been proposed in order to realize more flexible and appropriate bus arbitration. In other words, the timeout value for each bus master is compared with the actual waiting time to temporarily raise the rank of the low-level bus master, thereby preventing a timeout due to the waiting of the bus master having a low priority ( For example, refer to Patent Document 1), by controlling the priority of bus acquisition by weighting according to the time until request generation and priority order, for example, improve the bus usage efficiency (see Patent Document 2, for example), or a bus master can When the use of a bus master is started, time measurement of the mask time addressed to that bus master is started, and during that time, priority is given to other bus masters that have not started clocking, so that the bus master occupies a bus that has long continuous use. Has been proposed (see, for example, Patent Document 3). In addition, the priority of bus arbitration is prepared as a register bit, which is shifted each time an access occurs, so that the master with low priority can be given the bus right within a certain time. (For example, refer to Patent Document 4) has been proposed.

JP-A-8-314852 JP-A-10-27156 JP 2000-259556 A JP 2001-84219 A

  However, in the case of performing management by time as disclosed in Patent Documents 1 to 3 described above, it is necessary to prepare a time measurement counter for the bus master, which complicates the device configuration and increases the device cost. Etc. will be invited. Furthermore, if time management is uniformly performed, for example, the right to use a bus is granted to a type of bus master that transfers an unnecessarily large amount of data. There is a risk that the right will not be granted. Furthermore, if a low-level bus master is incorporated, the bandwidth is limited with respect to the high-level bus master. In addition, in the method having a plurality of priorities as disclosed in Patent Document 4 described above, there is a possibility that flexible and fine-tuned arbitration can be performed, but for this purpose, a table that only performs fine-tuned arbitration must be prepared. As a result, the apparatus configuration becomes complicated and the apparatus cost increases. Furthermore, it is very difficult to prepare a table corresponding to various combinations of bus masters and to perform effective switching.

  In the past, there were only two types of bus masters: a high-speed device that required high throughput or a low-speed device that could be low-throughput, but recently, for example, a serial bus host that supports USB (Universal Serial Bus) connection. There is a bus master having a characteristic different from the conventional one, such as a controller, which requires a certain amount of transfer for a certain period while being low speed. For such bus masters, in addition to actual data transfer using the bus master's own time frame, it includes operations that are not actual data transfer such as memory polling using DMA (Direct Memory Access). If it does, there is a possibility that the usage rate of the entire bus may be reduced.

  In this way, in the conventional bus arbitration, while avoiding a decrease in the usage rate of the entire common bus, realizing a flexible and appropriate bus arbitration, such as appropriately giving the bus use right to a low-level bus master, It is not always possible to achieve both the complexity of the configuration of the data transfer processing apparatus that performs the arbitration and the avoidance of an increase in apparatus cost.

  Therefore, the present invention can achieve both the realization of flexible and appropriate bus arbitration, which is not limited to low-level master rescue, and the avoidance of complicated device configuration and increased device cost. An object is to provide a data transfer processing device.

  The present invention provides a data transfer processing device devised to achieve the above object, a common bus, a plurality of bus masters that perform data transfer using the common bus, and a common bus use from the plurality of bus masters A bus arbiter that performs arbitration for a request based on a preset priority, and as a priority of a bus master among the plurality of bus masters, any one of a plurality of different priorities set for the bus master And a request switching means for selecting one and periodically switching the selection.

  According to the data transfer processing device having the above-described configuration, the bus arbiter arbitrates for a plurality of bus masters based on a preset priority order. Among a plurality of bus masters arbitrated by the bus arbiter, The request switching means selects one of a plurality of different priorities, and the selection is periodically switched. Therefore, for a certain bus master, the priority is switched periodically, so that it is possible to secure an intermediate bandwidth that is neither high-speed nor low-speed if you look at the switch over several periods. Become.

In the data transfer processing device of the present invention, a plurality of different priorities are periodically switched for a certain bus master, so that it is possible to secure an intermediate bandwidth and avoid a decrease in the usage rate of the entire common bus. Thus, it is possible to appropriately grant the bus use right to the certain bus master. That is, the bus arbiter can perform flexible and appropriate bus arbitration. In addition, even in such a case, there is no influence on a bus master other than a certain bus master (particularly a high-level master). As a result, it is possible to deal with a new characteristic device such as one corresponding to USB connection without breaking the balance of the existing system.
Also, even if flexible and appropriate bus arbitration is realized, it is not necessary to have a timer function or a table with a huge amount of data. Therefore, it is possible to realize with a simple apparatus configuration, and the apparatus configuration is not complicated and the apparatus cost is not increased.
As described above, according to the present invention, it is possible to achieve both the realization of flexible and appropriate bus arbitration and the avoidance of the complexity of the device configuration and the increase of the device cost.

  The data transfer processing device according to the present invention will be described below with reference to the drawings.

  First, a schematic configuration of the data transfer processing device will be described. FIG. 1 is a schematic diagram illustrating a schematic configuration example of a data transfer processing device. As shown in the figure, the data transfer processing device described here includes a common bus 1, a plurality of bus masters A to Z, a bus arbiter 2, a mode setting register 3, a request switching means 4, an interval counter 5, And an interval register 6.

  The common bus 1 functions as a common signal path between various devices such as the bus masters A to Z, a memory (not shown), and an I / O (Input / Output) device. As a typical example, for example, PCISIG Examples are those based on the PCI (Peripheral Component Interconnect) standard established by (Peripheral Component Interconnect Special Interest Group).

  Each of the bus masters A to Z performs data transfer between various devices using the common bus 1 like a DMA (Direct Memory Access) controller, for example. More specifically, in order to transfer data between various devices, a bus request signal is transmitted to the bus arbiter 2, and when a bus permission signal is received from the bus arbiter 2, data transfer using the common bus 1 is started. The transmission of the bus request signal is stopped when the data transfer is completed.

  The bus arbiter 2 performs arbitration with respect to a bus request signal that is a request for using the common bus 1 from each of the bus masters A to Z, that is, arbitrates the bus and transmits a bus permission signal that is a result of the arbitration. However, the bus arbiter 2 performs bus arbitration based on a preset priority order. The priority order may be fixed or variable. In other words, the bus arbiter 2 may correspond to the fixed priority method, may correspond to the round robin method, or corresponds to a combination of the fixed priority method and the round robin method. You may do it. Note that the details of the arbitration by the bus arbiter 2 are the same as in the prior art, and the description thereof is omitted here.

  The mode setting register 3 is a register that can set an operation mode in the bus arbiter 2, in particular, a priority order based on the bus arbiter 2 performing the arbitration of the bus. By changing the information stored in the mode setting register 3, the operation mode of the bus arbiter 2 can be changed. Note that the information holding function, the information writing function, and the like in the mode setting register 3 are omitted here because known techniques may be used.

  The request switching means 4 is a characteristic component of the data transfer processing device described in the present embodiment, and is arranged between a bus master A and a bus arbiter 2 among the bus masters A to Z. As the priority order, the user selects one of a plurality of different priority orders and periodically switches the selection. Specifically, the connection between the bus request signal line and bus permission signal line connected to a certain bus master A and the terminals REQ0 to REQ2 and GNT0 to GNT2 for these signal lines in the bus arbiter 2 is switched and switched. . However, it is assumed that the priority levels of the terminals REQ0 to REQ2 and GNT0 to GNT2 are different from each other. For example, if the priority is divided into three groups of high, medium, and low levels, three terminals REQ0 to REQ2 and GNT0 to GNT2 are assigned to all groups, respectively. Is secured. That is, the request switching means 4, that is, in the request switching means 4, the connection state between the bus master A and the bus arbiter 2 is switched, so that the priority order of the bus master A is selectively switched. Yes. The request switching means 4 can be realized by hardware such as a switching circuit, but it can also be realized by software by causing a CPU (Central Processing Unit) or the like to execute a predetermined program.

  When the request switching means 4 performs switching, the interval counter 5 counts the system clock, etc., at that point in time, and when the count reaches the set value INT_CTR, stops counting and requests that effect. In addition to notifying the switching means 4, the count number is reset to "0" and a new count is started again. Based on the notification from the interval counter 5, the request switching means 4 performs periodic selection switching (switching).

  The interval register 6 is set in advance with a set value INT_CTR at which the interval counter 5 stops counting. However, a plurality (for example, three) of set values INT_CTR1 to INT_CTR3 are set in the interval register 6, and these set values INT_CTR1 to INT_CTR3 are sequentially switched and loaded into the interval counter 5. Thus, every time the system counter or the like counts, the interval counter 5 uses different set values INT_CTR1 to INT_CTR3 as the count number to stop the count.

  As described above, the interval counter 5 and the interval register 6 are used as the interval variable means of the present invention that makes the selection switching (switching) interval periodically performed by the request switching means 4 variable so as to vary for each selection switching. It functions.

  Here, the case where the request switching means 4, the interval counter 5 and the interval register 6 are provided corresponding to one bus master A among the bus masters A to Z is shown as an example. Correspondingly, a plurality of request switching means 4 and the like may be provided. In this case, however, it is assumed that one bus master A to Z always corresponds to one request switching means 4.

  Next, an example of processing operation in the data transfer processing device configured as described above will be described.

  For example, when the bus masters A to Z have characteristics that require a certain amount of data transfer for a certain period of time, as in the case of supporting USB connection, the priority of the master is given. If the order is set high, the usage rate of the entire bus may be reduced. That is, other masters (especially masters having a high priority) are also affected. Also, for example, in the case of supporting USB connection, if the bus state is managed by time (see, for example, Patent Documents 1 to 3), a bus use right is granted to a bus master that transfers an unnecessarily large amount of data. As a result, there is a risk that the right to use the bus may not be given to a bus master having necessary data transfer even in a short time. Further, in the bus arbiter 2 to which a plurality of bus masters A to Z are connected, if the priority order for each of the bus masters A to Z is dynamically changed (see, for example, Patent Document 4), a table corresponding only to this. It will be necessary to prepare the device, and the device configuration for this will be very complicated.

  Therefore, in the data transfer processing device described in the present embodiment, one of the bus masters A to Z has a characteristic that requires a certain amount of data transfer for a certain period, for example, at a low speed. On the other hand, in order to realize arbitration that can ensure the right to use the common bus 1 smoothly, the request switching means 4 periodically switches and switches the priority order of the bus master A. An intermediate bandwidth that is neither high-speed nor low-speed is secured with a simple device configuration without changing the priority of (especially a high-level master).

  Specifically, the request switching means 4 is connected to three terminals REQ0 to REQ2 and GNT0 to GNT2 corresponding to each group of the high / mid / low level on the bus arbiter 2 side. Switching is performed so as to ensure a connection between the terminal REQ0 and GNT0 of level) and the bus master A. Then, every time the count in the interval counter 5 reaches the set values INT_CTR1 to INT_CTR3, the connection state between the bus master A and the bus arbiter 2 is switched in the order of, for example, High level → Mid level → Low level. However, the priority selection is switched in the reverse order, such as Low level → Mid level → High level, instead of switching from the highest order to the lowest order, such as High level → Mid level → Low level. You may do it. In any case, for example, state information can be used as a switching technique for level transition. The state information is composed of flip-flops, and changes state whenever the counter value reaches each count value. By using this signal as a mask signal, even if the request switching means 4 is connected to the three terminals REQ0 to REQ2 and GNT0 to GNT2, signals other than one selected from them are exchanged. It is possible to realize exclusive signal control.

  FIG. 2 is a state transition diagram showing a specific example when priority selection switching in the data transfer processing device is applied to the round robin method. As shown in the figure, here, in three groups of three levels of High / Mid / Low levels, the bus master B belongs to the High level group, the bus master C belongs to the Mid level group, and the bus master Z belongs to the Low level group. The round robin method set as described above will be described as an example. For the bus master A, high / mid / low levels are set as priorities (the terminals REQ0 to REQ2 and GNT0 to GNT2 correspond to the high / mid / low levels), respectively. Assume that the request switching means 4 selects one of them.

  In the case of the round robin method with such setting, when attention is paid to the bus master A, the use permission frequency of the common bus 1 changes as described below.

  The connection between the high level terminals REQ0 and GNT0, which is the default of the request switching means 4, and the bus master A is ensured until the count value by the interval counter 5 reaches the first set value INT_CTR1 from the start of the operation. Therefore, the priority order for the right to use the common bus 1 is “B” belonging to the high level group → “A” belonging to the high level group → “C” belonging to the mid level group → high The transition of “B” belonging to the level group → “A” belonging to the high level group → “Z” belonging to the low level group is repeated. Therefore, even when each of the bus masters A to Z transmits a bus request signal to the bus arbiter 2, the bus master A can acquire the right to use the common bus 1 at a rate of once every three times. Become.

  When the count number by the interval counter 5 reaches the set value INT_CTR1, the request switching means 4 performs switching so that the connection between the Mid level terminals REQ1 and GNT1 and the bus master A is secured. From the time of reaching INT_CTR1 to the time of reaching the set value INT_CTR2, the priority for the usage right of the common bus 1 is “B” belonging to the High level group → “C” belonging to the Mid level group → High The transition in the order of “B” belonging to the level group → “A” belonging to the Mid level group → “B” belonging to the High level group → “Z” belonging to the Low level group is repeated. Accordingly, when each bus master A to Z transmits a bus request signal to the bus arbiter 2, the bus master A can acquire the right to use the common bus 1 once every six times.

  When the count number by the interval counter 5 reaches the set value INT_CTR2, the request switching means 4 performs switching so as to ensure the connection between the low-level terminals REQ2 and GNT2 and the bus master A. Prior to reaching the set value INT_CTR3 after reaching INT_CTR1 + set value INT_CTR2, the priority level for the right to use the common bus 1 is high until the count reaches the set value INT_CTR2. “B” belonging to the group of “→” “C” belonging to the group of the Mid level → “B” belonging to the group of the High level → “Z” belonging to the group of the Low level → “B” belonging to the group of the High level → Mid level The transition in the order of “C” belonging to this group → “B” belonging to the high level group → “A” belonging to the low level group is repeated. Accordingly, when each bus master A to Z transmits a bus request signal to the bus arbiter 2, the bus master A can acquire the right to use the common bus 1 once every eight times.

  Thereafter, the request switching means 4 performs switching again so as to ensure the connection between the high level terminals REQ0 and GNT0 and the bus master A, so that the count number is set to the set value INT_CTR1 + set value INT_CTR2 + set value INT_CTR3. After reaching the setting value INT_CTR1, the bus master A can acquire the right to use the common bus 1 at a rate of once every three times as described above. It will be. It should be noted that such processing operations are repeated not only when the switching is performed in the order of High level → Mid level → Low level as described above, but also when switching is performed in the reverse order.

  FIG. 3 is a state transition diagram showing a specific example when the selection switching in the data transfer processing device is applied to the fixed priority method. As shown in the figure, here, each bus master A to Z is connected to the bus master A> bus master C> Mid level terminals REQ1 and GNT1 in a state of being connected to the bus master B> High level terminals REQ0 and GNT0. A fixed priority method in which priorities are set in the order of bus master A in the state of being connected to bus master A> bus master Z> low level terminals REQ2 and GNT2 will be described as an example.

  In the case of the fixed priority order method set as described above, when attention is paid to the bus master A, the use permission frequency of the common bus 1 changes as described below.

  The connection between the high level terminals REQ0 and GNT0, which is the default of the request switching means 4, and the bus master A is ensured until the count value by the interval counter 5 reaches the first set value INT_CTR1 from the start of the operation. Thus, the priority order of the bus master A exists between the bus master B and the bus master C. Therefore, even if each of the bus masters A to Z transmits a bus request signal to the bus arbiter 2, the bus master A acquires the right to use the common bus 1 if there is no bus request signal from the bus master B. Is possible.

  When the count number by the interval counter 5 reaches the set value INT_CTR1, the request switching means 4 performs switching so that the connection between the Mid level terminals REQ1 and GNT1 and the bus master A is secured. The priority of the bus master A exists between the bus master C and the bus master Z until the set value INT_CTR2 is reached after reaching the INT_CTR1. Therefore, even when each bus master A to Z transmits a bus request signal to the bus arbiter 2, the bus master A acquires the right to use the common bus 1 if there is no bus request signal from the bus masters B and C. It becomes possible to do.

  When the count number by the interval counter 5 reaches the set value INT_CTR2, the request switching means 4 performs switching so as to ensure the connection between the low-level terminals REQ2 and GNT2 and the bus master A. The bus master A has a lower priority than the bus master Z after reaching INT_CTR1 + set value INT_CTR2 until reaching the set value INT_CTR3. Therefore, the bus master A can acquire the right to use the common bus 1 only when there is no bus request signal from any of the bus masters B to Z.

  Thereafter, the request switching means 4 performs switching again so as to ensure the connection between the high level terminals REQ0 and GNT0 and the bus master A, so that the count number is set to the set value INT_CTR1 + set value INT_CTR2 + set value INT_CTR3. After reaching the setting value INT_CTR1, the bus master A can acquire the right to use the common bus 1 if there is no bus request signal from the bus master B as described above. Will be repeated. It should be noted that such processing operations are repeated not only when the switching is performed in the order of High level → Mid level → Low level as described above, but also when switching is performed in the reverse order.

  FIG. 4 is a state transition diagram showing a specific example when the selection switching in the data transfer processing device is applied to a combination of the round robin method and the fixed priority method. As shown in the figure, here, in three groups of three levels of High / Mid / Low levels, the bus master B belongs to the High level group, the bus master C belongs to the Mid level group, and the bus master Z belongs to the Low level group. A case where the round robin method set in this way and the fixed priority method in which the priority order is set in the order of high level group> mid level group> low level group will be described as an example. For the bus master A, high / mid / low levels are set as priorities (the terminals REQ0 to REQ2 and GNT0 to GNT2 correspond to the high / mid / low levels), respectively. Assume that the request switching means 4 selects one of them.

  In the case of such a combination method of setting, when attention is paid to the bus master A, the use permission frequency of the common bus 1 changes as described below.

  The connection between the high level terminals REQ0 and GNT0, which is the default of the request switching means 4, and the bus master A is ensured until the count value by the interval counter 5 reaches the first set value INT_CTR1 from the start of the operation. Thus, the switching of the bus master A belongs to a group having a high level. Therefore, the priority order for the right to use the common bus 1 repeats the transition of “B” belonging to the high level group → “A” belonging to the high level group, and the bus request signals from the bus masters A and B are transmitted. Only when there is not, the bus master C or the bus master Z can acquire the right to use the common bus 1.

  When the count number by the interval counter 5 reaches the set value INT_CTR1, the request switching means 4 performs switching so that the connection between the Mid level terminals REQ1 and GNT1 and the bus master A is secured. The bus master A belongs to the group of the Mid level from the arrival at INT_CTR1 until the set value INT_CTR2 is reached. Therefore, if there is no bus request signal from the bus master B, the priority order of the right to use the common bus 1 repeats the transition of “C” belonging to the Mid level group → “A” belonging to the Mid level group. Only when there is no bus request signal from any of the bus masters A, B, C, the bus master Z can acquire the right to use the common bus 1.

  When the count number by the interval counter 5 reaches the set value INT_CTR2, the request switching means 4 performs switching so as to ensure the connection between the low-level terminals REQ2 and GNT2 and the bus master A. The bus master A belongs to the low-level group from when it reaches INT_CTR1 + set value INT_CTR2 until it reaches the set value INT_CTR3. Accordingly, when there is no bus request signal from any of the bus masters B and C, the priority order for the right to use the common bus 1 is “Z” belonging to the low level group → “A” belonging to the low level group. The order transition will be repeated.

  Thereafter, the request switching means 4 performs switching again so as to ensure the connection between the high level terminals REQ0 and GNT0 and the bus master A, so that the count number is set to the set value INT_CTR1 + set value INT_CTR2 + set value INT_CTR3. Until the set value INT_CTR1 is reached after the arrival, the order of priority regarding the right to use the common bus 1 repeats in the order of “B” belonging to the High level group to “A” belonging to the High level group. Thereafter, the processing operation described above is repeated. It should be noted that such processing operations are repeated not only when the switching is performed in the order of High level → Mid level → Low level as described above, but also when switching is performed in the reverse order.

  As described above, in the data transfer processing device described in the present embodiment, the bus arbiter 2 performs arbitration for the bus request signals from the plurality of bus masters A to Z, but the arbitration by the bus arbiter 2 is fixed priority method and round robin method. Even when any one of these combinations is applied, for the bus master A, the request switching means 4 selects one of a plurality of different priorities, and the selection is switched. It is supposed to be done regularly. Therefore, since the priority of the bus master A is periodically switched regardless of the arbitration method, the intermediate band is neither high-speed nor low-speed when the switching is repeated several times. It becomes possible to secure the width.

  That is, in the data transfer processing device according to the present embodiment, a plurality of different priorities are periodically switched for a certain bus master A, so that an intermediate bandwidth can be secured, and even if the bus becomes overcrowded, the data transfer processing device fails. As a result, it is possible to appropriately give a bus use right to a certain bus master A while avoiding a decrease in the usage rate of the common bus 1 as a result. As a result, the bus arbiter 2 is flexible. It is possible to perform appropriate bus arbitration. Moreover, even in that case, the bus masters B to C other than a certain bus master A (particularly high-level ones) are not affected. This makes it suitable for new characteristic devices such as those that support USB connection, such as those that support low speed, but have limitations that terminate control in a certain time frame, without disrupting the balance of the existing system. Arbitration can be realized.

  Furthermore, even if flexible and appropriate bus arbitration is realized, there is no need for a timer function or an enormous amount of data table, and only the request switching means 4 for changing the priority (for example, switching) is provided. Therefore, it is possible to realize with a simple device configuration. It is also easy to realize the data transfer processing device of this embodiment in addition to the existing configuration. Therefore, the apparatus configuration is not complicated and the apparatus cost is not increased.

  As described above, according to the data transfer processing device of this embodiment, it is possible to achieve both flexible and appropriate bus arbitration and avoidance of complicated device configuration and increased device cost. It becomes.

  In the data transfer processing device according to the present embodiment, the request switching means 4 not only periodically switches the priority order of the bus master A but also sets a plurality of set values INT_CTR1 to INT_CTR3 set in the interval register 6. Based on the above, the interval of the selection switching performed periodically, that is, the count number by the interval counter 5 is different for each selection switching. That is, by providing the interval counter 5 and the interval register 6, the selection switching interval (count number) is variable. This is because when the request switching means 4 performs selection switching to secure an intermediate bandwidth for the bus master A, the intermediate bandwidth is determined depending on the setting of a plurality of setting values INT_CTR1 to INT_CTR3. Means that. Therefore, if the number of counts is variable for each selection change, the intermediate bandwidth size can be adjusted appropriately depending on the setting values INT_CTR1 to INT_CTR3, which is very important for realizing flexible and appropriate bus arbitration. This is preferable.

  Further, as described above, the data transfer processing device according to the present embodiment can be applied to any of the fixed priority method, the round robin method, or a combination thereof. And, when applied to the fixed priority method, it is possible to ensure the master's bandwidth required for high speed, and when applied to the round robin method, each master can obtain a fair bus right. When applied to the above, it is possible to directly enjoy the advantages of the respective systems, such as making it possible for each master to obtain a fair bus right while securing the bandwidth of a master that requires high speed.

  In the present embodiment, the preferred specific examples of the present invention have been described. However, the present invention is not limited to the contents, and can be appropriately changed without departing from the gist thereof. For example, in the present embodiment, the case where the bus arbiter 2 performs arbitration by the fixed priority method, the round robin method, or a combination thereof is taken as an example, but the same is true even when using other known techniques. It is conceivable to apply the present invention to the above.

  In the present embodiment, the request switching unit 4 has been described as an example in which the priority switching for the bus master A is switched in order from the highest to the lowest or vice versa. The switching order may be determined in advance according to the characteristics of the target bus master A, that is, whether the bus usage frequency gradually decreases or increases, and the higher order is necessarily required. There is no limitation to the order from low to low or vice versa.

It is a schematic diagram which shows the schematic structural example of the data transfer processing apparatus which concerns on this invention. It is a state transition diagram which shows one specific example at the time of applying priority selection switching in the data transfer processing apparatus which concerns on this invention to a round robin system. It is a state transition diagram which shows one specific example at the time of applying priority selection switching in the data transfer processing apparatus which concerns on this invention to a fixed priority system. It is a state transition diagram which shows a specific example at the time of applying the selection switching of the priority in the data transfer processing apparatus which concerns on this invention to what combined the round robin system and the fixed priority system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Common bus, 2 ... Bus arbiter, 3 ... Mode setting register, 4 ... Request switching means, A, B, C, Z ... Bus master, 5 ... Interval counter, 6 ... Interval register

Claims (6)

A common bus,
A plurality of bus masters performing data transfer using the common bus;
A bus arbiter that performs arbitration for a common bus use request from the plurality of bus masters based on a preset priority;
As a priority order of a certain bus master among the plurality of bus masters, one of a plurality of different priorities set for the certain bus master is selected, and the request switching is performed periodically to switch the selection. And a data transfer processing device. 2. The data transfer processing device according to claim 1, further comprising interval changing means for changing the interval of selection switching periodically performed by the request switching means so as to be different for each selection switching. The data transfer processing device according to claim 1, 2, or 3, wherein the priority order based on the bus arbiter is based on a fixed priority order system. The data transfer processing device according to claim 1, 2, or 3, wherein the priority order based on the bus arbiter is based on a round robin method. 4. The data transfer processing device according to claim 1, wherein the priority order based on the bus arbiter is based on a combination of a fixed priority method and a round robin method. 6. The request switching means performs selection switching of priority order in order from the highest order to the lowest order, or vice versa. The data transfer processing device described in 1.

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