JP2006201832A - Data transfer processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reconcile the flexible and appropriate arbitration of a bus and the avoidance of the complication of an apparatus constitution and an increase in apparatus cost and the like. <P>SOLUTION: The data transfer processing apparatus is comprised of a common bus 1, a plurality of bus masters A1 to Z for transferring data by using the common bus 1, a bus arbiter 2 for arbitrating requests to use the common bus from the plurality of bus masters A1 to Z based on an order of priority which is set beforehand and a request switching means 4 for switching the order of priority between the bus masters A1, A2 which are included in the plurality of bus masters A1 to Z at timing according to a data transfer method using the bus masters A1, A2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data transfer processing device having a function of arbitrating for common buses shared by a plurality of bus masters when use requests compete with each other.

  In general, when multiple bus masters share a common bus, if common bus use requests from these multiple bus masters compete, it is necessary to perform arbitration (bus arbitration) to which bus master is given the bus use right. As a typical method of arbitration, a fixed priority method and a round robin method are known. In the fixed priority method, the priority order of bus masters to which a bus use right is given is determined in advance, and a bus master having a higher priority always obtains the bus use right. On the other hand, the round robin method is such that the priority order of each bus master is updated (rounded) every arbitration, and the order of the bus masters to which the bus use right is given changes. At present, a method combining both is also common.

  However, if the data transfer using the common bus becomes very crowded, the fixed bus priority method and the round robin method will use the bus for low-level bus masters with low priority. There is a risk that it will be difficult to acquire the right. For example, when data transfer becomes congested, there is a possibility that a low-level bus master cannot obtain the right to use the bus in the fixed priority method. Further, in the round robin method, the turn goes to the low-level bus master, but there is no guarantee that the bus master can execute the data transfer because the data transfer is overcrowded.

  Therefore, in recent years, in order to realize more flexible and appropriate bus arbitration, a bus master that needs to transfer data within a certain period of time is monitored with a timer, and if it is not selected for a certain period, the priority of that bus master is The priority is changed so as to be the highest (see, for example, Patent Document 1), or the usage priority rate is dynamically changed according to the bus occupation time so that the ratio of the bus occupation time by each bus master becomes constant. It has been proposed to prevent long-term occupancy by a bus master having a long access execution time and frequent frequency (see, for example, Patent Document 2). In addition, the priority of bus arbitration is prepared as a register bit, which is shifted each time an access occurs, so that the master with low priority can be given the bus right within a certain time. (See, for example, Patent Document 3) and a self-learning function that autonomously changes the priority according to the usage status of each bus master. If the usage rate increases even if the priority is low, the priority is increased. Increasing the height (for example, see Patent Document 4) has been proposed.

Japanese Patent Laid-Open No. 9-91194 JP 2002-91903 A JP 2001-84219 A JP 2003-150537 A

  However, in the method of performing management based on time as disclosed in Patent Document 1 or Patent Document 2 described above, it is necessary to prepare a time measurement counter for the bus master, which complicates the device configuration and reduces the device cost. Will be raised. Furthermore, if the management is performed uniformly in time, for example, there is a possibility that the right to use the bus may not be given to a bus master having necessary data transfer even in a short time. Further, in the method having a plurality of priorities as disclosed in Patent Document 3 described above, there is a possibility that flexible and fine-tuned arbitration can be performed. As a result, the apparatus configuration becomes complicated and the apparatus cost increases. Furthermore, it is difficult to prepare a table corresponding to various combinations of bus masters. Moreover, in the method of calculating the number of bus acquisitions and the like autonomously changing the priority order as disclosed in Patent Document 4 described above, in order to realize a self-learning function for autonomously changing the priority order, it is enormous. A very complicated circuit (device configuration) is required.

In other words, conventional bus arbitration realizes flexible and appropriate bus arbitration, such as giving the right to use a bus to a low-level bus master while avoiding a decrease in the usage rate of the entire common bus. It is difficult to achieve both the complexity of the device configuration of the data transfer processing device that performs and avoiding an increase in device cost.
SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer processing device capable of realizing both flexible and appropriate bus arbitration and avoiding complicated device configuration and increased device cost. And

  The present invention provides a data transfer processing device devised to achieve the above object, a common bus, a plurality of bus masters that perform data transfer using the common bus, and a common bus use from the plurality of bus masters A bus arbiter that performs arbitration with respect to a request based on a preset priority, and a data transfer method in which at least two bus masters use the common bus for at least two bus masters that are part of the plurality of bus masters And a request switching means for switching the priority order between the at least two bus masters at a timing determined according to the above.

According to the data transfer processing device having the above-described configuration, the bus arbiter performs arbitration for a plurality of bus masters based on a preset priority, but a part of the plurality of bus masters arbitrated by the bus arbiter, that is, the plurality of bus masters. For at least two bus masters that are not all, the request switching means switches the priority order at a timing determined in accordance with the data transfer method by the bus master.
Here, the “data transfer method” is a data transfer method that is compatible with both of the at least two bus masters. Specifically, for example, a half-duplex communication method that is one of bidirectional communication methods. Is mentioned. The “timing determined according to the data transfer method” refers to a predetermined timing suitable for the contents of the data transfer method. For example, if the data transfer method is a half-duplex communication method, The timing at which the one-way data communication out of the two directions ends is given.
If the priorities of the at least two bus masters are interchanged at such timing, for example, in the case of a half-duplex communication method, when one-way data communication is completed, the priority order of the bus masters performing data communication in the opposite direction is In other words, the priority order of each bus master is flexibly switched so as to be suitable for the data transfer method using the at least two bus masters.

In the data transfer processing device of the present invention, the priority order of only a part of a plurality of bus masters is switched at a timing determined according to the data transfer method, so that other bus masters (particularly high-level masters). There is no effect on. In addition, the priority of the at least two bus masters that are part of the master is flexibly switched so as to be suitable for the data transfer method, so that it is possible to acquire the right to use the bus even when the level is low. Will be. That is, the bus arbiter can perform flexible and appropriate bus arbitration.
Moreover, even in such a case, a simple device configuration can be provided because it does not require a timer function or a table with a huge amount of data, and only has a request switching means for switching the priority order (for example, switching). Therefore, it is possible to achieve the above-described configuration, and the apparatus configuration is not complicated and the apparatus cost is not increased.
As described above, according to the present invention, it is possible to achieve both the realization of flexible and appropriate bus arbitration and the avoidance of the complexity of the device configuration and the increase of the device cost.

  The data transfer processing device according to the present invention will be described below with reference to the drawings.

  First, a schematic configuration of the data transfer processing device will be described. FIG. 1 is a schematic diagram illustrating a schematic configuration example of a data transfer processing device. As shown in the figure, the data transfer processing device described here includes a common bus 1, a plurality of bus masters A1 to Z, a bus arbiter 2, a mode setting register 3, and a request switching means 4. ing.

  The common bus 1 functions as a common signal path between various devices such as the bus masters A1 to Z, a memory (not shown), and an I / O (Input / Output) device. As a typical example, for example, PCISIG Examples are those based on the PCI (Peripheral Component Interconnect) standard established by (Peripheral Component Interconnect Special Interest Group).

  Each of the bus masters A1 to Z performs data transfer between various devices using the common bus 1 like a DMA (Direct Memory Access) controller, for example. More specifically, in order to transfer data between various devices, a bus request signal is transmitted to the bus arbiter 2, and when a bus permission signal is received from the bus arbiter 2, data transfer using the common bus 1 is started. The transmission of the bus request signal is stopped when the data transfer is completed.

  Of these, the bus masters A1 and A2 are assumed to perform data transmission or data reception using the common bus 1 by the half-duplex communication method. The half-duplex communication method refers to a communication method in which data cannot be transmitted or received from both sides at the same time and communication from only one direction is possible. In such a half-duplex communication method, the direction of communication is periodically switched, that is, data transmission and data reception are alternately repeated, but it is easy to perform data communication in a single band. There is. That is, the bus masters A1 and A2 perform paired data transfer, one of which alternately performs data transmission using the common bus 1 and the other alternately performs data reception using the common bus 1. It has become

  The bus arbiter 2 performs arbitration with respect to a bus request signal that is a request for using the common bus 1 from each of the bus masters A1 to Z, that is, arbitrates the bus and transmits a bus permission signal that is a result of the arbitration. However, the bus arbiter 2 performs bus arbitration based on a preset priority order. The priority order may be fixed or variable. In other words, the bus arbiter 2 may correspond to the fixed priority method, may correspond to the round robin method, or corresponds to a combination of the fixed priority method and the round robin method. You may do it. Note that the details of the arbitration by the bus arbiter 2 are the same as in the prior art, and the description thereof is omitted here.

  The mode setting register 3 is a register that can set an operation mode in the bus arbiter 2, in particular, a priority order based on the bus arbiter 2 performing the arbitration of the bus. By changing the information stored in the mode setting register 3, the operation mode of the bus arbiter 2 can be changed. Note that the information holding function, the information writing function, and the like in the mode setting register 3 are omitted here because known techniques may be used.

  The request switching unit 4 is a characteristic component of the data transfer processing device described in the present embodiment, and is arranged between the bus masters A1 and A2 that are part of each of the bus masters A1 to Z and the bus arbiter 2, The priorities of these two bus masters A1 and A2 are switched. Specifically, the bus request signal and bus permission signal connected to the bus masters A1 and A2 and the signal line terminals in the bus arbiter 2 (however, the terminals having different priority levels) are connected to the bus master. Switching is performed between A1 and A2. That is, the request switching means 4 switches the connection state between the bus masters A1 and A2 and the bus arbiter 2, so that the bus arbiter 2 performs the bus arbitration for these two bus masters A1 and A2. The order of priority is changed. The request switching means 4 can be realized by hardware such as a switching circuit, but it can also be realized by software by causing a CPU (Central Processing Unit) or the like to execute a predetermined program.

Here, the case where two bus masters A1 and A2 are connected to the request switching means 4 is shown as an example, but if the connection state can be switched, three or more bus masters are connected. Also good. However, the combination of the bus masters A1 and A2 connected to the request switching unit 4 corresponds to the same data transfer method and is paired when performing data transfer using the common bus 1.
In addition, here, a case where one request switching means 4 is provided is shown as an example, but if there are a plurality of pairs of bus masters for performing data transfer, a request corresponding to each pair is provided. A plurality of switching means 4 may be provided.
The bus masters A1 and A2 connected to one request switching unit 4 are not part of the bus masters A1 to Z, that is, not all of the bus masters A1 to Z. In the case where a plurality of request switching means 4 are provided, it is only necessary that each of the request switching means 4 is connected to each of the bus masters A1 to Z. That is, even if all of the bus masters A1 to Z are connected to any one of the request switching means 4, it is not necessary that all of them are connected to the same request switching means 4.

  Next, an example of processing operation in the data transfer processing device configured as described above will be described.

  For example, if there is a feature in each bus master A1 to Z that requires a certain amount of data transfer for a certain period even though it is low speed, if the priority of that master is set high, The overall usage rate may be reduced. That is, other masters (especially masters having a high priority) are also affected. In addition, for example, the bus state is monitored using a timer function or the like, and if it is detected that a request does not pass for a certain period of time, it may be possible to increase the priority (for example, refer to Patent Document 1). The target master remains at a low level until the priority is changed. Furthermore, in the bus arbiter 2 to which a plurality of bus masters A1 to Z are connected, if the priority order for each of the bus masters A1 to Z is dynamically changed (see, for example, Patent Documents 2 to 4), the priority order changing condition is changed. It seems that the circuit configuration to be calculated becomes very complicated.

  Therefore, in the data transfer processing device described in the present embodiment, the bus masters A1 and A2 in which a pair of data transfers exist for a certain data transfer can smoothly ensure the right to use the common bus 1. In order to realize arbitration, the request switching means 4 exchanges the priorities of the bus masters A1 and A2, thereby changing the priority of the other masters (especially high-level masters) and not being a high speed or a low speed. The bandwidth is secured with a simple device configuration.

  Specifically, in the half-duplex communication method, data transmission and data reception are repeated almost alternately, so that the request switching means 4 has a priority level among the signal line terminals for the bus masters A1 and A2 of the bus arbiter 2. When the data transfer by the bus master A1 or the bus master A2 connected to the higher terminal (hereinafter referred to as “level high side terminal”) is completed, the connection state between the bus masters A1 and A2 and the bus arbiter 2 is switched. The order of priority for A2 is changed. That is, after executing data transfer by arbitration via the level High side terminal, the request switching means 4 connects the bus request signal and bus permission signal to the level High side terminal at the end of the data transfer. Switch to the terminal with the lower level (hereinafter referred to as the “Level Low side terminal”). However, when data transfer is executed by arbitration via the level low side terminal, the connection state is not switched even if the data transfer ends. The end of data transfer can be detected by, for example, stopping transmission of a bus request signal. However, it may be detected by using another known technique, and switching may be performed using this as a trigger. .

  FIG. 2 is a state transition diagram showing a specific example when priority switching in the data transfer processing device is applied to the fixed priority method.

  For example, as shown in FIG. 2A, when the priority is set such that the bus master A1 that transmits data> the bus master A2 that receives data (see (i) in the figure), the data transfer by the bus master A1 is performed. When the data transfer is completed, the request switching means 4 switches the connection state between the bus masters A1 and A2 and the terminals of the bus arbiter 2, and switches the priority level from bus master A2 to bus master A1 ( (See (ii) in the figure). In the half-duplex communication method, since data transmission and data reception are repeated almost alternately, when the data transfer by the bus master A1 is subsequently executed, the request switching means 4 causes each of the bus masters A1, A2 and the bus arbiter 2 to The connection state between the terminals is switched to switch the priority level from bus master A1> bus master A2 (see (iii) in the figure).

  However, for example, as shown in FIG. 2B, when the priority order is set as bus master A1> bus master A2 (see (i) in the figure), when data transfer by the bus master A2 is executed, the request The switching means 4 does not switch the connection state between the bus masters A1 and A2 and each terminal of the bus arbiter 2 even when the data transfer is completed, and keeps the priority level as bus master A1> bus master A2. (Refer to (ii) in the figure). This is because data transmission and data reception are almost alternately repeated in the half-duplex communication method. After that, when data transfer by the bus master A1 is executed, the request switching means 4 switches the connection state between the bus masters A1 and A2 and each terminal of the bus arbiter 2, and sets the priority level to bus master A1> bus master. Switch to A2 (see (iii) in the figure).

  FIG. 3 is a state transition diagram showing a specific example when priority order switching in the data transfer processing device is applied to the round robin method. Here, a round robin method set in three groups and three layers will be described as an example.

  As shown in the figure, when the priority level of the bus master A1 belongs to the middle hierarchy, and the priority level of the bus master A2 belongs to the lower hierarchy, the priority is set as bus master A1> bus master A2. (See (i) in the figure) Data transfer by the bus master A1 is executed, and when the data transfer is completed, the request switching means 4 switches the connection state between the bus masters A1 and A2 and each terminal of the bus arbiter 2. Thus, the priority level is switched from bus master A2> bus master A1 (see (ii) in the figure). As a result, the priority level of the bus master A1 belongs to the lower hierarchy, and the priority level of the bus master A2 belongs to the middle hierarchy. After that, when data transfer by the bus master A2 is executed, the request switching means 4 switches the connection state between the bus masters A1 and A2 and each terminal of the bus arbiter 2, and sets the priority level to bus master A1> bus master. Switch to A2 (see (iii) in the figure). As a result, the priority level of the bus master A1 again belongs to the middle hierarchy, and the priority level of the bus master A2 belongs to the lower hierarchy.

  As described above, in the data transfer processing device described in the present embodiment, the bus arbiter 2 performs arbitration for the bus request signals from the plurality of bus masters A1 to Z, but the two bus masters A1 and A2 that are part of them The data by arbitration via the level high side terminal of the bus arbiter 2 at a timing determined according to the data transfer method by these bus masters A1 and A2, specifically at a timing determined according to the half-duplex communication method. When the transfer is completed, the request switching means 4 switches the connection state between the bus masters A1 and A2 and each terminal of the bus arbiter 2 so that the priorities of the bus masters A1 and A2 are switched. If the priority order of the bus masters A1 and A2 is switched at such timing, for example, when the data communication in one direction is completed, the priority order of the bus masters performing data communication in the opposite direction becomes higher. The priority order for A2 is flexibly switched so as to be suitable for the half-duplex communication method which is a data transfer method executed by the bus masters A1 and A2.

  Accordingly, the priority order of these two bus masters A1 and A2 can be flexibly switched so as to be suitable for the half-duplex communication method which is the data transfer method, and therefore, when one of the priority levels is set low. Even in such a case, the possibility of acquiring the bus use right for each of the two bus masters A1 and A2 is ensured. In other words, since one of the two bus masters A1 and A2 is not masked, there is a possibility that the common bus 1 can be accessed even if one of the priority levels is lowered.

In addition, since the priority order of only two bus masters A1 and A2, that is, a part of the plurality of bus masters A1 to Z, is switched, the bus masters other than these two bus masters A1 and A2 (particularly high-level masters) The priority and bus arbitration are not affected. For example, high-level ones remain high regardless of the order of priority.
Even when it is necessary to set a high priority level for the two bus masters A1 and A2, the priority is switched so as to be suitable for the half-duplex communication method, so either one of the two systems of transmission / reception is used. Only the priority of one system needs to be set high, and the priority of other masters can be raised by one level.

  In addition, even if the priority order of the two bus masters A1 and A2 is switched, the request switching means 4 that performs switching for switching the priority order is provided without requiring a timer function or a huge data amount table. Therefore, a simple device configuration can be realized, and the device configuration is not complicated and the device cost is not increased. That is, it can be realized with an inexpensive apparatus configuration, and can be easily added to an existing circuit.

  As described above, according to the data transfer processing device of this embodiment, it is possible to achieve both flexible and appropriate bus arbitration and avoidance of complicated device configuration and increased device cost. It becomes.

  In the present embodiment, the preferred specific examples of the present invention have been described. However, the present invention is not limited to the contents, and can be appropriately changed without departing from the gist thereof. For example, in the present embodiment, the case where the bus arbiter 2 performs arbitration by the fixed priority method or the round robin method is taken as an example. However, for example, the bus arbiter 2 may be a combination of these or another known technique. The present invention can be applied in exactly the same manner.

  In this embodiment, the case where the bus masters A1 and A2 perform data transfer by the half-duplex communication method has been described as an example, but other data transfer methods can be used as long as they perform paired data transfer. You may apply. As another data transfer method, for example, a method of performing data transfer by time division can be considered. In the case of such a data transfer method, the timing determined according to the data transfer method includes a timing at which a certain amount of data communication (for example, a certain number of packets) is completed.

It is a schematic diagram which shows the schematic structural example of the data transfer processing apparatus which concerns on this invention. It is a state transition diagram which shows one specific example at the time of applying the priority order change in the data transfer processing apparatus concerning this invention to a fixed priority system. It is a state transition diagram which shows one specific example at the time of applying priority order change in the data transfer processing apparatus which concerns on this invention to a round robin system.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Common bus, 2 ... Bus arbiter, 3 ... Mode setting register, 4 ... Request switching means, A1, A2, B, Z ... Bus master

Claims (4)

A common bus,
A plurality of bus masters performing data transfer using the common bus;
A bus arbiter that performs arbitration for a common bus use request from the plurality of bus masters based on a preset priority;
For at least two bus masters that are part of the plurality of bus masters, the priority order between the at least two bus masters at a timing determined according to the data transfer method performed by the at least two bus masters using the common bus And a request switching means for replacing the data. The at least two bus masters perform data transmission or data reception using the common bus by a half-duplex communication method.
2. The request switching unit, when data transmission or data reception by one of the at least two bus masters is completed, switches the priority order between the at least two bus masters. Data transfer processing device. The data transfer processing device according to claim 1, wherein the priority order based on the bus arbiter is based on a fixed priority method. The data transfer processing device according to claim 1, wherein the priority order based on the bus arbiter is based on a round robin method.

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