JPH0778967B2 - Signal playback device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotary head type recording / reproducing apparatus such as an R-DAT (rotary head type digital audio tape recorder).

2. Description of the Related Art In recent years, digital recording technology has been applied to many fields such as sound and images, and technologies such as a CD player, R-DAT, and digital VTR have been established.

Among them, the extraction of the reproduction clock, the error correction, and the signal processing technique at the time of error detection are important points that determine the reliability of the reproduction device.

In a digital reproducing apparatus, a self-clocking system that extracts a reproduction clock based on a signal recorded on a recording medium is generally used. The self-clocking method is a method in which a change point of a reproduction signal is detected, a PLL (Phase Locked Loop) circuit generates a clock phase-synchronized with the reproduction signal, and the reproduction signal is demodulated by the clock.

Problems to be Solved by the Invention In the case of a fixed head type reproducing apparatus, since the reproduced signal is continuously obtained, the PLL keeps the locked state unless there is a long burst error, so that the reproduction clock extraction operation is stable. ing. However, in the case of the rotary head type reproducing apparatus, the reproduced signal is not always obtained continuously. For example, when two heads are mounted on a cylinder and the wrap angle of the tape with respect to the cylinder is 90 degrees, the section where the head is in contact with the tape (head touch section) is only 180 degrees and the remaining 180 degrees. The head does not hit the tape in the minute section. In this case, the playback signal cannot be obtained in the 180-degree section, so if the PLL is operating during this period, the PLL will be in an extremely unstable state and may be in a state that deviates significantly from the frequency that should be locked. It takes time to lock to the correct frequency even if the correct playback signal is input in the next head touch section,
It could cause a read error.

In view of the above problems, the present invention masks the reproduction signal supplied to the PLL in a section other than the head touch space, prevents the state of the PLL from being greatly deviated from the frequency to be originally locked, and the next head touch It is intended to provide a signal reproducing device in which the PLL is locked immediately and a normal demodulation operation can be obtained when a correct reproduction signal is input in a section.

A pre-value hold type PLL in which the output frequency is held when the input signal becomes “0” is disclosed in, for example, Japanese Patent Application No. 61-24241.
There is one shown in No. 5 "Clock recovery phase synchronization circuit".
Further, the present invention is to improve the reliability of the demodulation operation by generating the optimum mask signal not only in the standard reproduction mode in which the cylinder rotation speed is constant but also in the high speed search mode in which the cylinder rotation speed changes according to the tape speed. is there.

Means for Solving the Problems A signal reproducing apparatus of the present invention is based on a cylinder provided with a reproducing head, a cylinder rotation phase detecting means for detecting a rotation phase of the cylinder, and phase information detected by the cylinder rotation phase detecting means. The reproduction signal is generated by calculating a cylinder rotation cycle, generating a reproduction signal mask signal proportional to the cylinder rotation cycle, and generating a reproduction signal mask signal based on the cylinder rotation phase, and a reproduction signal mask signal generated by the mask signal generation section. It is constituted by gate means for masking.

The present invention has the above-described configuration to generate a mask signal proportional to the cylinder rotation cycle, thereby masking the reproduction signal supplied to the PLL even in the high-speed search mode in which the cylinder rotation cycle changes, except in the head touch section. However, the state of the PLL is prevented from being greatly deviated from the frequency that should be locked, and when the correct reproduction signal is input in the next head touch section, the PLL is quickly locked and a normal demodulation operation can be obtained.

Embodiment An embodiment in which the signal reproducing apparatus of the present invention is applied to an R-DAT (rotary head type digital audio tape recorder) will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of an R-DAT in one embodiment of the present invention.

In FIG. 1, 100a and 100b are recording / reproducing heads each having an azimuth angle of ± 20 degrees, 101 is a cylinder, 102 is a magnetic tape, and 103a and 103b are reels for winding the tape 102,
104 is a capstan for running the tape 102 at a constant speed,
105 is a recording / playback head amplifier, 106 is an equalizer for equalizing the waveform of the playback signal, 107 is a PLL (Ph for extracting the playback clock PCK for punching the playback signal out of the playback signal
ase Loocked Loop) circuit. This PLL circuit is a pre-value hold type PLL in which the output frequency is held when the input signal becomes "0". The pre-value hold type PLL is shown in Japanese Patent Application No. 61-242415, "Clock recovery phase synchronization circuit", which the applicant of the present application filed earlier. By using such a PLL circuit, if the reproduction signal is interrupted and the period during which only noise is input is known, the reproduction signal can be masked during that period.
It is possible to prevent the PLL frequency from deviating significantly. Reference numeral 108 is a modulation / demodulation unit for demodulating a reproduction signal and modulation of a recording signal, 109 is a code processor for performing error detection, correction, and generation of an error correction code, and 110 stores modulation / demodulation data, PCM data, and the like. RAM part, 111 is a playback PC
PCM control unit that performs M data interpolation processing, 112 is an A / D converter, 113 is a D / A converter, 114 is a cylinder synchronization signal R3C
P, modulation / demodulation unit 108, code processor 109, RAM unit 110, P
A timing generation unit that generates a basic clock used in the CM control unit 111, and 115 is a servo block that controls the cylinder 101, the reels 103a and 103b, and the capstan 104. 116
Is a system control unit for instructing the system mode and the like. The system control unit 116 controls the servo
The tape speed data TPSP indicating the tape speed is given to the block 115, and the sync protection unit in the modulation / demodulation unit 108 is provided with the forward protection count data corresponding to the tape speed.
Give SCOUNT.

Reference numeral 120 is a PG (Fords Generator) provided to detect the rotation phase of the cylinder 101. The PG 120 is an optically detectable mark. A PG sensor 121 detects that the PG 120 has passed. 122 is PG sensor 121 is PG
This is a cylinder rotation phase detector that generates a rotation phase pulse PGT when 120 is detected. 123 is a reproduction signal mask signal corresponding to the head touch section based on the rotation phase pulse PGT
This is a mask signal generation unit that generates RFMSK, a signal S2HSW that distinguishes the first half and the second half of the head touch section, and a signal SSP that distinguishes the area in the head touch section.

Next, the flow of signals during recording will be described.

When the system control unit 116 instructs the recording mode, the audio input AIN is input to the A / D converter 112 and the 16-bit PIN
Converted to CM data. The PCM data is input to the PCM control unit 111, sent as 8-bit data to the RAM unit 110, interleaved, and saved. The code processor 109 adds an error correction code to the PCM data saved in the RAM unit 110, generates pre-modulation data, and saves it in the RAM unit 110. After that, the modulation / demodulation unit 108 receives the modulation data from the RAM unit 110 at a predetermined timing, performs a modulation process, and generates a recording signal RFOUT. The recording signal RFOUT is supplied to the heads 100a and 100b through the head amplifier 105.

On the other hand, the servo block 115 uses the cylinder synchronization signal R3CP generated by the timing generation unit 114 as a reference to determine the cylinder 10
Controls the rotation of 1 to control the head touch section and the recording signal RFO.
The head switching signal HSW is generated at the same time as the phase with UT, and it determines which of + azimuth and -azimuth the recording current is to flow.

FIG. 2 is a timing chart showing the operation of the serve block.
It is a chart. In FIG. 2, R3CP is a cylinder synchronization signal, and the servo block controls the cylinder rotation so that the recording signal RFOUT and the head touch phase match. Also + azimuth head Hp, -azimuth head H
Generate signal HSW for switching m.

At this time, the tape 102 runs at a constant speed and a track having a uniform width is recorded.

Next, the flow of signals during standard reproduction will be described.

When the system control unit 116 instructs the reproduction mode, the cylinder 101 is controlled by the servo block 115 with R3CP as a reference, and the head touch section and the demodulation timing are synchronized, as in the case of recording.

Furthermore, tape speed is ATF (Automatic Track Findi
ng) is used to control the head to trace a track.

The head signal RFSG reproduced from the heads 100a and 100b is supplied to the equalizer 106 through the head amplifier 105 to perform waveform equalization, and then is supplied to the PLL 107 via the AND gate 124 to extract a reproduction clock and perform modulation / demodulation. It is supplied to the unit 108.

The modulation / demodulation unit 108 writes the demodulated data in the RAM unit 110. Further, the code processor 109 reads the demodulated data from the RAM unit 110 and performs error detection and error correction.
The PCM control unit 111 reads the corrected 8-bit data from the RAM unit 110, deinterleaves it, and supplies it to the D / A converter 113 as 16-bit data. In addition, interpolation processing is performed on the data determined to be uncorrectable by the code processor 109. The D / A converter 113 converts the PCM data into an audio signal A _OUT and outputs it.

Next, the signal flow during high-speed search will be described.

The signal flow during high-speed search is basically the same as the signal flow during standard reproduction. However, cylinder synchronization signal R3
Since the CP and cylinder rotation are asynchronous, the head switching signals HSW and R3CP are asynchronous.

Next, a detailed configuration of the modulation / demodulation unit 108 will be described. Third
The figure is a block diagram showing the configuration of the modulation / demodulation unit 108.

In FIG. 3, reference numeral 301 denotes an NRZI-modulated reproduction signal RFIN.
NRZI inverse conversion unit for converting RZ signal RFDT, 304 is NRZ signal RF
A sync protector that extracts the block sync signal SYNC from DT, sends a valid SYNC flag VSYNC that gives the reference timing to the playback timing generator, and protects VSYNC from occurring even if SYNC is mistakenly detected. Is. Further, the synchronization protection unit 304 outputs the synchronization loss flag SYNG when detecting the synchronization loss. Reference numeral 302 denotes an SP conversion unit that performs serial-parallel conversion of the NRZ signal by the word clock WDCK generated by the reproduction timing generation unit 305, and 303 outputs 8 bits of the SP-converted 10-bit data.
It is an 8-10 decoder which converts bit data and sets an RF error flag RFF for data that does not conform to the 8-10 modulation rule.

305 is a valid SYNC flag VS sent from the synchronization protection unit 304.
This is a reproduction timing generation unit that generates a timing for demodulation processing by a reproduction clock PCK with YNC as a reference.
The reproduction timing generation unit 305 uses the S / P conversion clock WDC.
The K / RAM unit 110 generates a reproduction word address PWAD for writing demodulated data, a RAM write request signal WRRAM, and a SYNC window SYNCW used by the synchronization protection unit 304.

Here, the block format of R-DAT is shown in FIG.
Shown in. The format of W2 is shown in FIG. 4b. The block address BLK in W2 is 7 bits in the main data area and 4 bits in the sub data area. In other words, there are 128 main data areas and 16 sub data areas per track. Sub data area 0 to 7, sub data area 2
Has 8 to 15 block addresses. Also,
MSB of W2 is a sub area flag that is set to "1" in the sub data area. FIG. 5 shows the track format of R-DAT.

Reference numeral 320 denotes the signal SSP, S2HSW representing the section containing the sub data areas 1 and 2 and the main data area, respectively, and compares the sub area flag and the block address recorded on W2. AIF ＝
This is an area flag check unit that outputs 1.

When SSP is "1", the section including the sub data area
When it is "0", it indicates the section including the main data area, and therefore the data of W1 and W2 can be regarded as highly reliable if they match because they have the same logic as the sub-area flag on W2. S2HSW is "0" in the section containing sub-data area 1 and "1" in the section containing sub-data area 2, so it has the same logic as the MSB of the block address. The data can be regarded as highly reliable. SSP
The detailed timing of S2HSW and S2HSW will be described later.

The 306 performs a parity check of W1, W2, and P, which is the three words following the block SYNC, and the RF flag RFF = 0 (no error) supplied from the 8-10 decoder 303 and the area coincidence flag AIF = 1. This is a parity check unit that sets the parity OK flag PRF only when (matched) and the parity check is OK.

When the parity OK flag PRF = 1, the 307 reproduces the fetched block address BLK as the reproduction block address PBAD.
When PRF = 0, the previous block address PBLK ^-1 +1 is output as the playback block address PBAD, and the block address continuity is detected and the block continuous flag BCF is sent. It is a detection unit.

308 has BCF = 1 (block address continuation) and PRF =
When it is 1, that is, when a valid block address is detected for two consecutive blocks, it counts up and the sync loss flag SYNG = 1 from the sync protection unit (sync loss occurs).
, Or a continuous flag that is cleared when BCF = 0 (block address discontinuity) and PRF = 1.
When the count value of the counter and the continuous flag counter reaches a specific value N, the block address valid flag BZ
This is a continuous flag / count unit composed of a BZRVF generation circuit that outputs RVF.

309 is a timing at which BZRVF is output, and an address latch for simultaneously latching the reproduction block address PBAD and the reference address R3ADR output from the reference timing generation unit 315, 3
10 is the phase of the reproduction signal based on the latched reference address and reproduction block address, and the reference timing generator 31
The error from the phase of the reference address output by 5 is obtained, and the phase shift correction data STB is sent to the recording timing generator 316.
A correction data generation unit that gives LK.

Reference numeral 311 is a gate for writing the demodulated data in the RAM unit 110, which is opened during reproduction by the recording / reproduction switching signal PR.

Reference numeral 314 is an 8-10 encoder that performs 8-10 conversion, 313 is a PS conversion unit that performs parallel-serial conversion, and 312 is an NRZI conversion unit that performs NRZI conversion on serial data. Is supplied to the head amplifier 105.

Reference numeral 315 is a reference timing generation unit that generates a fixed timing on a crystal basis based on the cylinder synchronization signal R3CP.

The recording timing generation unit 316 generates a recording address RCADR used for reading the pre-modulation data from the RAM unit 110, and also generates clocks for 8-10 conversion and parallel-serial conversion. The recording address RCADR is based on the cylinder synchronization signal R3CP, with the phase shift correction data STBLK sent from the correction data generation unit 310 as an initial value,
Is generated. That is, the recording timing for R3CP can be shifted by the phase shift correction data STBLK. Also, it sends the signal MASKT for SYNC mask to the synchronization protection unit.

Reference numeral 317 is an address conversion unit that converts the recording address RCADR into a form suitable for the address of the RAM unit 110, and 318 is a recording / reproduction switching signal PR of the RCADR converted by the address conversion unit, the reproduction block address RBAD, and the reproduction word address PWAD. The address selector is switched by and is supplied to the RAM unit 110 as RAMADR.

Next, the operation of the mask signal generator 123 will be described.

FIG. 6 is a timing chart showing the operation of the mask signal generator 123. In FIG. 6a, PGT represents a rotational phase pulse generated by the cylinder rotational phase detector, which occurs 45 degrees before the head touch section of the + azimuth head. T _S in the figure represents the cylinder rotation period, and T _S = t in the standard reproduction mode. HSW is a head switching signal generated by the servo block 115. The head touch section represents a section in which each of the plus azimuth head and the minus azimuth head hits the effective section of the tape.

RFMSK represents a reproduction signal mask signal.

RFMSK becomes "1" in the head touch section and becomes "0" in other sections.

RFMSK is a cylinder period T _S which is measured with respect to the PGT based, is set at a timing of 1 / 8T _S is reset at the timing of the PGT is reset at the timing of _{3 / 8T S, 5 / 8T} S It is set at the timing of and reset at the timing of 7 / 8T _S. The RFMSK generated in this way is
The reproduction signal supplied to the AND gate 124 and used in a section other than the head touch section is used as a mask.

SSP is a signal for distinguishing the sub data area from the main data area. When SSP = 0, it indicates a section including the main data area, and when SSP = 1, it indicates a section including the sub data area.

S2HSW is a signal that distinguishes the first half and the second half of the head touch section, and is used to distinguish the sub data area 1 and the sub data area 2. S2HSW is the first half when S2HSW = 0, S2HSW =
When it is 1, it indicates the latter half.

Similar to RFMSK, SSP and S2HSW are also generated based on the cylinder rotation period T _S with PGT as a reference, at the timing shown in FIG. 6a.

FIG. 6b shows that the cylinder rotation cycle T _S is 1.
RFMSK, SSP, S in case of 5 times, that is, in case of T _S = 1.5t
2 shows HSW.

When the cylinder rotation cycle is not constant and is asynchronous with the cylinder synchronization signal R3CP as in the high speed search mode, it is necessary to generate a mask signal proportional to the cylinder rotation cycle T _S , but in the standard playback mode, Since the rotation of the cylinder and the cylinder synchronization signal R3CP are synchronized, RFMSK can be generated based on R3CP.

Further, in this embodiment, the cylinder rotation period T _S is measured based on the rotation phase pulse PGT, but if the phase of the head switching signal HSW generated in the servo block 115 is sufficiently accurate, the rising edge of HSW A signal such as RFMSK can also be generated based on the interval T _S or the interval 1 / 2T _S between the rising edge and the falling edge of HSW.

Further, in the present embodiment, the reproduction signal mask signal RFMSK is made to coincide with the head touch section, but considering the transition period in which the cylinder rotation speed changes, the reproduction signal may not be masked correctly, so it may be slightly different. Margins may be needed. In this case, the RFMSK = 1 section may be set to be slightly longer than the head touch section.

EFFECTS OF THE INVENTION As described above, the signal reproducing apparatus of the present invention is based on the cylinder provided with the reproducing head, the cylinder rotation phase detecting means for detecting the rotation phase of the cylinder, and the phase information detected by the cylinder rotation phase detecting means. To calculate the cylinder rotation period,
A mask signal generation unit that generates a reproduction signal mask signal that is proportional to the cylinder rotation cycle and that uses the cylinder rotation phase as a reference, and a gate unit that masks the reproduction signal by the reproduction signal mask signal generated by the mask signal generation unit. Thus, even in the high speed search mode in which the cylinder rotation cycle changes, the playback signal supplied to the PLL is masked during a period other than the head touch section to prevent the state of the PLL from significantly deviating from the frequency to be locked, When the correct playback signal is input in the next head touch section, the PLL locks quickly and normal demodulation operation is obtained.
The reading probability of data can be improved. In addition, by setting the reproduction signal supplied to the demodulation unit to "0" during periods other than the head touch period, the error detection performed in the demodulation unit can be made reliable, so that errors that are missed or erroneous can be detected. Corrections can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an R-DAT in the embodiment of the present invention, FIG. 2 is a timing chart showing the operation of a servo block, and FIG. 3 is a modulation / demodulation of the R-DAT in the embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of a part
Figure is a block format diagram of R-DAT, Figure 5 is R
FIG. 6 is a track format diagram of the -DAT, and FIG. 6 is a timing chart showing the operation of the mask signal generator in the embodiment of the present invention. 100a, 100b ... Head, 101 ... Cylinder, 108 ... Modulator / demodulator, 115 ... Servo block, 116 ... System controller, 120 ... Phase generator, 121 ... PG sensor, 122 ... Cylinder rotation Phase detection unit, 123 ... Mask signal generation unit, 304 ... Sync protection unit, 305 ... Reproduction timing generation unit, 307 ... Block address check unit, 308
...... Continuous flag counter, 309 ...... Address latch, 310 …… Correction data generator, 315 …… Reference timing generator, 318 …… Block address latch, 320 ……
Area flag check section.

Claims (1)

[Claims] 1. A cylinder provided with a reproducing head, a cylinder rotation phase detection means for detecting a rotation phase of the cylinder, and a cylinder rotation cycle calculated based on phase information detected by the cylinder rotation phase detection means, A mask signal generator that generates a reproduction signal mask signal that is proportional to the cylinder rotation period and that uses the cylinder rotation phase as a reference to mask a reproduction signal during a period in which the reproduction head does not hit the tape, and the mask signal generation unit. When the generated reproduction signal mask signal is valid, a gate means for masking the reproduction signal output from the reproduction head, and a pre-value hold type PL for extracting a reproduction clock from the reproduction signal via the gate means
A signal reproducing device comprising L.