JPH01194172A - Signal regenerating device - Google Patents

Abstract

PURPOSE:To improve the reliability of a demodulating operation in a high speed searching mode by generating a regenerating signal mask signal proportional to a cylinder rotation cycle and defining the cylinder rotation cycle to be a reference and masking the regenerating signal. CONSTITUTION:A mask signal generating part 123 generates the mask signal proportional to the rotation cycle of the cylinder 101, thereby, in the high speed search mode in which the cylinder rotation cycle is changed, the regenerating signal supplied to a PLL (Phase Locked Loop) circuit 107 through a gate 124 is masked except at a head touch partition. Thereby, the state of the PLL is prevented from being a state remarkably deviated from a frequency to be originally locked to rapidly lock the PLL and the normal modulating operation is obtained when the correct regenerating signal is inputted in a next head touch partition.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a rotary head type recording and reproducing apparatus such as an R-DAT (rotating head type digital audio tape recorder).

BACKGROUND ART In recent years, digital recording technology has been applied to many fields such as audio, video, CD players, and R-DAT.

Technologies such as digital VTR have been established.

Among them, extraction of recovered clocks and correction of errors.

Signal processing technology such as error detection is an important point in determining the reliability of a playback device.

Digital playback devices generally use a self-clocking method that extracts a playback clock based on a signal recorded on a recording medium. The self-clocking method detects the changing point of the reproduced signal and uses the PLL (Phase Locked
In this method, a clock that is phase-synchronized with the reproduced signal is generated by a Loop) circuit, and the reproduced signal is demodulated using this clock.

Problems to be Solved by the Invention In the case of a fixed head type reproducing device, since the reproduced signal is obtained continuously, the PLL remains locked unless there is a long burst error, so the extraction operation of the reproduced clock is stable. ing. However, in the case of a rotary head type reproducing device, the reproduced signal is not necessarily obtained continuously. For example, if the ramp angle of the head and tape with respect to the cylinders is 90 degrees, the area in which the head is in contact with the tape (head touch area) is only 180 degrees, and there is no remaining print. The head does not touch the tape in the 180 degree section. In this case 1
Since no reproduction signal is obtained in the 80 degree section, if the PLL is operating during this period, the PLL will become extremely unstable and may deviate greatly from the frequency that it should be locked to. Even if the correct playback signal was input during the next head touch period, it took time to lock to the correct frequency, which could lead to reading errors.

In view of the above-mentioned problems, the present invention masks the playback signal supplied to the PLL in sections other than the head touch section, prevents the PLL state from deviating greatly from the frequency that should originally be locked, and It is an object of the present invention to provide a signal reproducing device in which a PLL locks quickly and normal demodulation operation is obtained when a correct reproduced signal is input in a section.

Note that a previous value hold type PLL in which the output frequency is held when the input signal becomes 5o" is disclosed in Japanese Patent Application No. 1983, for example.
There is one shown in No. 242415 "Clock regeneration phase synchronization circuit". Furthermore, the present invention generates an optimal mask signal and increases the reliability of demodulation operation not only in the standard playback mode where the cylinder rotation speed is constant, but also in the high-speed search mode where the cylinder rotation speed changes depending on the tape speed. be.

Means for Solving the Problems The signal reproducing device of the present invention includes a cylinder provided with a reproducing head, a cylinder rotational phase detection means for detecting the rotational phase of the cylinder, and a cylinder rotational phase detection means based on the phase information detected by the cylinder rotational phase detection means. a mask signal generation section that calculates the cylinder rotation period and generates a reproduction signal mask signal proportional to the cylinder rotation period and based on the cylinder rotation phase; and a reproduction signal generated by the mask signal generation section. It is constructed by a gate means for masking.

According to the above-described configuration, the present invention generates a mask signal proportional to the cylinder rotation period, thereby masking the playback signal supplied to the PLL even in a high-speed search mode in which the cylinder rotation period changes when the cylinder rotation period is not in the head touch section. This prevents the PLL state from deviating greatly from the frequency to which it should originally be locked, and promptly locks the PLL when the correct playback signal is input in the next head touch section.
is locked and normal demodulation operation is obtained.

Embodiments Hereinafter, embodiments in which the signal reproducing apparatus of the present invention is applied to an R-DAT (rotating head type digital audio tape recorder) will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of R-DAT in one embodiment of the present invention.

In Figure 1, 1001L and 1 oob are recording/reproducing heads with an azimuth angle of ±20 degrees, respectively, and 1o1.
is a cylinder, 102 is a magnetic tape, 103&.

103b is a reel for winding the tape 102; 104 is a capstan for running the tape 102 at a constant speed;
5 is a head amplifier for recording and reproduction; 106 is an equalizer for equalizing the waveform of the reproduction signal; and 107 is a PLL (Phase Looked Loop) for extracting a reproduction clock PCK for punching the reproduction signal from the reproduction signal.
) circuit, 108 is a modulation/demodulation unit for demodulating the reproduced signal and modulating the recording signal, 109 is an error detection, correction, and
a code processing processor for generating an error correction code;
110 is modulation/demodulation data.

RAM section that stores PCM data etc. 111 is a playback PC
112 is a human/D converter, 113 is a D/mu converter, 114 is a cylinder synchronization signal RaCP, and a modulation/demodulation section 108 . Code processing processor 109゜RAM section 11o, timing generation section that generates a basic clock used in the PCM control section 111, 115 is serial J"1Q1.Lee/1z1031
L, 103b.

and a servo block that controls capstan 104. Reference numeral 116 denotes a system control unit that instructs the mode of the system. At the time of high-speed search, the system control unit 116 provides tape speed data TPSP that indicates the tape speed to the servo block 115, and sends forward protection count data 5COtTNT corresponding to the tape speed to the synchronization protection unit in the modulation/demodulation unit 108. give.

12o is a PC (phase generator) provided to detect the rotational phase of the cylinder 10.1. P
G120 is a mark that can be detected optically. 121
is a PG sensor that detects that PG12Q has passed. Reference numeral 122 denotes a cylinder rotational phase detection section that generates rotational phase pulses PG and T when the P0 sensor 121 detects PG120. 123 is a reproduction signal mask signal R corresponding to the head touch section based on the rotational phase pulse PGT.
This is a mask signal generating section that generates FMSK, a signal 32H5W that distinguishes between the first half and the second half of the head touch section, and a signal SSP that distinguishes the area within the head touch section.

Next, the flow of signals during recording will be explained.

When the system control section 116 instructs the recording mode, the audio input cam IN is input to the A/D' converter 112 and converted into 16-bit PCM data. PCM
The data is input to the PCM control section 111, sent as 8-bit data to the RAM section 110, interleaved, and saved. The code processing processor 109 is R
An error correction code is added to the PCM data saved in the AM section 110 to generate pre-modulation data, and the data is stored in the RAM section 110.
Save to. After that, the modulation/demodulation section 108 transmits the 11M section 1
It receives modulated data from 1o at a predetermined timing, performs modulation processing, and generates a recording signal RFOUT. The recording signal RFOUT is supplied to the heads 100&, IQQb through the head and amplifier 106.

On the other hand, the servo block 115 includes the timing generator 1
The rotation of the cylinder 101 is controlled based on the cylinder synchronization signal RsCP generated by No. 14, and the head touch section and the recording signal RFOUT are aligned in phase, and the head switching signal H3W is generated to change the +azimuth to ~azimuth. Decide which head the recording current will flow through.

Figure 2 shows the timing diagram representing the operation of the servo block.
It is a chart. In Fig. 2, R3CP is a cylinder synchronization signal, servo block is a recording signal RFO.
Cylinder rotation is controlled so that the UT and head touch are in phase. It also generates a signal HSW for switching between +azimuth (H) and (7) Hm.

At this time, the tape 102 runs at a constant speed, and tracks with a width of - are recorded.

Next, the signal flow during standard playback will be explained.

When the system control unit 116 instructs the reproduction mode, the cylinder 101 is controlled by the servo block 116 based on R3CP, and the head touch period and demodulation timing are synchronized, as in the case of recording.

Furthermore, the tape speed can be changed to MUTF (Mutom2Lti
The head is controlled to trace the track using a technique called cTrack Finding.

Head signal R reproduced from heads 100&, 1oob
The FSG is connected to the equalizer 1 through the head amplifier 106.
06 and performs waveform equalization, the AND gate 12
4 to the PLL 107, extracts a reproduced clock, and supplies the recovered clock to the modulation/demodulation section 108.

The modulation/demodulation section 10B stores the demodulated data in the RAM section 110.
write to. Furthermore, the code processing processor 109
The demodulated data is read from the M section 110 and error detection and error correction are performed. The PCM control section 111 is an 11M section 11o.
The corrected 8-pit data is read out, deinterleaved, and supplied to the D/M converter 113 as 16-pit data. Also, the code processing processor 10
Interpolation processing is performed on the data determined to be uncorrectable in step 9. The D/Music converter 113 converts the PCM data into an audio signal and outputs it.

Next, the signal flow during high-speed search will be explained.

The signal flow during high-speed search is basically the same as the signal flow during standard playback. However, cylinder synchronization signal R
Since the rotation of 3CP and the cylinder are asynchronous, the head switching signals H3W and R3CP are asynchronous.

Next, the detailed configuration of modulation/demodulation section 108 will be explained. FIG. 3 is a block diagram showing the configuration of modulation/demodulation section 108.

In FIG. 3, 301 is an NRZI inverse converter that converts the NRZI-modulated playback signal RFXN into the NFtZ signal RFDT, and 304 is an NRZI inverse converter that extracts the fukutsuku synchronization signal 5YNC from the NRZ signal RFDT and sends it to the playback timing generator. , valid 5YNC flag VSY giving reference timing
This is a synchronization protection unit that sends out NC and protects VSYNC from occurring even if 5YNC is erroneously detected.

Furthermore, when the synchronization protection unit 304 detects the synchronization loss, it outputs the synchronization loss flag 5YNG.

302, the NRZ signal is serially converted to the word clock WDCK generated by the reproduction timing generator 306.
The S-P converter 303 that performs parallel conversion converts the S-P converted 10-bit data into 8-bit data and sets an RF error flag RFF for data that does not conform to the 8-10 modulation rule. It is an 8-10 decoder.

305 is a valid 5YN sent from the synchronization protection unit 304
Regenerated clock PCK based on C flag VSYNC
This is a playback timing generation section that generates timing for demodulation processing. The reproduction timing generating section 305
- P conversion clock WDCK, reproduction word address PWAD for writing demodulated data to RAM section 110, RAM write request signal WRRAM, and synchronization protection section 3
Generates the 5YNC window 5YNCW used in 04.

Here, the block format of R-DAT is shown in FIG. 4a. Also, FIG. 4 shows the format of W2.

The block address BLK in W2 is 7 bits in the main data area and 4 bits in the sub data area.
Become a bit. That is, each track has 128 blocks in the main data area and 16 blocks in the sub data area. Sub data area 1 is assigned block addresses 0 to 7, and sub data area 2 is assigned block addresses 8 to 15. Furthermore, the MSB of W2 is a sub-area flag that becomes -” when it is a sub-data area.
The figure shows the track format of R-DAT.

320 are signals SSP and 5 representing sections including the above-mentioned sub data areas 1 and 2 and the main data area, respectively.
This is an area flag check section that compares 2H3W with the subarea flag and block address recorded on W2, and outputs an area match flag AIF=1 only when they match.

When SSP is ``1'', it represents the section that includes the sub data area, and when it is ``o'', it represents the section that includes the main data area, so it has the same logic as the sub area flag on W2, so if it matches, this Wl, The data of W2 can be considered to be highly reliable. 82H8W is '0' in the section that includes sub data area 1, and is 111+? in the section that includes sub data area 2. This has the same logic as the MSB of the block address, so if they match, the Wl and W2 data can be considered to be highly reliable. The detailed timing of SSP and 52H8W will be described later.

306 is the 3 words following block 5YNC, Wl
, W2. P's parity check is performed, and only when the RF flag RFF supplied from the 8-10 decoder 303 is OK (no error), area match flag IF=1 (match), and the parity check is OK, This is a parity check section that sets a parity OK flag PRF.

307 is parity 0K77gP RF = 1 (7
), the captured block address BLK is output as the reproduced block address PBAD, and PRF=0.
When , the previous block address PBLK-'
+1 to play block address PBAD,! : and outputs it, detects the continuity of block addresses,
This is a block address detection unit that sends out a block continuity flag BCF.

30B is BCF=1 (block address consecutive).

And when PRF=1, that is, it is a valid block.

Counts up when two blocks of addresses are detected in a row, and outputs the out-of-synchronization flag 5YNG from the synchronization protection section.
= 1 (out of synchronization occurs), or gcy = o (
block address discontinuity).

and a continuous flag counter that is cleared when PRF=1, and a block address valid flag BZR when the count value of the continuous flag counter reaches a specific value N.
This is a continuous flag counting section consisting of a BZRVF generation circuit that outputs VF.

309 is an address latch that simultaneously latches the reproduced block address PBAD and the reference address latch DR output from the reference timing generator 316 at the timing when BZRVF is output; 310 is the latched reference address and the reproduced block address; , the phase of the reproduced signal and
This is a correction data generation section that calculates the error between the phase of the reference address output from the reference timing generation section 315 and provides phase shift correction data 5TBLK to the recording timing generation section 316.

Reference numeral 311 is a gate for writing demodulated data into the RAM section 110, and is opened during reproduction by a recording/reproduction switching signal PR.

314 is an 8-10 encoder that performs 8-10 conversion; 31
3 is a P-5 converter that performs parallel-to-serial conversion;
12, NRZ that performs NRZ conversion on serial data
This is an I conversion section, and the output recording signal RFOUT is supplied to the head amplifier 105.

Reference numeral 315 is a reference timing generating section that generates fixed timing on a crystal basis based on the cylinder synchronization signal R3CP.

The recording timing generating section 316 generates a recording address RCA used for reading out the pre-modulation data from the RAM section 110.
In addition to generating DR, it also generates clocks for 8-10 conversion and parallel-to-serial conversion. The recording address RCADR is generated using the cylinder synchronization signal R3CP as a reference and the phase shift correction data 5TBLK sent from the correction data generation section 310 as an initial value. In other words, the recording timing for 13CP can be shifted by the phase shift correction data 5TBLK. It also sends a signal MASKT for 5YNC mask to the synchronization protection section.

31 is an address conversion unit 318 that converts the recording address RCADR into a format suitable for the address of the RAM unit 1jo;
The RAM
This is an address selector that is supplied to section 110 as RAMADH.

Next, the operation of the mask signal generating section 123 will be explained.

FIG. 6 is a timing chart showing the operation of the mask signal generating section 123. In FIG. 6a, PGT indicates the rotational phase pulse generated by the cylinder rotational phase detection section,
+ Occurs 45 degrees before the head touch section of the azimuth head. Ts in the figure represents the cylinder rotation period, which is T,==t in the standard reproduction mode. H2N is a head switching signal generated by the servo block 115. The head touch section represents the section in which each of the positive azimuth head and the negative azimuth head hits the effective section of the tape.

RFMSK represents a reproduced signal mask signal.

RFMSK becomes 1" in the head touch section and becomes "o" in other sections.

RFMSK is P based on the measured cylinder cycle Ts.
With GT as a reference, it is reset at the timing of PGT, set at the timing of 3ATs, reset at the timing of %Ts, set at the timing of %Ts, and reset at the timing of %Ts. The RFMSK generated in this manner is supplied to the AND gate 124 and masks the reproduced signal in sections other than the head touch section.

SSP is a signal for distinguishing between the sub data area and the main data area; when 5SP=O, it indicates a section including the main data area, and when 5SP=1, it indicates a section including the sub data area.

52HSW is a signal that distinguishes between the first half and the second half of the head touch section, and is used to distinguish between sub data area 1 and sub data area 2. 52H3W indicates the first half when 52H3W=O, and the second half when 82H8W=1.

5SpH! :52H8W is also based on the cylinder rotation period Ts as well as RFMSK, and based on PGT, Figure 6 a.
It is generated at the timing shown in .

FIG. 6 shows RFMSK, SSP, and 52H3W when the cylinder rotation period Ts is 1.5 times that of the standard regeneration mode, where T=1.5t.

Note that when the cylinder rotation period is not constant and is not synchronized with the cylinder synchronization signal 13CP, as in the high-speed search mode, it is necessary to generate a mask signal proportional to the cylinder rotation period Ts. Since the rotation of the cylinder is synchronized with the cylinder synchronization signal R3CP, RFMSK can also be generated based on R3CP.

Furthermore, in this embodiment, the cylinder rotation period Ts is measured based on the rotational phase pulse P(1,T, but if the phase of the head switching signal H3W generated by the servo block 115 is sufficiently accurate, the HSW Rising edge interval Ts
Alternatively, a signal such as RFMSK can be generated based on the interval y2Ts between the rising edge and the falling edge of HSW.

Furthermore, in this embodiment, the reproduced signal mask signal RFMSK is made to coincide with the head touch section, but considering the transitional period when the cylinder rotation speed changes, there may be a slight delay in order to avoid masking the correct reproduced signal. Margins may be required. In this case, it is preferable to make the RFMSK=1 section slightly longer than the head touch section.

Effects of the Invention As described above, the signal reproducing device of the present invention has a cylinder equipped with a reproducing head, a cylinder rotational phase detection means for detecting the rotational phase of the cylinder, and a signal reproducing apparatus based on the phase information detected by the cylinder rotational phase detection means. Calculate the cylinder rotation period,
A mask signal generation section that generates a reproduction signal mask signal that is proportional to the cylinder rotation period and based on the cylinder rotation phase, and a gate means that masks the reproduction signal with the reproduction signal mask signal generated by the mask signal generation section. Even in the high-speed search mode in which the cylinder rotation period changes, the playback signal supplied to the PLL is masked during times other than the head touch period, and the PLL state is prevented from becoming significantly deviated from the frequency to which it should be originally locked. When a correct reproduction signal is input in the next head touch section, the PLL is quickly locked and a normal demodulation operation is obtained, making it possible to improve the probability of reading data.

Furthermore, by setting the reproduced signal supplied to the demodulator to '0' during periods other than the head touch period, error detection performed by the demodulator can be ensured.
It is possible to prevent errors from being overlooked and errors from being incorrectly corrected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of R-DAT in an embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the servo block, and FIG. 3 is a modulation/demodulation of R-DAT in an embodiment of the present invention. Block diagram showing the configuration of the section,
Figure 4 is a block format diagram of R-DAT, Figure 5
The figure is a track format diagram of R-DAT, and FIG. 6 is a timing chart showing the operation of the mask signal generating section in the embodiment of the present invention. I QQ&, 1 oob...head, 1o1
......Cylinder, 10B...Modulation/demodulation section,
115... Servo block, 116...
- System control unit, 120... Phase generator, 121... PG center, 122...
...Cylinder rotation phase detection section, 123...
Mask signal generation section, 304...Synchronization protection section, 3
05...Reproduction timing generation section, 307...
...Block address check section, 308...
... Continuous flag counter, 309 ... Address latch, 310 ... Correction data generation section, 3
15...Reference timing generation section, 318...
...Block address latch, 320...Area flag check section.

Claims (1)

[Claims] A cylinder including a reproducing head, a cylinder rotation phase detection means for detecting the rotation phase of the cylinder, and a cylinder rotation period calculated based on the phase information detected by the cylinder rotation phase detection means, and a cylinder rotation period proportional to the cylinder rotation period. and a mask signal generation section that generates a reproduction signal mask signal based on the cylinder rotation phase, and a gate means that masks the reproduction signal with the reproduction signal mask signal generated by the mask signal generation section. Signal regenerator.