JPH07118158B2 - Recording / playback device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for recording / reproducing digital data such as an R-DAT (rotary head type digital audio tape recorder).

2. Description of the Related Art In recent years, digital recording technology has been applied to many fields such as sound and images, and technologies such as a CD player, R-DAT, and digital VTR have been established.

Among them, in addition to basic recording / playback technology, applied technical fields such as after-recording and continuous recording have become important.

When performing after recording, continuous recording, etc., it is necessary to perform new recording according to the reproduced signal. If the phases of the reproduction signal and the recording signal are different, the recording format itself is not guaranteed, and normal tracking servo and reproduction cannot be performed.

In the conventional recording apparatus, taking the R-DAT as an example, the signal processing unit generates a timing signal serving as a reference of rotation of a cylinder having two heads, and based on this signal, a rotation phase of the cylinder is generated. A servo system has been used in which the timing of the signal processing unit and the timing of the signal processing unit are synchronized.

Problems to be Solved by the Invention However, in the above-mentioned configuration, a mechanical PG (phase generator) is required to know the rotation phase of the cylinder, and PG mounting error and its detection error become a problem. The phase accuracy of the reproduction signal and the timing of the signal processing unit cannot be sufficiently obtained, and the phase of the old recording track and the new recording track does not match during after recording and continuous recording, which adversely affects the subsequent reproduction. Had a point.

In view of the above problems, the present invention extracts the block address in the reproduction signal and compares it with the reference address at that time,
By detecting the phase shift between the reproduction signal and the reference address and reflecting the result in the recording address, the phase of the recording address and the reproduction signal can be matched and a continuous recording track can be formed even after recording. A playback device is provided.

Means for Solving the Problems In order to solve the above problems, the recording / reproducing apparatus of the present invention is configured to reproduce a reproduction block from a reproduction signal divided into blocks.
A block address detection unit that detects an address, a reference timing generation unit that generates a reference address independent of a reproduction signal, and a valid block address when a reference address and a reproduction block address are used,
The sub data area is detected based on the timing of the phase shift detecting means for detecting the phase shift between the reproduction signal and the reference address and sending the phase shift correction data, and the timing of the recording timing generator whose phase is determined by the phase shift correction data. Is provided with a recording signal generation unit for performing after-recording by generating a recording signal corresponding to.

The present invention has the above-described configuration, detects a valid block address, obtains a phase difference between the reproduction signal and the reference address by using the reference address and the block address at this time, corrects the phase of the recording address, and corrects it. After-recording that matches the phase of the reproduced signal is performed using the recorded address.

First Embodiment A first embodiment of the recording / reproducing apparatus of the present invention will be described below.
A description will be given with reference to the drawings.

FIG. 1 shows a first embodiment in which the recording / reproducing apparatus of the present invention is applied to an R-DAT (rotary head type digital audio tape recorder).

In FIG. 1, 100a and 100b are recording / reproducing heads each having an azimuth angle of ± 20 degrees, 101 is a cylinder, 102 is a magnetic tape, and 103a and 103b are reels for winding the tape 102, 10
4 is a capstan for running the tape 102 at a constant speed, 10
5 is a recording / playback head amplifier, 106 is an equalizer for equalizing the waveform of a playback signal, 107 is a PLL (Phas) for extracting a playback clock PCK for punching the playback signal out of the playback signal.
e Loocked LooP) circuit, 108 demodulates the reproduced signal,
A modulation / demodulation unit for modulating a recording signal, 109 is a code processing processor for performing error detection, correction, and error correction code generation, 110 is a RAM unit for storing modulation / demodulation data, PCM data, and the like, and 111 is reproduction PCM data. PCM for interpolation processing
Processing unit, 112 is an A / D converter, 113 is a D / A converter, 11
Reference numeral 4 is a cylinder synchronization signal R3CP, and a timing generator that generates a basic clock for the modulation / demodulation unit 108, the code processing processor 109, the RAM unit 110, and the PCM control unit 111, and 115 is the cylinder 101, reel 1
A servo block that controls 03a, 103b, and the capstan 104. Reference numeral 116 is a system control unit that instructs the mode of the system.

Next, the flow of signals during recording will be described.

When the system control unit 116 instructs the recording mode, the audio input AIN is input to the A / D converter 112 and the 16-bit PIN
Converted to CM data. The PCM data is input to the PCM control unit 111, sent as 8-bit data to the RAM unit 110, interleaved, and saved. Code processing 10
Reference numeral 9 adds an error correction code to the PCM data saved in the RAM unit 110 to generate pre-modulation data and saves it in the RAM unit 110. After that, the modulation / demodulation unit 108 receives the modulation data from the RAM unit 110 at a predetermined timing, performs a modulation process, and generates a recording signal RFOUT. Recording signal RFOUT is head amplifier
It is supplied to the heads 100a and 100b through 105.

On the other hand, the servo block 115 controls the rotation of the cylinder 101 on the basis of the cylinder synchronization signal R3CP generated by the timing generation unit 114 and controls the rotation of the cylinder 101 so that the head touch section and the recording signal RFOUT are generated. The head switching signal HSW is generated while the phases are matched, and it is determined which of the + azimuth head and the −azimuth head the recording current is to flow.

2 (a), (b), (c) and (d) are timing charts showing the operation of the servo block. Second
In the figure, R3CP is a cylinder synchronization signal, and the servo block controls the cylinder rotation so that the phase of the head touch matches the recording signal RFOUT. See also + azimuth
A signal HSW for switching between the head Hp and the azimuth head Hm is generated.

At this time, the tape 102 runs at a constant speed and a track having a uniform width is recorded.

Next, the flow of signals during reproduction will be described.

When the system control unit 116 instructs the reproduction mode, the cylinder 101 is controlled by the servo block 115 with R3CP as a reference, and the head touch section and the demodulation timing are synchronized, as in the case of recording.

Furthermore, tape speed is ATF (Automatic Track Findi
ng) is used to control the head to trace a track.

The head signal RFSG reproduced from the heads 100a and 100b is supplied to the equalizer 106 through the head amplifier 105 for waveform equalization and then supplied to the PLL 107 to extract a reproduction clock and then to the modulation / demodulation unit 108.

The modulation / demodulation unit 108 writes the demodulated data in the RAM unit 110. Further, the code processing processor 109 reads the demodulated data from the RAM unit 110 and performs error detection and error correction.
The PCM control unit reads the corrected 8-bit data from the RAM unit 110, deinterleaves it, and supplies it to the D / A converter 113 as 16-bit data. In addition, interpolation processing is performed on the data determined to be uncorrectable by the code processing processor 109. The D / A converter 113 converts the RCM data into an audio signal Aout and outputs it.

Next, a detailed configuration of the modulation / demodulation unit 108 will be described.

FIG. 3 is a block diagram showing the configuration of the modulation / demodulation unit 108.

In FIG. 3, reference numeral 301 denotes the NRZI-modulated reproduction signal RFIN.
The NRZI inverse conversion unit 304 for converting into a signal extracts the block synchronization signal SYNC from the NRZ signal, sends DSYNC giving the reference timing to the reproduction timing generation unit, and even if SYNC is erroneously detected, DSYNC is It is a synchronization protection unit that protects against occurrence. Further, the synchronization protection unit outputs the synchronization loss flag SYNG when detecting the synchronization loss. 302 is an SP converter that performs serial-parallel conversion of the NRZ signal by the word clock WDCK generated by the reproduction timing generator, and 303 is SP converted 10-bit data to 8-bit data Do with 8
It is an 8-10 decoder that sets an RF error flag RFF for data that does not conform to the -10 modulation rule.

Reference numeral 305 denotes a sync detection flag DS sent from the sync protection unit 304.
This is a reproduction timing generation unit that generates a timing for demodulation processing by a reproduction clock PCK with YNC as a reference.
The reproduction timing generation unit 305 uses the S / P conversion clock WDC.
It generates a reproduction word address PWAD for writing demodulated data in the K, RAM unit 110, a RAM write request signal WRRAM, and a SYNC window SMASK used in the synchronization protection unit 304.

306 performs a parity check of W1, W2, P, the three words following the block SYNC, and when the RF flag RFF = 0 (no error) supplied from the 8-10 decoder 303 and the parity check is OK Only the parity check unit that sets the parity OK flag PRF. The block format of R-DAT is shown in FIG. The format of W2 is shown in FIG. 4 (b). The block address BLK in W2 is 7 bits in the main data area,
4 bits in the serve data area. That is,
There are 128 main data areas and 16 sub data areas per track. Also, W2
The MSB of is a sub area flag which becomes "1" in the sub data area. FIG. 5 shows the track format of R-DAT.

When the parity OK flag PRF = 1, the 307 reproduces the fetched block address BLK as the reproduction block address PBAD.
When PRF = 0, the previous block address PBLK ¹ +1 is output as the playback block address PBAD, the block address continuity is detected, and the block continuous flag BCF is sent. It is a department.

308 has BCF = 1 (block address continuation) and PRF =
When it is 1, that is, when a valid block address is detected for two consecutive blocks, it counts up and the sync loss flag SYNG = 1 from the sync protection unit (sync loss occurs).
, Or a continuous flag that is cleared when BCF = 0 (block address discontinuity) and PRF = 1.
When the count value of the counter and the continuous flag counter reaches a specific value N, the block address valid flag BZ
This is a continuous flag / count unit composed of a BZRVF generation circuit that outputs RVF.

309 is a timing at which BZRVF is output, and an address latch for simultaneously latching the reproduction block address PBAD and the reference address R3ADR output from the reference timing generation unit 315, 3
Reference numeral 10 denotes the phase of the reproduction signal based on the latched reference address and reproduction block address, and the reference timing generator 315.
Of the phase difference of the reference address output from the recording timing generator 316
Is a correction data generation unit that gives

Reference numeral 311 is a gate for writing the demodulated data in the RAM section 110, which is opened during reproduction by the recording / reproduction switching signal PR.

314 is a recording address transmitted by the recording timing generator 316
An 8-10 encoder that performs 8-10 conversion of unmodulated data read from the RAM unit 110 based on RCADR, 313 is a PS conversion unit that performs parallel-serial conversion, and 312 is NRZI for serial data. An NRZI conversion unit that performs conversion, and an output recording signal RFOUT is supplied to the head amplifier 105.

The NRZI conversion unit 312, the PS conversion unit 313, and the 8-10 encoder 314 will be collectively referred to as a recording signal generation unit.

Reference numeral 315 is a reference timing generation unit that generates a fixed timing on a crystal basis based on the cylinder synchronization signal R3CP.

The recording timing generation unit 316 generates a recording address RCADR used for reading the pre-modulation data from the RAM unit, and also generates clocks for 8-10 conversion and parallel-serial conversion. The recording address RCADR is generated based on the cylinder synchronization signal R3CP, with the phase shift correction data STBLK sent from the correction data generation unit 310 as an initial value. That is, the phase shift correction data STBLK causes R
The recording timing for 3CP can be shifted. In addition, it sends the window MASKT for the SYNC mask to the synchronization protection unit.

317 is an address conversion unit that converts the recording address into a form suitable for the address of the RAM unit, and 318 switches the reference address R3ADR, the reproduction block address PBAD, and the reproduction word address PWAD by the recording / reproduction switching signal PR, and the RAM unit 110 RA
Address selector supplied as MDR.

Next, a phase shift correction process that can be used for post-recording will be described.

As described in FIG. 2, the servo
The block 115 controls the phase of the head touch with reference to the cylinder synchronization signal R3CP so that the reproduction signal RFIN having the correct phase can be obtained with respect to R3CP.

However, in R-DAT and the like, there is a problem such as a mounting error of a PG (phase generator) that detects a rotation phase of a cylinder, and the like, in view of compatibility, sufficient cylinder phase control cannot be performed. .

Therefore, when the phase of the reproduction signal RFIN shifts with respect to R3CP, the shift amount is detected, and the recording timing generation unit 31
Allow the initial phase of 6 to be shifted over R3CP over several blocks before and after. That is, since the recording timing is generated according to the phase of the reproduction signal, the recording track at the time of after recording can be matched with the original track.

First, a method of detecting the phase shift of the reproduction signal will be described.

FIGS. 6A to 6I are timing charts showing the process of generating the block address valid flag BZRVF, which is output when a highly reliable block address is detected.

In FIG. 6, PBAD is a block address detection unit 307.
Indicates the block address detected in.

0,1,2,7,8, ..., 19 indicates a block address of parity OK, and (127), (3), and (15) are parity NG, which indicate interpolated block addresses. a and b are blocks in which SYNG stands, that is, blocks in which synchronization is lost, and c is a block in which a block address is erroneously detected due to a missed parity check.

PRF is a parity OK flag transmitted by the parity check unit 306.

BCF has the above blocks and this block.
This is a block continuation flag that is set when addresses are continuous, and is generated by the block address detection unit 307 by comparing the previous block address with the current block address.

Continuous flag counter (output value: Q _BC ) is BCF / PRF = 1
, That is, when the block addresses are consecutive, the count is incremented. When! BCF / PRF = 1, that is, when block addresses are discontinuous, the continuous flag counter is cleared. When PRF = 0,
That is, when the block address is unknown, the continuous flag counter holds the previous value.

SYNG is the SYNC when the sync protector 306 detects a loss of synchronism, that is, M consecutive times (M = 1,2,3 ...)
Is an out-of-sync flag that stands when is not detected at a particular interval. The continuous flag counter (output value: Q _BC ) is cleared by SYNG. Therefore, when the counter clear signal CNTCR = SYNG +! BCF • PRF = 1, the continuous flag counter is cleared.

BCCK is a counter enable signal CNTEN = BCF • PRF punched out with a pulse of a specific timing, and is used as a clock of a continuous flag counter. However, in d, the parity OK flag PRF is not set, so the count, Not up. Block address valid flag BZ
In RVF, the output value Q _BC of the continuous flag counter is N (N = 1, 2,
3 ……) is a flag that is set when the playback block address PBAD and recording address RCADR are BZR.
Latched on the rising edge of VF. Since N = 4 here, BZRVF stands at point e. In other words, check the continuity of block addresses with parity OK without any loss of synchronization, and when BCCK is set N times, the last block address is set as a highly reliable block address that does not miss parity. It is adopted and the reference address R3ADR at that time is latched to obtain the phase shift.

Next, the phase shift correction processing will be described.

If the phase shift of the playback signal with respect to R3CP is ΔADR, then ΔADR = PBAD + OFS-R3ADR (1) PBAD: Playback block address OFS: Address offset R3ADR: Reference address OFS is the line phase shift Address when ΔADR is '0' -It is an offset.

When ΔADR = 0, OFS = R3ADR-PBAD (2). The address offset OFS differs depending on which area block address is used.

7A to 7F show the relationship between the reproduction block address PBAD and the reference address R3ADR in R-DAT.
The OFS value is defined as follows so as to satisfy the equation (2).

Further, in FIG. 7, SUBPCM is a signal for identifying the sub data area and the main data area.
2CP is a signal that distinguishes the first half and the second half of the track.
Based on PCM and R12CP, the signals of sub data area 1, sub data area 2 and main data area can be extracted. Therefore, since the address offset OFS can be set to a correct value by using SUBPCM and R12CP, the phase shift detection can be realized by using the block address of any one of the above three areas.

On the other hand, the recording timing generation unit 316 generates the recording address RCADR based on R3CP, but the initial value of the address is determined by the phase shift correction data STBLK.

8A to 8G are timing charts showing the operation of the recording timing generator 316. In FIG. 8, R3ADR is a reference address starting from the edge of R3CP. Also, the phase shift correction data STBLK = 0 (block)
In the case of, the recording address RCADR starts the 0th block from the edge of R3CP. RCADR when STBK = 0.5 (block)
Has a phase that starts 0.5 blocks and is 0.5 blocks ahead of R3CP. When STBLK = -1.0 (block),
RCADR starts with −1.0 block and has a phase sent 1.0 block to R3CP. That is, the recording address RCADR (n) of the nth track is expressed as RCADR (n) = R3ADR + STBLK (n) (3). Therefore, using the equation (1), the phase shift ΔADR (n) of the nth track is obtained, and the phase shift correction data STBLK (n + 1) of the next track is set as STBLK (n + 1) = ΔADR (n). For example, the phase of the recording address is 1 times that of the reproduction signal.
Follow the truck behind. For example, if the playback signal RFIN is 1
When the block is delayed, if SBLK = -1.0, the phase of the playback signal RFIN and RCA
The phases of DR will match. Therefore, if after-recording is performed using the RCADR timing corrected by STBLK, recording in the same phase as the reproduced signal becomes possible.

Although the reference timing generation unit and the recording timing generation unit have independent timing generation units here, if the phase shift correction data STBLK and the recording address RCADR generated by the recording timing generation unit are used, the reference address R3ADR Therefore, the reference timing generation section and the recording timing generation section can be shared. R3ADR is the phase shift correction data STBLK for the nth track.
Using (n) and the recording address RCADR (n), it can be expressed as R3ADR = RCADR (n) -STBLK (n).

Next, after-recording using the above-mentioned phase shift correction processing will be described.

FIGS. 9A to 9G are timing charts showing the after recording timing of the sub data area.

In FIG. 9, the reproduction signal RFIN is the cylinder synchronization signal R3CP.
It is 10 blocks behind. SRPR is the head
With the amplifier switching signal, the head amplifier 105 enters the reproducing state when SRPR = 0 and the recording state when SRPR = 1. At this time, the sub data area is the recording mode, the main
The data area is in playback mode. Therefore, the phase shift detection process is performed using the block address of the main data area.

Since the phase of the recording address RCADR is delayed by 10 blocks due to the phase shift correction processing described above, the recording signal RFOUT is generated with a phase delay of 10 blocks in accordance with it. The head amplifier switching signal SRPR is also RC.
It is generated based on ADR, so it is 10 blocks behind.
Also, write request signal WRRAM to RAM and read request signal RD
Each RAM is also delayed by 10 blocks according to the playback signal and RCADR.

Therefore, the recording pattern after after recording is continuous, and the ATF signal used for servo control is not erased, so that stable reproduction can be performed.

When performing after recording in the main data area, set SRPR = 1 in the main data area to set the recording mode, and detect the phase shift using the block address in the sub data area. .

EFFECTS OF THE INVENTION As described above, the recording / reproducing apparatus of the present invention has a block address detecting unit for detecting a reproduction block address from a reproduction signal divided into blocks, and a reference timing for generating a reference address independent of the reproduction signal. Phase shift detecting means for detecting the phase shift between the reproduction signal and the reference address by using the reference address and the playback block address when the generation unit and the effective block address are detected, and sending the phase shift correction data. According to the timing of the recording timing generation unit whose phase is determined by the phase shift correction data, a recording signal generation unit that generates a recording signal corresponding to the sub data area and performs after recording is provided. , It is possible to detect the phase of the reproduction signal and adjust the phase of the recording address to the reproduction signal. Even if there is a large mounting error in the phase generator, after recording can be performed in phase with the playback signal, so the tracking signal adjacent to the sub data area may be erased, or after recording before The signal in the sub data area remains unerased and does not adversely affect the next reproduction. For example, if the recording phase of after recording is shifted backward due to a mounting position error of a PG (phase generator), if the present invention is not applied, the previously recorded sub data remains, and the block synchronization that remains after the next reproduction is erased. Since the signal is detected first, the original sub data becomes unreadable. Further, when the recording phase of the after recording is shifted forward, and when the present invention is not applied, the unerased sub data is erroneously reproduced. The present invention can easily solve the problems that occur during after recording as described above.

Also, by using a recording address that matches the reproduction signal phase, it is possible to provide a window that follows the reproduction signal phase, so a window is provided at the timing at which the block synchronization signal SYNC is expected to come, and at other timings. It is possible to prevent erroneous detection of SYNC that occurs.

When data is recorded by dividing it into several areas like R-DAT, for example, sub data
Provide a sub area window for the area and a main area window for the main data area,
It is possible to capture unnecessary data and prevent false detection. Also, since these windows follow the phase of the playback signal, there is little possibility of masking even the necessary data, and it is possible to capture all the necessary data and discard the unnecessary data, thus improving the reliability of the playback process. improves.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of a recording / reproducing apparatus in the first and second embodiments of the present invention, FIG. 2 is a timing chart showing the operation of a servo block, and FIG. 1 is a block diagram showing a configuration of a modulation / demodulation unit of the recording / reproducing apparatus of the first embodiment, FIG. 4 is a configuration diagram showing an R-DAT block format, and FIG. 5 is an R-DAT track format.
FIG. 6 is a block diagram showing a format, FIG. 6 is a timing chart showing the process of block address detection, FIG. 7 is a timing chart showing the relationship between a reproduction block address and a reference address, and FIG. 8 is a recording timing generator. FIG. 9 is a timing chart showing the operation, and FIG. 9 is a timing chart showing the timing of after recording in the sub data area. 100a, 100b ... Head, 101 ... Cylinder, 108 ... Modulator / demodulator, 115 ... Servo block, 307 ... Block address checker, 308 ... Continuous flag counter, 3
09 …… Address latch, 310 …… Correction data generator, 3
15 …… Reference timing generator, 318 …… Block address latch.

Claims (1)

[Claims] 1. A block address detection unit for detecting a reproduction block address from a reproduction signal divided into blocks, a reference timing generation unit for generating a reference address independent of the reproduction signal, and a valid block address is detected. Then, using the reference address and the playback block address, the phase shift between the playback signal and the reference address is detected,
After-recording is performed by generating a recording signal corresponding to the sub-data area based on the timing of the phase-shift detecting means for sending the phase-shift correcting data and the timing of the recording-timing generator whose phase is determined by the phase-shift correcting data. A recording / reproducing apparatus comprising a recording signal generation unit for performing the above.