JP2593841B2 - Sync signal detection circuit - Google Patents

Description

The present invention relates to, for example, converting a video signal or an audio signal into a PCM signal, and recording the same as a diagonal track on a recording medium by a rotating head for each unit time. The present invention relates to a synchronous signal detecting circuit suitable for use in a digital signal recording / reproducing device for reproducing a signal.

2. Description of the Related Art When a video signal or an audio signal is formed and recorded on a magnetic tape by a helical scan type rotary head device, one diagonal track is recorded every unit time, and is reproduced. It has been considered that video signals and audio signals are converted to PCM for recording and reproduction. This is because high-quality recording and reproduction can be achieved by using PCM.

In this case, at the time of reproduction, the tracking control to make the rotating head scan the recording track correctly,
Conventionally, a control signal recorded at one end in the width direction of a tape is reproduced by the fixed head by a fixed magnetic head, and the reproduction control signal and the rotational phase of the rotary head are set to have a constant phase relationship. It is usually done by doing.

However, in this method, a particularly fixed magnetic head must be provided for tracking control.

Providing such a fixed magnetic head is disadvantageous in terms of the mounting location and the like when it is desired to reduce the size of the recording / reproducing apparatus.

Therefore, a method of performing tracking control of the rotary head using only the reproduction output of the reproducing rotary head without using the fixed head has been previously proposed by the present applicant.

According to this method, the PCM signal can be easily compressed and decompressed on the time axis. Therefore, unlike the analog signal, it is not necessary to always record and reproduce the signal continuously in time.
The purpose of the present invention is to focus on the fact that it is easy to record the PCM signal and a signal different from the PCM signal by dividing the area into tracks of a book.

That is, when a PCM signal is compressed on a time axis and a plurality of rotating heads form a track obliquely on a recording medium without forming a guard band and record it, the PCM signal is recorded in the longitudinal direction of each track. A plurality of tracking pilot signals are independently recorded as an area, and at the time of reproduction, the recording track is scanned by a rotating head having a scanning width wider than the track width, and the rotating head reads pilot signals from tracks on both sides of the track being scanned. Is used to control the tracking of the rotary head by the reproduction output.

Then, this tracking pilot signal is recorded,
As a reference signal at the time of reproduction, a 30 Hz pulse signal (PG) indicating the rotation phase of the rotary head obtained in synchronization with the rotation of the rotary drive motor of the rotary head is used.

However, when the PG signal is used as the detection position reference when reproducing the tracking pilot signal during reproduction as described above, the reference position of the PG signal is shifted due to mechanical aging or temperature change of the device. A kind of tracking error appears as a predetermined amount (offset).

For this reason, it is difficult to control the rotating head by reproducing the tracking pilot signal at the same timing as during reproduction and recording, and there is a problem that compatibility between devices cannot be obtained.

In addition, since the sampling pulse for obtaining the reproduction output of the tracking pilot signal is formed over one rotation period of the head with reference to the PG signal, the error is increased in an integrated manner and the influence of the so-called jitter is increased. Therefore, there is a disadvantage that the position of the sampling pulse is shifted.

Also, in the recording / reproducing apparatus of the rotary head system, when considering the tracking control, not only the normal reproduction but also the variable speed reproduction in which the tape speed is made different from that at the time of recording must be considered.

Therefore, the present applicant further reliably reproduces the tracking pilot signal without being affected by mechanical aging, temperature change, or jitter of the apparatus during normal reproduction as well as variable speed reproduction, and corrects the rotation head. We have previously proposed a digital signal recording / reproducing apparatus that can control and achieve compatibility between devices and can simplify a circuit configuration when reproducing by switching a plurality of reproducing speeds.

First, FIG. 1 to FIG.
This will be described with reference to FIG.

FIG. 1 shows the circuit configuration, in which a pilot signal for tracking and a signal for erasure are recorded for convenience, and are reproduced by normal reproduction and variable-speed reproduction, for example, at double speed and 3 times.
Only a circuit configuration for switching and performing reproduction at double speed is shown, and a circuit configuration for recording and reproducing, for example, a PCM signal as recording information is omitted.

In the figure, (1A) and (1B) are rotating heads, (2)
Is a magnetic tape as a recording medium. Rotating head (1
As shown in FIG. 2, (A) and (1B) are arranged at the peripheral portion of the drum (3) at regular angular intervals, that is, at intervals of 180 degrees. On the other hand, if the magnetic tape (2) is smaller than its 180 degree angle range around the tape guide drum (3), for example, 90
Wound over the angle range. Then, the rotating heads (1A) and (1B) rotate at the rate of 30 rotations per second (4).
H), the tape (2) is run at a predetermined speed in the direction shown by the arrow (4T), and the rotating heads (1A) and (1B) place a third tape on the magnetic tape (2). One diagonal magnetic track (5A) as shown
(5B) is formed, for example, in a so-called overwritten state. That is, the width of the head gap (scanning width)
W is made larger than the track width. In this case, the width direction of the gap between the heads (1A) and (1B) is different from the direction orthogonal to the scanning direction. That is, the so-called azimuth angles are made different.

Then, a period during which the two rotating heads (1A) and (1B) do not contact the tape (2) together (this is the case in this example)
A period corresponding to a 90-degree angular range) is generated, and if this period is used to add redundant data at the time of recording and to perform correction processing at the time of reproduction, the apparatus can be simplified.

(6) is an oscillator for generating the tracking pilot signal P. The pilot signal P has, for example, a frequency f ₀ of a relatively large value of azimuth loss, that is, a frequency at which azimuth loss is effective, for example, about 130 kHz, and a relatively high frequency. Recorded at a high level. Note that this pilot signal P
Is preferable to be a frequency with relatively small azimuth loss as long as linearity of tracking phase shift versus pilot reproduction output can be guaranteed. Further, (6A) is an oscillator for generating an erasing signal E of the pilot signal, and the erasing signal E is recorded on a previously recorded tape,
Later, when a new recording is performed while erasing the previous recording information, the recording track does not always match the previous recording track, so the previously recorded pilot signal needs to be erased. Is used for
Its frequency f _1, the frequency f ₀ of the pilot signal be those around the practically separated for example 700 kHz, and are relatively high frequency of azimuth loss. Also, the recording level is such that the pilot signal P can be practically erased. The erasing signal E is used here as a positioning signal for detecting the position of the pilot signal.

Further, (6B) is a generator for generating an erase signal E ₀ of another and the erasing signal E above, the erase signal E ₀ is
Thus when overwriting pilot signal P and the erase signal E, which like the signal P and preferably has a high erasure rate of E, As the frequency f ₂ is used. For example, about 2MHz.

(7), (7A) and (7B) are recording waveform generation circuits, which are output from edge detection circuits (8A) and (8B) for detecting edges, for example, falling edges of delay signals related to the pulse PG described later. In response to the outputs, respectively, the generating circuits (7) and (7A) generate a number of pilot signals P per track based on the pilot signal and the erasing signal from the oscillators (6) and (6B).
And a predetermined time t _P (where t _P is each pilot signal and the erasing signal E ₀₎ depending on the arrangement of the erasing signal E ₀ and the arrangement thereof.
Recording time, provided that the one recording recording time is per area time in succession in the track (5A) t _P, track (5B) in put together the two points of time apart time t _P of the erasing signal E ₀ of The pilot signal P and the erasure signal E ₀
The generation circuit (7B) is provided with an erasing signal E from the oscillator (6A).
A predetermined time according to how many erase signals are inserted per track and in what arrangement based on the The erasing signal E having, occurs at predetermined intervals T _1. (8
F) is an OR circuit that logically processes the outputs of the generating circuits (7), (7A) and (7B). (9) is a rotating head (1
A switching circuit for switching between A) and (1B), wherein a switching signal S from a timing signal generation circuit (10) is provided.
₁ (FIG. 4A). The timing signal generating circuit (10) includes a rotary head (1A) (1B) obtained in synchronization with the rotation of the rotary drive motor (12) of the rotary heads (1A) (1B) from the pulse generator (11). A pulse PG of 30 Hz indicating the rotation phase of ()) is supplied. Also the pulse
A 30 Hz pulse from the timing signal generation circuit (10) is supplied to the PG to the phase servo circuit (13), and the rotation phase of the motor (12) is controlled by the servo output.

Pilot signals from the switching signal S ₁ by the switched switching circuit (9) from the timing signal generating circuit (10) comprises an amplifier (14A) or respectively switching circuit after being amplified by (14B) (15A) or (15B ) Is supplied to the rotary head (1A) or (1B) through the contact R side of the magnetic tape (2).
Recorded above. The switch circuits (15A) and (15B) are connected to the contact R side during recording, and are switched to P side during reproduction.

Also, the output signal from the timing signal generation circuit (10)
S ₂ (FIG. 4C) is supplied to the delay circuit (16), and after a delay corresponding to the interval between the mounting positions of the rotary heads (1A) (1B) and the pulse generator (11) is made. Is supplied to the input side of the edge detection circuit (8A) to detect an edge, for example, a falling edge, as a recording reference of the pilot signal. The fall of the signal S ₃ (FIG. 4D) delayed by the delay circuit (16) is set to coincide with the time when the first head comes into contact with the tape during one rotation period.

(17A), (17B), (17C), (17D) and (17
E) is the delay time T ₁ (time corresponding to the interval between the pilot signal P recorded on one track, the erasing signal E and E ₀ , respectively), T ₂ (2T ₁ ), and T (half rotation period of the head) Time corresponding to), t _P and Is a delay circuit having: Signal S ₃ from delay circuit (16)
(FIG. 4D) are supplied to delay circuits (17A) to (17C), respectively. The signal S ₄ (FIG. 4E) from the delay circuit (17A) is supplied to the edge detection circuit (8A), and the signal S ₅ (FIG. 4F) from the delay circuit (17B) is supplied to the edge detection circuit (8B). , And the signal S ₆ (FIG. 4G) from the delay circuit (17C) is directly supplied to the edge detection circuit (8B), and the time T ₁ and the time T ₁ are supplied to the delay circuits (17A) and (17B), respectively. is supplied to only ₂ is delayed by the signal S ₇ (FIG. 4 H) and the signal S ₈ (FIG. 4 I) as an edge detection circuit (8B) and (8A).

The signal S ₉ from the edge detection circuits (8A) and (8B) (fourth
FIG. J) and the signal S ₁₀ (FIG. 4K) are each a delay circuit (17D)
And (17E) at time t _P and The signal is delayed and becomes a signal S ₁₁ (FIG. 4L) and a signal S ₁₂ (FIG. 4M). Signal S ₁₁ is the time delay circuit (17E) is supplied to one input terminal of the OR circuit (8C) The signal is delayed and becomes a signal S ₁₃ (FIG. 4N). The signal S ₁₃ time delay circuit (17E) together is supplied to one input terminal of the OR circuit (8D) Time is the delay signal S ₁₄ (FIG. 4 O), and the delay circuit together with the signal S ₁₄ is supplied to one input terminal of the OR circuit (8E) (17E) The signal is delayed and becomes the signal S ₁₅ (FIG. 4P), and the OR circuit (8
D) Supplied to others.

Further, the signal S ₁₂ is the time t _P delayed by the delay circuit (17D) is supplied to the multi-input terminal of the OR circuit (8E) and the signal S ₁₆
(Fig. 4 Q), and the further delay circuit together with the signal S ₁₆ is supplied to another other input terminal of the OR circuit (8D) (17D)
The signal is delayed by the time t _P to become a signal S ₁₇ (FIG. 4R), which is supplied to the other input terminal of the OR circuit (8C).

Signal S from OR circuit (8C), (8D) and (8E)
₁₈ (FIG. 4S), signal S ₁₉ (FIG. 4T) and signal S ₂₀ (FIG. 4U) are substantially gate signals to the recording waveform generating circuits (7), (7A) and (7B), respectively. And pilot signals P, from generators (6), (6B) and (6A), respectively.
The erasing signals E ₀ and E are supplied to the output side of the OR circuit (8F) via the recording waveform generating circuits (7), (7A) and (7B).
₂₁ (FIG. 4V).

The (18A) and (18B) switch circuits (15A) (15
An amplifier to which reproduction outputs from the corresponding rotary heads (1A) and (1B) are supplied when B) is switched to the contact P side. Each output of these amplifiers (18A) and (18B) is a switch circuit. (19). The switch circuit (19) receives the 30 Hz switching signal S ₁ ′ from the timing signal generation circuit (10).
According to (FIGS. 5A, 6A and 7A), at the same time as recording, a half rotation period including the tape contact period of the head (1A) and a half rotation period including the tape contact period of the head (1B). It is switched alternately with the period.

(20) is a narrow-band band-pass filter of the central pass frequency f ₀ that extracts only the pilot signal P from the reproduced output from the switch circuit (19), (21) in order to improve the response characteristics, the filter (20) A peak hold circuit for holding the peak value of the output of the sampling circuit, (22) is a sampling hold circuit for sampling and holding the held peak value, and (23) is a peak hold circuit (21) and a sampling hold circuit. A comparison circuit for comparing each output of (22), for example, a differential amplifier, and (24) is a sampling and holding circuit for sampling and holding a comparison error signal from the differential amplifier (23). (22) and (24) are, as will be described later, substantially the two adjacent tracks adjacent to the track currently being scanned during normal reproduction. At both ends and the center of the rack, or at the center or end of the track currently being scanned during double-speed playback, and at the two adjacent tracks adjacent to the track adjacent to the track being scanned during triple-speed playback. It works to sample and hold the crosstalk of each pilot signal recorded in the center part or both ends. Then, the output of the sampling and holding circuit (24) is taken out to the output terminal (26) via the switch circuit (25) as a tracking control signal.

Further, in order to form a sample and hold circuit (22) (24) sampling pulses or the like for, the central pass frequency f ₁ for taking out only the erasing output E of reproducing output to the output side of the switch circuit (19) narrow A band-pass filter (29) for the band is provided, and its output S _E (FIGS. 5K, 6I, and 7K) is waveform-shaped by a waveform shaping circuit (30), and the signal S ₂₂ (5th FIG. L, FIG. 6J, and FIG. 7L). As the waveform shaping circuit (30), although not shown, for example, a comparator having a certain reference value, or a comparator provided with an envelope detector at a stage preceding the comparator is used.

(31) is a rise detection circuit for detecting the rise of the signal from the waveform shaping circuit (30). As described later, the rise of the erase signal is detected every half-rotation period of the head. The output of the detection circuit (31) includes a plurality of gate circuits (33 _1), (33 _2), (33 _3), (33 _4), (33 ₅₎
And it is supplied to the (33 _6), the window signal from the window signal generator circuit (34) as a gate signal using the counter example S _W1 to S _W6 (Fig. 5 C to H) are used.
Window signal generating circuit (34) comprises a clock terminal (4 in response to the output signal S ₂ from the timing signal generating circuit (10)
Counting the clock from 2), generated in response to the window signal of a predetermined width adapted to cover the end edges of at least the above-mentioned signal S ₂₂ into a plurality of playback modes.

In other words, the window signal generator circuit (34) receives the command signal of the normal reproduction mode setting from the mode setting circuit (32) sequentially generates a window signal S _W1 to S _W6, also,
When the command signal for setting the double speed playback mode is received, only the window signal _SW2 , _SW5 or _SW3 , _SW4 is generated, and when the command signal for setting the triple speed playback mode is received, the window signal S
Only _W2 , _SW5 or _SW1 , _SW3 and _SW4 , _SW6 are generated.

Therefore, each output of the gate circuit (33 ₁₎ to (33 _6), only is derived edges of the signal S _22, which has entered the period of the window signal S _W1 to S _W6 of this like, an OR circuit ( output side to the output signal S ₂₃ of 35) (FIG. 5 M, Fig. 6 K, Fig. 7 M)
And supplied to one input side of a delay circuit (36) using a counter as a start pulse.

Furthermore, provided a plurality of delay time setting circuit (38) and (39), the setting circuit (38) is substantially sampling start a pilot signal from the time point of generation of double speed and triple speed reproduction signal S ₂₃ set the delay time ta until the setting circuit (39), when double-speed reproduction, the delay time than time point of generation of the signal S ₂₃ to the virtual sampling point of the pilot signal
Set tb.

Each of the delay times set by the setting circuits (38) and (39) in this way is determined by the delay time setting selector (37).
Window signal S _W1 to S from the window signal generator (34)
_The signal is selected by _W6 and supplied to the other input side of the delay circuit (36). Therefore, the delay circuit (36) is a counter counts a clock from the signal S ₂₃ directly if the delay is not required as a start pulse, or delay by the set time if necessary clock terminal (42) At the end of the counting, a narrow signal S ₂₄ (FIG. 5N, FIG. 6L and FIG. 7N) is generated on the output side.

(43), for example a pulse generation circuit using a counter, counts the clocks from the clock terminal of the signal S ₂₄ from the delay circuit (36) as a trigger pulse (42),
At the time of normal reproduction and at the time of 3 × speed reproduction (the first method), a pair of pulses Pi (FIG. 5O, FIG. 7O) are provided at predetermined intervals.
Also, at the time of double speed reproduction and at the time of triple speed reproduction (the second method)
Then, one of the pair of pulses Pi (FIG. 6M, P, FIG. 7R) is generated corresponding to each pilot signal to be detected. The pulse Pi is supplied to a peak hold circuit (21) and to a sampling pulse generating circuit (44) using, for example, a D-type flip-flop circuit.

Sampling pulse generator (44) in response to the pulse Pi, it generates a sampling pulse SP _1, SP ₂ the sampling and hold circuit (22) and (24).

Reference numeral (51) denotes a comparison circuit provided on the output side of the filter (29), and the comparison circuit (51) includes the filter (2).
Output 9), i.e. by comparing the reference value from the reproduction output and the reference power source (52) of the erasing signal E, reproduction output is the output signal if exceeding the reference value, for example S ₂₅ a (FIG. 8 C) It is generated and supplied to the clock terminal of the D-type flip-flop circuit (53) as a latch pulse. The switching signal S ₁ from the timing signal generating circuit (10) 'circuit for detecting, for example, falling of (54) is provided, the switching signal S _1' in synchronization with the falling edge of the output signal S ₂₆ (8 Figure E)
The reset signal is supplied to the reset terminal R of the flip-flop circuit (53). Further, the switching signal S ₁ ′ is inverted by the inverter (55) to become the signal ▼ (FIG. 8F), which is supplied to the input terminal D of the flip-flop circuit (53).

Further, a circuit (56) for detecting, for example, a rising edge of the switching signal S ₁ ′ is provided, and an output signal S ₂₇ (FIG. 8G) is generated in synchronization with the rising edge of the switching signal S ₁ ′. It is supplied to the clock terminal of the type flip-flop circuit (57). The input terminal D of the flip-flop circuit (57) output signal S ₂₈ of the flip-flop circuit (53) (FIG. 8 H) is supplied, the output signal S ₂₉ of the flip-flop circuit (57) (FIG. 8 I) Are used as switching control signals for the switching circuit (25). That is, the switch circuit (25) as described later, is connected to the contact a side when the control signal S ₂₉ is one level for example high (H), and takes out a tracking control signal to the output terminal (26) performing a normal operation Te also taken out is connected to the contact b when the control signal S ₂₉ is the other level such as low level (L), the pin (58) output terminals a constant voltage Vcc from (26) This is supplied to the capstan servo system as a tracking control signal to force the head being scanned into a normal tracking state.

Next, the circuit operation of FIG. 1 will be described with reference to the signal waveforms of FIGS.

First, at the time of recording, in response to a pulse PG from the pulse generator (11) indicating the rotation phase of the rotary heads (1A) (1B), the timing signal from the timing signal generation circuit (10) is as shown in FIG. signal S ₂ is generated, the signal S ₂ is delay circuit (1
6) a predetermined time T _R is delayed, on its output side signal S ₃ shown in FIG. 4 D output with. This signal S ₃
Is supplied to the edge detection circuit (8A) directly and via the delay circuits (17A) and (17B) as described above, where the edge (falling edge) is detected, and the output side is synchronized with this edge. signal S ₉ narrow as shown in FIG. 4 J is generated in. Also, the signals S ₅ , S ₆ and S ₇ from the delay circuits (17B), (17C) and (17A) are supplied to an edge detection circuit (8B), where the edge (falling edge) is detected. In synchronization with this edge, a signal as shown in FIG.
S ₁₀ is generated. Signals S ₉ and S ₁₀ are delay circuits (17D)
And (17E) to be delayed as described above (see FIGS. 4L to 4R). As a result, the OR circuits (8C) to (8C)
E) at the output side is a signal S as shown in FIGS.
₁₈ to S ₂₀ is taken out, by which such signals S _18, S ₁₉ and S ₂₀ of substantially the head (1A), (1B) by the pilot signal P, the recording of the erasing signal E ₀ and the erase signal E The starting criteria are each determined.

The signals S ₁₈ , S ₁₉ and S ₂₀ are supplied to recording waveform generating circuits (7), (7A) and (7B), respectively, and the recording waveform generating circuit (7) oscillates in synchronization with the supplied signal S _18. becomes a pilot signal P from (6) to the fourth at predetermined intervals as shown in FIG. S passes the predetermined time t _P, also the recording waveform generating circuit (7A) is synchronized with the signal S ₁₉ supplied substantially now pass the predetermined time t _P at predetermined intervals as shown the erasing signal E ₀ from the oscillator (6B) in FIG. 4 T Te, further, recording waveform generator circuit (7B) is fed predetermined time erasing signal E from the signal S ₂₀ to the synchronization with the oscillator (6A) at predetermined intervals as shown in FIG. 4 U was Only let through.

Recording waveform generator circuit (7), is added in (7A) and (7B) the output signal from the OR circuit (8F), at its output side signal S ₂₁ shown in FIG. 4 V is taken out with.

Incidentally this time, for example, consider the case where the head (1B) is recording tracks (5B ₂₎ in Figure 3, the first signal S ₁₈ in FIG. 4 S, the second and third pulses each pilot corresponding to the signal P _A2, P _A4 and P _A6, the first signal S ₁₉ in FIG. 4 T, the second and third pulses, both sides and the erasing signal E _A6 of the erasing signal E _A2, E _A4 corresponding to the erase signal E ₀ for each adjacent to one side, also, the first signal S ₂₀ in FIG. 4 U, the second and third pulses each said E ₀
Corresponding to the erasing signals E _A2 , E _A4, and E _A6 adjacent to, and signals corresponding to the arrangement of these signals, that is, P _A2 , E ₀ , EA ₂ ,
A composite signal of E ₀ and P _A4 , E ₀ , E _A4 , E ₀ and E _A4 , and E ₀ and P _A6 is extracted to the output side of the OR circuit (8F) for each group.

Further, for example, it is considering a case where the head (1A) is recording tracks (5A ₂₎ in FIG. 3, first, second and third pulses each pilot signal P of the signal S ₁₈ in FIG. 4 S _B2, corresponding to P _B4 and P _B6, the first signal S ₁₉ in FIG. 4 T, the second and third pulses, erasing signal
E _B2, corresponding to the erase signal E ₀ for each adjacent to both sides of one side and the erasing signal E _B6 of E _B4, The signal in Figure 4 U
The in S ₂₀ 1, second and third pulse corresponds to the erase signal E _B2, E _B4 and E _B6 adjacent respectively above E _0, signal or E _B2, E which like corresponding to the arrangement of the signal ₀ , P _B2 and E _B4 ,
A composite signal of E ₀ , P _B4 and P _B6 , E ₀ , E _B6 , E ₀ is extracted to the output side of the OR circuit (8F) for each group.

On the other hand, from the timing signal generating circuit (10) includes a pulse generator (11) switching signal S ₁ as shown in FIG. 4 A in response to the pulse PG from are generated, the signals S ₁ is rotated head (1A) is synchronized with the rotation of (1B), as shown in Figure 4 a and B, in a half turn period t _a of the head signals S ₁ is at the high level heads (1A) is a tape ( abuts the 2), the signal S ₁ is the head (1B) is a relationship as to be in contact with the tape (2) at half the rotational period t in _B, which is a low level. Then, the switching circuit (9) switching signal S _1, in the state of FIG. In the period t _A, the opposite state to the state of FIG period t _B, respectively switched, head switching is performed.

Therefore, the signal S ₂₁ obtained on the output side of the OR circuit (8F)
When the switch circuit (9) is in the opposite state to the state diagram, an amplifier (14B) and through the R side of the switch circuit (15B) is supplied to the head (1B), in the period t _B the beginning of the contact period the tape (2) of the head (1B), in the middle and the end, as shown in FIG. 3, equidistant l (T ₁ or equivalent) from the longitudinal center position of the track (5B) only Time is recorded in the tracking signal recording areas A _T1 and A _T2 provided at both ends in the longitudinal direction of the separated track (5B), respectively. And recorded in the same recording area _AT3 provided in the center of the track (5B). Recorded during.

Meanwhile when the switch circuit (9) is in the state diagram, the signal S ₂₁ is R amplifier (14A) and a switch circuit (15A)
At the beginning, in the middle and at the end of the abutment period of the head (1A) with the tape (2) during the period t _A , as shown in FIG. The recording areas A _T1 and A _T2 similar to those described above provided at both ends in the longitudinal direction of the track (5A) separated by an equal distance l (corresponding to T ₀ ) from the central position in the longitudinal direction of the track (5A) When And recorded in the same recording area _AT3 provided at the center of the track (5A). Recorded during.

Except for the time when these pilot signals and the erasing signal are recorded, an audio PCM signal of one segment portion to be recorded as one track, not shown,
Spaced t through the _A amplifier (14A) is supplied to the head (1A), the period t _B in the head via the amplifier (14B) (1B)
And recorded in the recording areas _AP1 and _AP2 of the tracks (5A) and (5B) other than the recording area of the pilot signal.

Next, reproduction of the signal recorded as described above will be described.

Also at the time of reproduction, the drum (12) is subjected to drum phase servo by the phase servo circuit (13) in the same manner as during recording.

First, during normal playback, the rotating head (1A)
The signals extracted from the tape (2) by (1B) and (1B) are respectively connected to the contact P side of the switch circuit (15A) and the amplifier (18).
A) and the contact P side of the switch circuit (15B) and the amplifier (18
It is supplied to the switch circuit (19) via B). The switch circuit (19) is half turn comprising a tape contact period in the same manner as when the recording head (1A) by the timing signal generating circuit (10) a 5 30 Hz switching signal S ₁ as shown in Figure A from ' and duration t _a, is alternately switched between the half rotation period t _B containing tape contact period of the head (1B). Therefore, this is a switch circuit (19) obtained intermittent PCM signal S _R of the one segment, such as FIG. 5 I, which is supplied to also play a processor not shown demodulated to the original PCM signal The data is further supplied to a decoder, where data for each block is detected by a block synchronization signal, and processing such as error correction and de-interleaving are performed. The data is returned to an analog audio signal by a D / A converter and is derived to an output side. You.

Tracking control is performed as follows.

Now, for example, if the head (1B) scans a range of the scanning width W including the track (5B ₂ ) as shown by the dashed line in FIG. 3, the head (1B) will be located on both sides of this track (5B ₂ ). track (5A ₂₎ (5A ₁₎ scans across a pilot signal P _A2 of the track 5B ₂ in the area a _T1 as shown in FIG. 3, the track of two neighboring (5
Reproduces the pilot signal P _B1 pilot signal P _B2 and the track of the A ₂₎ (5A _1), a pilot signal P _A4 tracks (5B ₂₎ in the region AT _3, track two neighboring (5A
₂₎ reproduces the pilot signal P _B3 of the pilot signal P _B4 and track (5A ₁₎ of the pilot signal P _B6 and track of the track of the two neighboring in the region T ₂ (5A ₂₎ (5
A ₁ ) pilot signal P _B5 and a track (5A ₂ ) pilot signal P _A6 are reproduced. At this time, the switch circuit (1
The reproduction output of the head (1B) from 9) is the pass center frequency f ₀
It is supplied to the narrow band pass filter (20) and, as its output S _F as shown in FIG. 5 J only the pilot signal is extracted, which is supplied to the peak hold circuit (21).

Further, the output S _R of the switch circuit (19) is supplied to a band-pass filter (29), the erasing signal S _E as shown in FIG. 5 K of the frequency f ₁ at thisゝretrieved. This signal is supplied to a waveform shaping circuit (30) and a signal as shown in FIG.
Is a S _22, then supplied to the rise detecting circuit (31), is detected its rise in thisゝgate circuit (3
3 ₁₎ is fed to (33 _6).

The window signal generation circuit (34) outputs a signal as shown in FIG. 5B from the timing signal generation circuit (10).
In response to S _2, window signal as shown in FIG. 5 C~H
S _W1 to S _W6 are sequentially generated gate circuit (33 ₁₎ to (33 ₆₎
Is supplied as a gate signal to, therefore, on the output side of which, such as gate circuits, only the signal entering during each period of the window signal S _W1 to S _W6 is substantially removed, resulting in a gate circuit (33 ₁₎ to the output side of the - (OR circuit at the output side of the 33 ₆₎ (35), as shown in FIG. 5 M, signal S ₂₂
That erasing signal S _E (period t in in _{B E A2, E A4, E} A6,
In the period _{t A E B2, E B4,} E B6) narrow matches the starting end of the signal S ₂₃ is obtained.

The signal S ₂₃ is supplied to the delay circuit (36). However, this signal S ₂₃ is in the normal reproduction is not necessary to delay because it matches near the center of the pilot signal to be sampled, thus setting the delay time for the delay circuit (36) by the time selector (37) Is not done,
Delay circuit (36), as shown in FIG. 5 N, sequentially generates a signal S ₂₄ that matches the signal S _23.

The signal S ₂₄ is supplied to a pulse generating circuit (43), wherein as shown in FIG. 5 O on the basis of the signal S _24, a pair of pulses Pi corresponding to each pilot signal to be detected
Is formed and supplied to the sampling pulse generation circuit (44) and the peak hold circuit (21). Then, from the sampling pulse generating circuit (44), based on the pair of pulses Pi, Figure 5 sampling pulse shown in P and Q SP ₁ and SP ₂ is generated, each sampling hold circuit (22) and (24).

Such pulse Pi obtained by the difference formed on the basis of the pulse Pi is supplied to the peak hold circuit (21) sampling pulses SP ₁ and SP ₂ is each sampling hold circuit (22) and (24) Will be supplied.

Therefore, during the scanning by the head (1B) tracks (5B _2), as is apparent from FIG. 5, the first pulse P _i1 pulse Pi is transported indicated by the arrow (4T) (Figure 3) The crosstalk between the pilot signals P _B2 , P _B4 and P _B6 of the adjacent track (5A ₂ ) on the opposite side to the direction is peak-held in the peak hold circuit (21), and the peak hold circuit (21) The output is supplied to a sampling and holding circuit (22), where it is sampled by a sampling pulse SP1 generated at the falling edge of the first pulse _Pi1 , and _one of the differential amplifier (23) is used as a leading phase tracking signal. Is supplied to the input terminal of

The second pulse P of the pulse Pi _i2 becomes a state of peak hold in the adjacent tracks of the tape transport direction side peak hold circuit crosstalk of the pilot signals P _B1, P _B3 and P _B5 of (5A ₁₎ (21) The output of the peak hold circuit (21) at this time is supplied to the other input terminal of the differential amplifier (23) as a tracking signal having a delayed phase. Therefore, the differential amplifier (23)
The _B2 and P _B1, P _B4 and P _B3, tracking signals respectively corresponding to the crosstalk P _B6 and P _B5 to rank comparison. The comparison error signal from the differential amplifier (23) is supplied to the sampling hold circuit (24), it is sampled by the sampling pulse SP ₂ generated at the falling edge of the second pulse P _i2 in thisゝ. Therefore, the difference between the two inputs to the differential amplifier (23) is obtained as a tracking control signal from the sampling and holding circuit (24), and this is sent from the output terminal (26) via the contact a of the switch circuit (25). Although not shown, the tape transfer amount is supplied to the capstan motor to control the tape transfer amount, and the level difference between the two inputs to the differential amplifier (23) is zero, that is, the head (1B) scans the track (5B ₂ ). At this time, the two tracks (5A ₂ ) and (5A ₁ ) on both sides are controlled so as to extend by the same amount. That is, control is performed so that the center position in the width direction of the gap of the head (1B) coincides with the center position of the track (5B ₂ ) to perform scanning.

Also, performed similarly with the other tracks, for example when scanning tracks (5A ₂₎ head (1A) is, as shown in the right portion of FIG. 5, a track of the two neighboring (5B ₃ ) And (5B ₂ ) pilot signals P _A7 , P _A9 , P
_Since crosstalk between _A11 and P _A2 , P _A4 , and P _A6 is obtained, these are sequentially peak-held by the peak hold circuit (21) as described above, and supplied from the sampling pulse generation circuit (44) to the sampling hold circuit (22). The tracking signal is obtained by sampling the crosstalk of the pilot signals P _A7 , P _A9 , and P _A11 with the sampling pulse SP ₁ to be obtained.
This was supplied to the output of the peak hold circuit (21) corresponding to the crosstalk of the pilot signals P _A2, P _A4, P _A6 supplies the next stage of the differential amplifier (23), a thisゝ, pilot signal in P _A7 and P _A2, P _A9 and P _A4, P _A11 and compares the respective corresponding tracking signal to crosstalk P _A6, the sampling pulse SP ₂ supplied to the comparison error signal to the sampling hold circuit (24) By sampling, a tracking control signal for the head (1A) can be obtained.

Similarly, when the head (1B) scans the track (5B ₃ ), as shown in FIG. 3, the pilot signals P _B7 , P _B7 , of the adjacent tracks (5A ₃ ) and (5A ₂ )
Since crosstalk P _B9, P _B11 and P _B2, P _B4, P _B6 is obtained by sampling the crosstalk of the pilot signals P _B7, P _B9, P _B11 sampling pulse SP _1, a differential amplifier (23) in a pilot signal P _B7 and P _B2, P _B9 and P _B4, P _B11
Comparing each corresponding tracking signal to crosstalk P _B6, by sampling the comparison error signal finally sampling pulse SP _2, it is possible to obtain a tracking control signal for the head (1B).

Then, at the time of double-speed playback, it scans the position shown by the broken line T _D in Fig. 3 so as to pass the center of the gap width of the rotary head. That is, one of two adjacent recording tracks (5A) and (5B) formed by two rotating heads having different azimuth angles at the time of recording, for example, the track (5B) is applied to the tape of each rotating head (1A) (1B). The scanning is performed in the first half of the contact period, while the track (5A) is scanned in the latter half, for example.

 In this manner of scanning, the rotating heads (1A) and (1A)
The signals extracted from tape (2) by B)
The contact P side of the switch circuit (15A) and the amplifier (18A) and switch
Via the contact P side of the switch circuit (15B) and the amplifier (18B)
It is supplied to the switch circuit (19). This switch circuit
(19) is a timing signal generation circuit (10) from FIG.
30Hz switching signal S as shown in₁'As in recording
Half rotation period t including the head (1A) tape contact period_AWhen,
Half rotation period t including the tape contact period of the head (1B)_BAnd in
Alternately switched. Therefore, this switch circuit
From (19), intermittent one segment at a time as shown in Fig. 6G
PCM signal S This is a playback processor (not shown).
Demodulated to the original PCM signal, and then decoded.
The data is supplied to the
Data is detected and error correction, de-interleaving
Processing is performed, and analog audio is output by the D / A converter.
The output signal is returned to the output side.

Tracking control is performed as follows.

Now, for example, when the head (1B) is to be scanned in a direction as shown by the broken line T _D across two tracks (5A ₂₎ (5B ₃₎ In FIG. 3, the head (1B) is shown in Figure 3 reproduces the pilot signal P _A7 tracks (5B _3), and a pilot signal P _B2 of the track pilot signals P _A2 and track (5B ₂₎ (5A ₂₎ in the region a _T1 as region a
_{At T3} , the pilot signal P _A9 of the track (5B ₃ )
The track (5B ₂ ) pilot signal _PA4 and the track (5A
₂₎ reproduces the pilot signal P _B4, the pilot signal P _B11 of the track (5A ₃₎ in the region A _T2, track (5
A ₂ ) pilot signal P _B6 and a track (5B ₃ ) pilot signal P _A11 are reproduced. At this time, the switch circuit (1
The reproduction output of the head (1B) from 9) is the pass center frequency f ₀
, And only the pilot signal is taken out as its output _SF as shown in the left part of FIG. 6H, and this is supplied to the peak hold circuit (21). .

Also, for example a track (5A ₃₎ and (5B ₄₎ of the head tracks of two in the direction as shown by the broken line T _D in FIG. 3 (1A)
There When scanning is a pilot P _A8 tracks (5B ₄₎ in the region A _T1 shown in the figure, the pilot signal P _B7 track pilot P _A7 and tracks (5B ₃₎ (5A ₃₎
Playing the door, the pilot signal P _A10 tracks (5B ₄₎ in the region A _T3, pilot signals P _B9 tracks (5B ₃₎
Playing the door, in the area A _T2 reproduces the pilot signal P _A12 tracks (5A ₄₎ of the pilot P _B12, pilot signals P _B11 and tracks (5B ₄₎ of the track (5A _3). At this time, the head (1A) from the switch circuit (19)
Is output to a band-pass filter (20),
As the output S _F as shown in the right portion of FIG. 6 H) only the pilot signal is extracted, which is simultaneously supplied to the peak hold circuit (21).

The output S _R of the switch circuit (19) is supplied to the band-pass filter (29) in the same manner as described above, and the erasing signal S _E (typically during the period t _B ) as shown in FIG. E _A7 ,
E _A9 , E _A11 , typically E _B7 , E _B9 , E _B11 during the period t _A )
Is taken out. The signal S _E is the signal S ₂₂ as shown in FIG. 6 J are supplied to the waveform shaping circuit (30), then is supplied to the rising detection circuit (31), is detected its rise in thisゝgate It is supplied to the circuit (33 ₁₎ to (33 _6).

At the time of 2 × speed reproduction, the window signal generation circuit (34) outputs the window signals _SW2 and _SW as shown in FIGS. 6C and 6F according to the setting command signal from the mode setting circuit (32).
_W5 is generated gate circuit (33 ₂₎ and (33 ₅₎ is supplied as a gate signal to, thus the gate circuit (33 ₂₎
At the output of (33 ₅ ), only the rising edge of the signal S ₂₂ , which has entered during the period of the window signals SW ₂ and SW ₅ , is substantially taken out, and consequently the gate circuits (33 ₂ ) and (33 ₅ ) the output side of the OR circuit at the output side of ₅₎ (35), as shown in FIG. 6 K, a narrow width of the signal S ₂₃ that respectively match with the rise of the signal S ₂₂ is obtained.

The signal S ₂₃ is supplied to the delay circuit (36). Also,
At this time, the delay time setting circuit (38) is selected by the selector (37), and the delay time ta is set for the delay circuit (36). Delay circuit (36), during the period t _B, as shown in the left part of FIG. 6 L, generates a signal S ₂₄ which is delayed by the time Ta from the signal S _23, the time t _A in Figure 6 L as shown in the right portion, for generating a signal S ₂₄ that matches the signal S _23.

The signal S ₂₄ is supplied to a pulse generating circuit (43), wherein as shown in FIG. 6 M on the basis of the signal S _24, the pulse Pi corresponding to each pilot signal to be detected is formed, the sampling pulses The signal is supplied to the generation circuit (44) and the peak hold circuit (21).

In the time of this double-speed playback, starting with 1 rotation period of the two periods or head of period t _B and t _A so as to obtain the single tracking error signal.

Therefore, the thisゝ, for example the period t first end appears pilot signal in the central region of the track being scanned by the pulse P _i1 pulse Pi from the pulse generating circuit in _B (43), ie the head (1B) is a track When scanning over (5A ₂ ) and (5B ₃ ), the cross talk of the pilot signal P _B4 of the track (5A ₂ ) is peak-held by the peak hold circuit (21) as shown in FIGS. , On the other hand
The second end appears pilot signal in the central region of the track being scanned by the pulse P _i2 pulse Pi from t _A the pulse generating circuit (43), that the head (1A) is a track (5A ₃₎ (5B ₄ ), The pilot signal P of the track (5B ₄ ) as shown in FIGS.
_{Make A10} crosstalk peak hold.

Therefore, the first pulse P _i1 only occurs, the other scanning period eg period of the head t _A the pulse Pi of the one scan period eg period t _B in the pulse Pi of a pulse generating circuit (43) In this mode, head Only the second pulse P _i2 is generated.

As described above, for example, when the bed (1B) scans over _two tracks (5A ₂ ) and (5B ₃ ), the crosstalk of the pilot signal P _B4 in the area _AT3 is generated by the pulse generation circuit (43). The first pulse P _i1 of the pulse Pi
In FIG. M), the peak is held by the peak hold circuit (21), and the output of the peak hold circuit (21) is sampled and held by the sampling pulse SP ₁ (FIG. 6N) from the sampling pulse generation circuit (44). In order to make the same polarity as the tracking error signal at the time of normal reproduction sampled in (22),
It is supplied to the other input terminal of the differential amplifier (23).

The head (1A) is two tracks and (5A ₃₎ (5
B ₄ ) When scanning across two tracks, the area
Second pulse P of the pulse Pi crosstalk pulse generating circuit of the pilot signal P _A10 in A _T3 (43) _i2 (Sixth
In FIG. M), the peak is held by the peak hold circuit (21), and the output of the peak hold circuit (21) at this time is supplied to one input terminal of the differential amplifier (23).

Then, the comparison error signal (tracking error signal) from the differential amplifier (23) at this time is input to the sampling pulse generation circuit (44) in the sampling and holding circuit (24).
The signal is sampled by a sampling pulse SP ₂ (FIG. 6O), and is derived as a tracking control signal to the output terminal (26) via the contact a side of the switch circuit (25).

The derived control signal is supplied to the capstan motor to control the amount of tape transport, and the differential amplifier (23)
The level difference between the two inputs is zero, that is, the head (1B) extends over _two tracks, tracks (5A ₂ ) and (5B ₃ ), and the head (1A) extends over two tracks, tracks (5A ₃ ) and (5B ₄ ). when scanning, the scanning trajectory as shown by a broken line T _D is the rotary head is controlled so as to draw in Figure 3.

In the above-mentioned double speed reproduction, the crosstalk of the pilot signal recorded in the center area of the track being scanned is used. However, as shown in FIGS. The crosstalk of the pilot signal recorded at the end of the track may be used.

For example, the period t at _B in the end region of the track being scanned crosstalk finally appears pilot signal P _A11, the peak hold circuit (21), the first pulse P of the pulse Pi as shown in FIG. 6 P and peak hold at _i1, whereas the period t crosstalk of the pilot signals P _B7 last occurrence at the beginning region of the track _a in during scanning, the peak hold circuit (21), pulses as shown in FIG. 6 P
The peak is held at the second pulse _Pi2 of Pi.

And in the period t _B, the output of the peak hold circuit (21), the sample and hold circuit (22), and sampled by the sampling pulse SP ₁ shown in FIG. 6 Q from the sampling pulse generating circuit (44) Normal is supplied to one input terminal similar to the playback differential amplifier (23), while the period t _a, and supplies the output of the peak hold circuit (21) to the other input terminal of the differential amplifier (23), this The comparison error signal (tracking error signal) from the differential amplifier (23) at the time is supplied to the sampling hold circuit (24) by the sampling pulse generation circuit (44).
Sampling is performed by a sampling pulse SP ₂ as shown in FIG.
6) Lead to the side.

In this case, the window signal generation circuit (34) receives a setting designation signal from the mode setting circuit (32).
6 and the window signal S _W3 and S _W4 are generated as shown in Figure D and E, extract only this like the rise of the signal S _W3 and the signal S _22, which has entered during the S _W4 of the OR circuit (35 ) so as to obtain a signal S ₂₃ at the output side of the (Figure 6 K).

At this time, the selector (37) uses the setting circuit (39)
Set the delay circuit (36) to the delay time tb select signal S delayed by time tb from the signal S ₂₃ at the output side
₂₄ (FIG. 6L), which is generated by a pulse generation circuit (43)
To obtain a pulse Pi as shown in FIG. 6P.

Also, at the time of triple speed playback, even if the adjacent tracks (5A) and (5B) have different azimuth angles,
Since the rotating heads (1A) and (1B) scan alternately at the track pitch, the head does not scan tracks having different azimuths as in the case of the double speed. Therefore, in this example controls so that the rotary head scanning locus as indicated by a chain line T _T two points in Figure 3 depicts.

Now, for example, the head (1B) is shown by a two-dot chain line T _{T in} FIG.
If the head (1B) scans over a range of the scanning width W including the track (5B ₃ ) as shown by, the head (1B) scans over the track (5A ₃ ) (5A ₂ ) on both sides of the track (5B ₃ ). , a pilot signal P _A7 tracks (5B ₃₎ in the region a _T1 as shown in FIG. 3, the pilot signal P _B2 of the pilot signal P _B7 and track of the track of the two neighboring (5A ₃₎ (5A ₂₎ Play the, in the area a _T2 reproduces the pilot signal P _B6 pilot signal P _B11 and track of the track of the two neighboring _{(5A 3) (5A 2)} , and a pilot signal P _A11 track 5B _3). At this time, the reproduction output of the head (1B) from the switch circuit (19) is the passing center frequency.
fed to a narrowband bandpass filter (20) of f ₀ ,
As the output S _F as shown in FIG. 7 J only the pilot signal is extracted, which is the peak-hold circuit (21)
Supplied to

The output S _R of the switch circuit (19) is supplied to the band-pass filter (29) in the same manner as described above, and the erasing signal S _E (typically E _A7 , E _A9 , E _A11 ) is taken out. The signal S _E is the signal S ₂₂ as shown in FIG. 7 L is supplied to the waveform shaping circuit (30), is then supplied to the rise detecting circuit (31), a thisゝ, its rising is detected gate circuit (33 ₁₎ is supplied to (33 _6).

During triple-speed playback, the window signal generation circuit (34) outputs window signals _SW2 and _SW as shown in FIGS. 7D and 7G according to a setting command signal from the mode setting circuit (32).
_W5 is generated and supplied as a gate signal to the gate circuits (33 ₂ ) and (33 ₅ ), so that the outputs of these gate circuits are provided during the respective periods of the window signals _SW2 and _SW5 , respectively. only the rise of the entered signal S ₂₂ is substantially removed, the output side of the resulting gate circuit ((33 ₂₎ and (oR circuit at the output side of the 33 ₅₎ (35), in FIG. 7 M as shown, the narrow width of the signal S ₂₃ that matches the rising edge of the signal S ₂₂ is obtained.

The signal S ₂₃ is supplied to the delay circuit (36). However, in this case the normal reproduction similar signal S ₂₃ need not be delayed because it coincides with the vicinity of the center of the pilot signal to be sampled, thus the time selector (37)
7 does not set the delay time for the delay circuit (36), and the delay circuit (36), as shown in FIG.
Generating a signal S ₂₄ that matches the _23.

The signal S ₂₄ is supplied to a pulse generating circuit (43), wherein as shown in FIG. 7 O on the basis of the signal S _24, a pair of pulses Pi corresponding to each pilot signal to be detected
Is formed and supplied to the sampling pulse generation circuit (44) and the peak hold circuit (21). Then, from the sampling pulse generating circuit (44), and sampling pulses SP ₁ and SP ₂ shown in FIG. 7 P and Q based on the pair of pulse Pi is generated, each sampling hold circuit (22) and ( 24).

Therefore, while the track (5B ₃ ) is being scanned by the head (1B), as is clear from FIG. 7, the first pulse P _i1 of the pulse Pi is transferred by the arrow (4T) (FIG. 3). The crosstalk of the pilot signal _PB9 of the adjacent track (5A ₃ ) on the opposite side to the direction is set to the peak hold state in the peak hold circuit (21), and the output of the peak hold circuit (21) at this time is the sampling hold circuit ( is supplied to the 22), is sampled by the sampling pulse SP ₁ generated at the falling edge of the first pulse P _i1 in thisゝproceeds normal playback and the same differential amplifier as a phase of the tracking signal of one of the (23) It is supplied to the input end.

The second pulse P _i2 pulse Pi becomes a state of peak hold at the peak-hold circuit (21) cross-talk pilot signal P _B4 of the adjacent track in the tape transport direction (5A _2), the peak-hold in this case The output of the circuit (21) is supplied to the other input terminal of the differential amplifier (23) as a delayed phase tracking signal. Thus, the differential amplifier (23) compares the tracking signals respectively corresponding to the crosstalk of the pilot signals P _B9 and P _B4. Then, the comparison error signal from the differential amplifier (23) is supplied to the sampling and holding circuit (24), where the second pulse
It is sampled by the sampling pulse SP ₂ generated at the falling edge of P _i2.

Therefore, the difference between the two inputs to the differential amplifier (23) is obtained as a tracking control signal from the sampling and holding circuit (24), and this is sent to the output terminal (26) via the contact a of the switch circuit (25). more is not shown is supplied to the capstan motor control transfer amount of the tape, the level difference between the two inputs to the differential amplifier (23) is zero, that is, the pilot signal P _B9 and P in the central region a _T3 head (1B) using _B4 is controlled so as to draw a scanning locus as shown by a two-dot chain line T _T in Figure 3.

Also, it performed similarly with the other tracks, for example track after three tracks from (5B ₃₎ tracks (5
A ₄₎ when the head (1A) is scanned as two-dot chain line T _T of FIG. 3, as shown in the right portion of FIG. 7 J, the pilot signal P _B8 tracks (5A _4), P _B10 , P _B12 and the pilot signals of the adjacent tracks (5B ₅ ) and (5B ₄ )
Since the crosstalk of P _A13 , P _A15 , P _A17 and P _A8 , P _A10 , P _A12 is obtained, the adjacent tracks (5B ₅ ) among these are obtained.
And the crosstalk of the pilot signals P _A15 and P _A10 described in the central part (area A _T3 ) of (5B ₄ ) is sequentially peak-held by the peak hold circuit (21), and is sampled from the sampling pulse generation circuit (44). sampling the crosstalk of the pilot signals P _A15 by the sampling pulse SP ₁ supplied to the hold circuit (22) to obtain a tracking signal, the pilot signal P _A10 and supplies it to the next stage of the differential amplifier (23) The output from the peak hold circuit (21) corresponding to the crosstalk is supplied, and the tracking signals corresponding to the crosstalk of the pilot signals _PA15 and _PA10 are compared, and the comparison error signal is sampled and held. by sampling at the sampling pulse SP ₂ supplied to (24), tracking for the head (1A) It is possible to obtain a control signal.

In the above-mentioned triple speed reproduction, the crosstalk of the pilot signal recorded in the center area of the track being scanned is used. However, as shown in FIGS. The crosstalk of the pilot signal recorded at the end of the track may be used.

For example, the pilot signal P _B2 appearing respectively last and first at the beginning and the end region of the track of the time period t in during the scan _B
First pulse P of the pulse Pi as shown in FIG. 7 R in and a peak hold circuit crosstalk P _B11 (21)
peak hold at _i1 and second pulse P _i2 , while period t
_{In A} , the crosstalk of the pilot signals P _A8 and P _A17 appearing second in the beginning and end areas of the track being scanned is converted by the peak hold circuit (21) into the first pulse Pi as shown in FIG. so as to peak-hold in the pulse P _i1 and the second pulse P _i2.

The period t in _B, the output of the peak hold circuit (21) (corresponding to the pilot signal P _B2), a sampling pulse generating circuit (4 in sample and hold circuit (22)
4) sampling pulse SP ₁ as shown in FIG. 7S
In order to make the polarity the same as the polarity of the tracking error signal during normal reproduction, the signal is supplied to the other input terminal of the differential amplifier (23).
The output of the peak hold circuit (21) corresponding to P _B11 is supplied to one input terminal of the differential amplifier (23), and the comparison error signal (tracking error signal) from the differential amplifier (23) at this time is in the sampling and hold circuit (24), sampled by the sampling pulse SP ₂ shown in FIG. 7 T from the sampling pulse generating circuit (44),
This is derived to the output terminal (26) as a tracking control signal. Further, the same operation for the pilot signal P _A8 and P _A17 even in the period t _A.

In this case, the window signal generating circuit (34) receives a setting command signal from the mode setting circuit (32),
Figure 7 C, E and F, by generating a window signal SW _1, SW ₃ and SW _4, SW _6, as shown in H, only the rising edge of the signal S _22, which has entered during the this such window signal extraction, so as to obtain a signal S ₂₃ at the output side of the OR circuit (35) (FIG. 7 M).

At this time, the selector (37) uses the setting circuit (38)
Set the delay circuit (36) selected by the delay time ta the signal S delayed by the time ta from the signal S ₂₃ at the output side
₂₄ (FIG. 7N), which is used as a pulse generation circuit (43)
To obtain a pulse Pi as shown in FIG. 7R.

Also, since in the above description are to be recorded by a preselected frequency f ₁ of the erasing signal E to a relatively large value of azimuth loss, from the head the relationship between the azimuth of the track being scanned and its azimuth ignored If the azimuth is different, that is, if the track is shifted from the track being scanned and enters an adjacent track, the crosstalk component of the erasing signal E is reduced accordingly.

Therefore, in this case, when the track deviation amount of the head is within the predetermined range, the normal operation of detecting the tracking error output corresponding to the track deviation amount and performing the tracking control as described above is performed, and the track deviation amount is set to the predetermined value. When the value exceeds the range, the control amount is fixed to a certain potential Vcc, thereby forcibly controlling the tracking of the head.
At this time, the reference value to be compared includes the reproduction output of the erasing signal E (inverse azimuth) of the adjacent track when the head scans the track of the same azimuth, and the reproduction of the head by scanning the reverse azimuth track. When the head scans the track of the same azimuth, the minimum value is determined so as to be larger than the reproduction output of the higher level among the reproduction outputs of the erasing signal E (same azimuth) of the adjacent track. The maximum value is determined so as to be smaller than the reproduction output of the erasing signal E for that track, and the reference value is set anywhere in the range between the minimum value and the maximum value.

Further, in order to set this reference value without considering the influence of jitter or the like, the head (1B) in FIG. 3 is used to set the track (5B ₂ ). when scanning at just tracking the maximum value is smaller than the reproduction output of the erasing signal E _A2 of the same azimuth and the minimum value of the adjacent track (5A ₂₎ or (5A ₁₎ of the signal E _B2 or erasing of the reverse azimuth The adjacent track (5B ₃ ) or (5B ₂ ) when scanning the reverse azimuth track (5A ₂ ) or (5A ₁ ) by just tracking with the head (1B) shifted by one track and larger than the playback output of E _B1 Of the erasing signal E _A7 or E _A2 (both have the same azimuth) or the reproduction output of the erasing signal E _A2 or E _A1 (both have the same azimuth) of the adjacent track (5B ₂ ) or (5B ₁ ) Between the maximum and minimum values A reference value may be set.

However, for example, when there is an influence of jitter or the like, the recording time of the erasing signal E is at least as short as the pilot signal P as in this example.
Must be shorter than the recording time of Equivalent), the erasing signals E of both tracks adjacent to the track being scanned partially overlap, and the start end of the erasing signal E cannot be detected, so that a self-clock cannot be formed and a malfunction may occur in the tracking control. There is.

For example, when beginning of the erasing signal E _A2 and the terminal end of the erasing signal E _A7 under the influence of the jitter or the like is the relationship to overlap, the head (1B) is displaced by one track with the reverse azimuth tracks (5A ₂₎ those obtained by adding the reproduction output of the erasing signal E _A7 and E _A2 is the azimuth when the scanning is to be detected by just tracking. Therefore, even if it is determined to be larger than the reproduction output of E _A7 or E _A2 which is one of the conditions of the minimum value of the reference value as described above, a malfunction may be caused. In this case, the minimum value is at least as described above. must be greater than the sum of the reproduction output of the erasing signal E _A7 and E _A2, it only results in a range for setting the reference value in the comparator circuit (51) is narrowed.

Therefore, in this case, as described above, the method of recording the erasing signal E is such that the beginning is located near the center of the pilot signal P of the adjacent track and at least the end is located near the end of the pilot signal P. This is done so that the recording time of the erasing signal E is at least shorter than the recording time of the pilot signal P, so that the above-mentioned overlapping of the erasing signals E is avoided. Therefore, in FIG. 1, it is not necessary to set a reference value in consideration of the overlap between the overlapping erasing signals E, and the minimum value can be set wider, so that even if there is an influence of jitter or the like, , The setting range of the reference value can be widened.

In this connection, in this case, the minimum value of the reference value is different from the reproduction output of the erasing signal E (inverse azimuth) of the adjacent track when the head is scanning the track of the same azimuth, and the head is shifted by one track. When the azimuth track is scanned, the reproduction output of the erasing signal E (same azimuth) of the adjacent track is determined to be larger than the reproduction output of the higher level, and the maximum value is determined as described above. Good.

In addition, time The effect of the jitter in the inside should be sufficiently absorbed mechanically.

Therefore, if the crosstalk output of the detected erasing signal E exceeds this reference value, the signal
S ₂₃ is generated, the sampling pulse S based on this
Even if P ₁ and SP ₂ are formed, if it is less than the reference value, the head is no longer scanning the reverse track and the signal S ₂₃ is not generated, so that the sampling pulses SP ₁ and SP ₂ are not formed.

Therefore, in FIG. 1, the erasing signal E starts at the reference value.
If the crosstalk output is below this value, the head is no longer considered to have significantly deviated from the track, and the head is forcibly shifted to the correct position.

This operation is performed by the circuits after the comparison circuit (51) shown in FIG. Next, the operation of this circuit will be described with reference to FIG.

Now, the filter (2) is connected to one input side of the comparison circuit (51).
When the eighth signal S _E, as shown in Figure B from 9) is supplied, the signal S _E is a reference value from a reference power supplied to the other input of the comparator circuit (51) (52) Compared and the signal S _E
There larger than the reference value, the output of the comparator circuit (51) is supplied as a latch pulse to the flip-flop circuit are generated signal S ₂₅ shown in FIG. 8 C (53). On the other hand, falling detection circuit (5 prior to the occurrence of the signal S ₂₅
4), the fall of the switching signal S ₁ ′ (FIG. 8D) is detected, a signal S ₂₆ as shown in FIG. 8E is generated at the output side, and the flip-flop circuit (53) is turned on in FIG. It is reset as shown in H. The input terminal D of the flip-flop circuit (53) is supplied with a switching signal ▼ as shown in FIG. 8F inverted by the inverter (55).
₂₅ a signal S ₂₈ of the high level (H) occurs as shown in FIG. 8 H at its output when the (latch pulse) is supplied, and supplies to the next-stage flip-flop circuit (57).

Further, it is detected the rise of switching signal S ₁ 'by the rising detection circuit (56), the signal S ₂₇ as shown in FIG. 8 G is outputted to the output side, the flip-flop circuit (57)
Clock terminal. This time the high-level signal S ₂₉ as the output side of the flip-flop circuit (57) shown in FIG. 8 I is generated by and supplied as switching control signal to the switch circuit (25). Switch circuit (25), so when a childゝsignal S ₂₉ is high is adapted to be connected to the contact a side, to have an output terminal (26),
A tracking control signal is derived from the sampling and holding circuit (24).

On the other hand, if the signal _SE is equal to or less than the reference value, the comparison circuit (51)
Since the output side is not the signal S ₂₅ is generated, the flip-flop circuit (53) is or was reset signal S ₂₆ aゝ,
The output signal S ₂₈ is maintained at a low level (L) as indicated by the dashed line in FIG. 8 H. In this state at a high level as shown by a broken line in the output signal S ₂₉ is also 8 Figure I of the flip-flop circuit (57).

When the switching signal S ₁ 'rise detection circuit (56) from the signal S ₂₇ (FIG. 8 G) is supplied, the output signal S ₂₉ of the flip-flop circuit (57) in broken lines in FIG. 8 I changes from high level to low level as shown, the low level of the signal S ₂₉ is supplied to the switch circuit (25), the switch circuit (25) is switched to contact b side. As a result, the output terminals (2
At 6), a signal having a constant potential Vcc is derived from the terminal (58), and this signal is supplied to a capstan servo system (not shown) to perform tracking control.

For example, when the constant potential Vcc is positive, the tape is advanced earlier through the capstan servo system, so the head substantially moves to the next track corresponding to its own azimuth and performs a normal tracking operation, When the potential Vcc is 0, the tape feed is slowed down, so that the head is substantially pulled back to the track currently being scanned, thereby starting a normal tracking operation.

In this manner, in this apparatus, the signal E for elimination of the pilot signal is set to a signal having a relatively large azimuth loss, and this signal is also used as a signal for locating the pilot signal. The structure can be simplified and the performance can be improved.

In addition, in this apparatus, at the time of reproduction, a pilot signal is detected with reference to a starting point of the reproduction output of the erasing signal E recorded on the track substantially as a reference, and a sampling pulse is generated by itself. Since the clock is generated substantially from the track pattern, there is no adverse effect when the pulse PG such as an offset is used as a reference.

Further, when the crosstalk output of the erasing signal E having a frequency at which azimuth loss is effective is equal to or less than the reference value, the control amount is forcibly fixed to a constant potential to perform head tracking control. High tracking control is possible.

Further, the tracking position is detected by generating the sampling pulse as described above for each scanning period of each head. That is, each head generates a self-clock as a sampling pulse substantially every time on the track pattern.
Since the tracking position of each track is detected, the influence of jitter is eliminated.

Further, in each reproduction mode, the detection position of the pilot signal is determined by substantially using the edge of the erasing signal E,
Alternatively, most of the circuit configuration can be shared because the delay time from this edge may be switched.

Further, since the recording is performed such that the beginning of the erasing signal E for detecting the position of the pilot signal is located near the center of the pilot signal of the adjacent track, the beginning of the erasing signal E is bothersome. There is no need for a circuit or the like that delays to be located near the center,
As a result, the circuit configuration is simplified. Since the recording time of the erasing signal E is set to be at least shorter than the recording time of the pilot signal P, the erasing signal E of the adjacent track is held at a predetermined interval, so that the recording is effected by the influence of jitter or the like. The erased signal E thus obtained does not substantially overlap between adjacent tracks, so that the setting range of the reference value in the comparison circuit (51) can be given a margin.

In the case of the circuit of FIG. 1, to obtain a synchronizing signal or the synchronizing signal S ₂₂ for the position out signal for detecting the position of the pilot signals forming the sampling pulses, the head (1A), (1B) The output reproduced by the amplifier is passed through the amplifier (18A) and (18B) to the band pass filter (29)
Extracting the erasing signal S _E through, and so as to form a synchronizing signal S ₂₂ as compared with a constant reference value is supplied to the waveform shaping circuit comprising the signal S _E from the comparator or the like (30) The amplifier (18
A), when there is no variation in such tape and head so that the output is subjected to be the signal S _E is influenced obtained at the output side of the band-pass filter (29) varies, for example, shown in FIG. 9 in (18B) is also such signal S _E in Figure 9 a is obtained, the amplifier (18A) by variations such as tape or head, even if the signal S _E output correspondingly when reduced to 1/2 of (18B) 9 As shown in FIG. Therefore, the waveform shaping circuit (3
Setting of the reference value for obtaining a synchronizing signal S ₂₂ at 0) is very difficult, the amplifier (18A), or occurs accidentally synchronizing signal S ₂₂ when the fluctuation exceeds a certain width of the output of the (18B) ,
Or, on the contrary, there arises such a problem that it does not occur at all.

SUMMARY OF THE INVENTION In view of the foregoing, an object of the present invention is to provide a synchronous signal detection circuit that can reliably detect a synchronous signal without being affected by fluctuations in the output of a reproduction amplifier due to variations in a tape, a head, and the like. It is.

SUMMARY OF THE INVENTION In the present invention, a digital signal is time-compressed and one of a pair of inclined tracks of a tape-shaped recording medium (2) recorded by a pair of magnetic heads (1A) and (1B) mounted on a rotating drum. An erasing signal and a pilot signal corresponding to one magnetic head (1A) of the pair of magnetic heads (1A) (1B)
A PCM signal is recorded, and an erasing signal, a pilot signal, and a PCM signal corresponding to the other magnetic head (1B) of the pair of magnetic heads (1A) (1B) are recorded on the other of the inclined tracks. Integrating the playback output of the rotary head in a synchronization signal detection circuit used in a digital signal recording / playback apparatus for playing back a plurality of pairs of tracks recorded without forming a guard band by the magnetic heads (1A) and (1B) Integrating means (60), a comparing means (61) for comparing the output of the integrating means (60) with a reference value, and a band-pass filter (29) for extracting an erasure signal from the output of the comparing means (61). Signal processing means comprising a comparator (30), wherein the output side of the signal processing means obtains a synchronizing signal for forming a sampling pulse for detecting the position of a pilot signal. Sync A signal detection circuit,
Even if the output of the reproduction amplifier fluctuates due to variations in the tape, the head, and the like, a stable synchronization signal can be obtained.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 10 to 14.

FIG. 10 shows a circuit configuration of the present embodiment. In FIG. 10, parts corresponding to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In this embodiment, an equalizer (60) having an integrating function and a zero-cross comparator (61) are provided between the switch circuit (19) and the band-pass filter (29). Other configurations are first
It is the same as the figure. Here, the case where a single comparator is used as the waveform shaping circuit (30) is shown.

Now, the amplifier (18A) and (18B) switch circuit (1
The signal supplied to 9) is integrated by the equalizer (60). That is, in general, a magnetic recording system has a differential performance, and thus the reproduced signal SR is differentiated to form a differential waveform. In the conventional configuration shown in FIG. 1, the reproduction signal SR is directly supplied to the band-pass filter (29), and is output as an analog signal from the output of the band-pass filter (29).
In this example, the signal is integrated by the equalizer (60) once and is restored to the original signal at the time of recording, and is digitally processed. For example, when the reproduction signal S _R supplied to the equalizer (60) is traced on the track (5B ₂ ) in FIG. 3 with a head width W larger than the track width, the reproduction signal SR becomes an erase signal E ₀ to be traced when on-track. On the other hand, the erase signal _EB6 from the adjacent track (5A ₂ ) is superimposed as the adjacent leak signal SL as shown in FIG. 16A. Since the reproduction signal SR on which the leakage signal SL is superimposed is subjected to band limitation by the integration circuit of the equalizer (60), the reproduction signal SR having a differentiated waveform has trapezoidal rising and falling portions as shown in FIG. 16B. It becomes an oblique line with an angle, and the position of the pulse width Δt ₁ of the H level with the adjacent leakage signal SL is shifted to the right side compared to the pulse width Δt ₀ of the reproduction signal SR without the adjacent leakage signal SL, and the next L level Shifts to the left, the H level shifts to the right, continues to the pulse width Δt _2, and after the pulse width Δt ₂ , the waveform has a normal pulse width Δt ₀ with a duty of 50%. The signal integrated in this way is supplied to a comparator (61) where it is compared with a reference value SH (zero potential), binarized as shown in FIG. 16C, and converted into a signal of a constant level. You.

This means that modulation in the phase direction (FM modulation) has been applied at the frequency of the leakage signal SL. In other words, the leakage signal SL from the adjacent track is different from the pulse width Δt _{0 of the} signal to be traced originally by the pulse width Δt ₁ of the portion SL where the leakage signal exists.
And Δt ₂ , the suppression effect is obtained by this FM modulation, and by binarization, a signal to be originally detected by adding a high frequency of a carrier component (for example,
In contrast to E _A6 ), the level difference between the leakage signal component SL and the leakage signal component SL increases through the band-pass filter (29), and the ratio of the erasure signal E _A6 and the leakage signal E _B6 component that should be detected is relatively reduced. Then, from the band-pass filter (29), for example, the third
When the truck (5B ₂ ) shown in the figure is on-track,
As shown in FIG. 7, the adjacent leak signal SL, that is, _EB6 is output at a small level modulated by FM, and the erase signal _{EA6 of the} track to be detected is discriminated by a large output of full swing, and the comparator at the next stage is output. The erase signal _EA6 to be supplied to the waveform shaping circuit (30) having the above configuration and to be originally detected is discriminated. Therefore,
For example, a signal as shown schematically in FIG. 11A above the equalizer (60) (actually, when a differential waveform is supplied to the SR, the comparator (61) outputs the signal shown in FIG. 11B at its output side. When the equalizer (60) generates a digital signal of a certain level, while the equalizer (60) supplies a small signal of a slightly lower level as shown in the lower part of FIG. 11A, the comparator (61) also outputs the digital signal at the output thereof. 11 A digital signal of a constant level is generated as shown in Fig. B. That is, a digital signal of a constant level is always generated regardless of the level of an input signal by passing through a comparator (61). the output side of the bandpass filter output of 61) is passed (29) as shown in FIG. 11 C, always a constant level of the erasing signal S _E (E ₀₎ is obtained. the signal S _E is is supplied to the waveform shaping circuit (30), is compared with the reference value signal S ₂₂ sand That is, a synchronization signal is obtained.

Thus, in the present embodiment, the amplifier (18
If the output of (A) and (18B) becomes, for example, 1/2, the equalizer (6
The output of the equalizer (60) is also halved, but by supplying the output of the equalizer (60) to the comparator (61), a digital signal of a constant level is always obtained on the output side, and the band through which the signal is passed. The output of the pass filter (29) is also constant, so that it is easy to set the reference potential in the waveform shaping circuit (30).

In the above description, the digital signal of a constant level obtained at the output side of the comparator (61) is substantially analog-processed by a band-pass filter (29) and a waveform shaping circuit (30) to detect a synchronization signal. In this case, an example in which this is digitally processed and detected will be described below with reference to FIGS. 12 to 14.

The erasing signal recorded on the tape (2) by the pilot signal erasing oscillator (6A) of this example is supplied from the terminal (42) of FIG. 10 through the channel clock (CL) shown in FIG.
It is made as shown in FIG. 12B with a period eight times that of K). Therefore, if the digital signal obtained at the output side of the comparator (61) is extracted with this channel clock, ideally 8T
(The maximum inversion interval of the synchronization signal) should be detected.

However, there is no correlation between the waveform at the time of reproduction and the phase of the channel clock. At such a frequency, it is difficult to synchronize with a PLL. Further, since the waveform is affected by distortion of the waveform during magnetic recording, the length may vary by ± 1T. Therefore, as shown in FIG. 12C, if the length of the synchronization signal obtained after the reproduction-time comparator (61) changes by ± 1T with respect to a certain point, in the worst case, FIG. The waveform becomes as shown.

Therefore, in such a worst waveform example, in order to detect a synchronization signal, the maximum inversion interval of PCM data recorded in one track is 4T, and the pilot signal is 18T, so that these are mistaken for other signals. All that is required is logic that can perform signal processing that does not detect. Therefore, this worst waveform example cannot be detected, but as shown in the lower part of FIG. 12D, 6T is detected, no subsequent 2T is detected, and the next 6T is detected continuously. It can be seen that detection should be performed. (Note that the x mark shown in the lower part of FIG. 12D indicates Don't Care in which nothing is detected.) In this case, signals such as other pilot signals which are not synchronization signals can be obtained as follows. Is not erroneously detected. That is, as described above, the pilot signal has a maximum inversion period of 18
Since there are 3 consecutive 6T synchronization signals because there are consecutive T, 6T is used to distinguish pilot signals from synchronization signals.
If at least three continuations are detected, it can be determined as a synchronization signal. However, even if two consecutive 6T (A and B blocks) and the last 6T (not all C blocks are detected, it is sufficient that the first signal has a polarity opposite to that of the first A block. What is necessary is to detect at 6T + 6T + 1T = 13T.

A block diagram of a circuit for performing such signal processing is shown in FIG.
Figure 13 shows the logic part (digital signal processing circuit)
Is shown in FIG.

In FIG. 13, (62) is a D-type flip-flop circuit, (63) is a shift register, and (64) is a digital signal processing circuit. A digital signal from a comparator (61) (FIG. 10) supplied to an input terminal D of a flip-flop circuit (62) is applied to a clock terminal CK (42).
(Fig. 10) is input by the clock from the output terminal Q
Are sequentially taken into the shift register (63). Shift register (63) as well as the above clock
The digital signal processing circuit (64) performs logical processing on the content captured by the shift register (63) as described above.
1) (Fig. 10).

The digital signal processing circuit (64) has a logic configuration as shown in FIG. 14, for example. That is, the output terminal A, B, and divided into three C blocks of the above shift register (63), for example, the A block Q ₁ to Q _6, B block Q ₁₁
And Q ₁₆ , the C block being Q _{21 to} Q _26, and an AND circuit (65) to which the signal of the A block shown in the lower part of FIG. 12D is directly supplied
And an AND circuit (67) and an AND circuit (6) in which the signals of the B block are inverted and supplied by the inverters (66a to 66f).
5) AND circuit (68) to which each output of (67) and the signal of C block (69) are supplied, and AND circuit to which the signal of A block is inverted and supplied by inverters (69a)-(69f) and (70), an aND circuit (71) where the signal of the B block is directly supplied, an aND circuit supplied with inverted signals Q ₂₁ to Q ₂₆ of the C block by an inverter (75a) ~ (75f) (7
4), an AND circuit (72) to which the outputs of the AND circuits (70) and (71) and a signal of the C block (74) are supplied, and an output of the AND circuits (68) and (72) to be supplied OR circuit (73).

AND circuit (65) (67) (69) and (70) (71)
The A, B, and C block data of FIGS. 15A and 15B of 6T are supplied to each of (74), and the outputs of the AND circuits (68) and (72) are supplied to the OR circuit (73). = 18T, the most accurate synchronization signal can be obtained. However, as described above, the minimum circuit configuration for preventing erroneous detection can detect the synchronization signal at 13T of 6T + 66T + 1T.

In summary, the maximum inversion interval of the synchronization signal is nT (n
Is a positive integer, n = 8 in the above example.
The signal constrained by the shift register (63) is (2n + 1) T; (b) (nk) T (n> K1, K = 2 in the above example) is detected, and is continuous ( nk)
The sign of T is reversed; (c) the two bits after (nk) T are Don't Care.

In this way, the synchronization signal can be detected by digital processing.

As described above, in the present embodiment, the signal reproduced by the head and supplied through the reproduction amplifier is temporarily integrated by the equalizer (60), and the integrated signal is detected by the comparator (61) for zero-cross detection to obtain a fixed digital signal. forming a signal, since in order to detect the signal S ₂₂ that synchronizing signal is compared with a reference value in the waveform shaping circuit a digital signal through a band-pass filter (29) (61), the variation of such a tape or a head The amplifier (18A) which is a reproduction amplifier by
Even if the output of (18B) fluctuates, the synchronization signal can be detected without being affected at all.

Further, a fixed digital signal obtained by zero-cross detection can be digitally processed to detect a synchronization signal.
In this digital processing, a digital signal of at least 2n + 1 bits is constrained, and if the (nk) bits are the same, it is detected as a synchronizing signal, and at least (nk) bits are the same, and the next k bits Is not detected, and the next (n
-K) detecting that bits are the same.

Although not shown in FIG. 10, the PCM data reproduction system generally includes an equalizer, a zero-cross comparator, a demodulator, a decoder, and a D / A converter on the output side of the switch circuit (19). Yes, therefore, the equalizer and the zero-cross comparator used in the PCM data reproduction system are shared without providing the equalizer (60) and the zero-cross comparator (61) exclusively for obtaining the synchronization signal as described above. You may do so.

As described above, according to the present invention, the output of the rotary head is integrated, the integrated output is compared with a reference value to obtain a digital signal of a certain level, and the digital signal is processed by analog processing or digital processing. Since the synchronization signal is detected, even if the output of the reproduction amplifier fluctuates due to variations in the tape, the head, etc., the synchronization signal can be always reliably detected in a stable state without any influence. .

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram according to the prior art of the present invention, FIG. 2 is a diagram showing an example of a rotary head device used in FIG. 1,
FIG. 3 is a diagram showing an outline of a recording track pattern, FIG. 4 is a signal waveform diagram for explaining a recording operation in FIG. 1, and FIG. 5 is a diagram for explaining a normal reproducing operation in FIG. FIG. 6 is a signal waveform diagram, and FIG.
FIG. 7 is a signal waveform diagram for explaining the double speed reproducing operation, FIG. 7 is a signal waveform diagram for explaining the triple speed reproducing operation in FIG. 1, and FIGS. 8 and 9 are diagrams of the reproducing operation in FIG. FIG. 10 is a circuit diagram showing an embodiment of the present invention, FIG. 11 and FIG. 12 are signal waveform diagrams for explaining a main part of the present invention, FIG. FIG. 14 is a block diagram for explaining an example of a main part of the present invention. FIG. 14 is a digital signal processing circuit of FIG.
Connection diagram showing a specific example of FIG. 15, FIG. 15 is a waveform explanatory diagram of FIG. 14,
FIG. 16 is an explanatory diagram of the pulse width, and FIG. 17 is an explanatory diagram of the output of the band-pass filter. (1A) (1B) is a rotating magnetic head, (2) is a magnetic tape,
(6) is a pilot signal oscillator, (6A) and (6B) are erasing signal oscillators (7), (7A) and (7B) are recording waveform generating circuits, and (16) and (17A) to (17E). , (36) are delay circuits, (8A), (8B) are edge detection circuits, (20), (29)
Is a bandpass filter, (21) is a peak hold circuit,
(22) and (24) are sampling and holding circuits, (23) is a differential amplifier, (25) is a switch circuit, (30) is a waveform shaping circuit, (31) and (56) are rising detection circuits, and (32) mode setting circuit (33 ₁₎ to (33 ₆₎ is a gate circuit, (34)
Is a window signal generation circuit, (37) is a delay time setting selector, (38) and (39) are delay time setting circuits, (43) is a pulse generation circuit, (60) is an equalizer, and (61) is a zero cross comparator. , (62) are D-type flip-flop circuits, (63) is a shift register, and (64) is a digital signal processing circuit.

Claims (3)

(57) [Claims] A digital signal is time-compressed and one of a pair of magnetic heads is provided on one of a pair of inclined tracks of a tape-shaped recording medium recorded by a pair of magnetic heads mounted on a rotary drum. An erasing signal, a pilot signal, and a PCM signal corresponding to the other magnetic head are recorded, and the erasing signal, the pilot signal, and the PCM signal corresponding to the other magnetic head of the pair of magnetic heads are recorded on the other of the inclined tracks.
A synchronous signal detection circuit used in a digital signal recording / reproducing apparatus for reproducing a plurality of pairs of tracks recorded without forming a guard band by the pair of magnetic heads. Integrating means for integrating the output, comparing means for comparing the output of the integrating means with a reference value, signal processing means comprising a band-pass filter and a comparator for extracting an erasure signal from the output of the comparing means, A synchronous signal detecting circuit for obtaining a synchronous signal for forming a sampling pulse for detecting a position of a pilot signal at an output side of the signal processing means. 2. A signal processing means comprising: a flip-flop circuit;
2. The synchronous signal detecting circuit according to claim 1, comprising a shift register and a digital signal processing circuit. 3. The synchronization signal detection circuit according to claim 1, wherein a zero cross comparator is used as the comparison means.