JPH0778498A - 半導体メモリ装置およびその検査方法 - Google Patents

半導体メモリ装置およびその検査方法

Info

Publication number
JPH0778498A
JPH0778498A JP6220906A JP22090694A JPH0778498A JP H0778498 A JPH0778498 A JP H0778498A JP 6220906 A JP6220906 A JP 6220906A JP 22090694 A JP22090694 A JP 22090694A JP H0778498 A JPH0778498 A JP H0778498A
Authority
JP
Japan
Prior art keywords
bar
clock signal
signal
address
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP6220906A
Other languages
English (en)
Japanese (ja)
Inventor
Norbert Wirth
ウイルト ノルベルト
Willibald Meyer
マイヤー ウイリバルト
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Publication of JPH0778498A publication Critical patent/JPH0778498A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
JP6220906A 1993-08-26 1994-08-22 半導体メモリ装置およびその検査方法 Withdrawn JPH0778498A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AT93113670.9 1993-08-26
EP93113670A EP0640986A1 (de) 1993-08-26 1993-08-26 Halbleiterspeicheranordnung und Verfahren zum Testen dieser Halbleiterspeicheranordnung

Publications (1)

Publication Number Publication Date
JPH0778498A true JPH0778498A (ja) 1995-03-20

Family

ID=8213213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6220906A Withdrawn JPH0778498A (ja) 1993-08-26 1994-08-22 半導体メモリ装置およびその検査方法

Country Status (4)

Country Link
EP (1) EP0640986A1 (OSRAM)
JP (1) JPH0778498A (OSRAM)
KR (1) KR950006878A (OSRAM)
TW (1) TW265443B (OSRAM)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6421789B1 (en) 1999-01-19 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device capable of reducing test cost and method of testing the same
US6489819B1 (en) 1998-10-27 2002-12-03 Mitsubishi Denki Kabushiki Kaisha Clock synchronous semiconductor memory device allowing testing by low speed tester

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5757705A (en) * 1997-01-22 1998-05-26 Micron Technology, Inc. SDRAM clocking test mode
WO1998036417A1 (en) * 1997-02-13 1998-08-20 United Memories Inc. Clock doubler and minimum duty cycle generator for sdrams
JP3645791B2 (ja) * 2000-05-29 2005-05-11 エルピーダメモリ株式会社 同期型半導体記憶装置
TWI662555B (zh) * 2018-06-08 2019-06-11 華邦電子股份有限公司 用於可測試性設計的資料讀取裝置及資料讀取方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2839547B2 (ja) * 1989-05-02 1998-12-16 株式会社東芝 半導体集積回路装置
US5181191A (en) * 1991-11-27 1993-01-19 Hughes Aircraft Company Built-in test circuitry providing simple and accurate AC test of digital microcircuits with low bandwidth test equipment and probe stations

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6489819B1 (en) 1998-10-27 2002-12-03 Mitsubishi Denki Kabushiki Kaisha Clock synchronous semiconductor memory device allowing testing by low speed tester
US6421789B1 (en) 1999-01-19 2002-07-16 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device capable of reducing test cost and method of testing the same
US6546503B2 (en) 1999-01-19 2003-04-08 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device capable of reducing test cost and method of testing the same

Also Published As

Publication number Publication date
KR950006878A (ko) 1995-03-21
TW265443B (OSRAM) 1995-12-11
EP0640986A1 (de) 1995-03-01

Similar Documents

Publication Publication Date Title
US6671787B2 (en) Semiconductor memory device and method of controlling the same
US4667330A (en) Semiconductor memory device
DE19807298C2 (de) Synchrone Halbleiterspeichereinrichtung
US4586167A (en) Semiconductor memory device
US4707811A (en) Semiconductor memory device having extended period for outputting data
EP0262867A2 (en) Integrated circuit with memory self-test
EP0429673A1 (en) Test pattern generator
US4661930A (en) High speed testing of integrated circuit
US6246619B1 (en) Self-refresh test time reduction scheme
US5726950A (en) Synchronous semiconductor memory device performing input/output of data in a cycle shorter than an external clock signal cycle
US6654299B2 (en) Semiconductor device
US4908796A (en) Registered outputs for a memory device
JPH0778498A (ja) 半導体メモリ装置およびその検査方法
JPH11297097A (ja) 半導体記憶装置
EP0220577B1 (en) Memory array
US6288957B1 (en) Semiconductor memory device having test mode and method for testing semiconductor therewith
JP2529680B2 (ja) 半導体メモリ装置
JPH04212776A (ja) 半導体記憶装置のテスト回路
US20090303806A1 (en) Synchronous semiconductor memory device
JPH117798A (ja) メモリを具備する集積回路のストレステスト方法及びメモリ用のストレステスタを具備する集積回路
US20030128613A1 (en) Semiconductor memory device capable of measuring a period of an internally produced periodic signal
US5579271A (en) Automatic test circuit for a semiconductor memory device capable of generating internal ras and cas signals, and row and column address signals
US4757523A (en) High speed testing of integrated circuit
KR100524925B1 (ko) 테스트 시간을 줄일 수 있는 병렬 비트 테스트를 구현하는 반도체 메모리 장치 및 이를 이용한 병렬 비트 테스트 방법
JPH08161883A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
A300 Application deemed to be withdrawn because no request for examination was validly filed

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20011106