JPH0777695A - Liquid crystal display device and its production - Google Patents

Abstract

PURPOSE:To effectively suppress the deformation of a low-resistance metallic layer having a compressive stress by a production process temp. by forming a laminated structure consisting of the low-resistance metallic layer and a high melting point metallic layer having a tensile stress as address wiring electrodes. CONSTITUTION:An insulating film 21 is formed for preventing the contamination from a glass substrate 11 and protecting the glass substrate 11. The low- resistance metallic layer 22 and the first high melting point metallic layer 23 are continuously formed at a film thickness of 50nm thereon. The film forming pressure of the first high melting metallic layer 23 is regulated within a range of 0.5 to 0.8Pa to provide the layer with the tensile stress. The laminated films are etched to work and form address wiring electrode patterns and auxiliary capacitance wiring electrode patterns to prescribed shapes. The second high melting point metallic layer 24 is then formed at a film thickness of 300nm. The low-resistance metallic layer 22-the first high melting point metallic layer 23 - the second high melting point metallic layer 24 forming the address wiring electrodes are commonly used as gate electrodes of thin-film transistors as switching elements.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device and its manufacturing method, and more particularly to its electrode structure.

[0002]

2. Description of the Related Art A liquid crystal display device for displaying characters such as characters and figures has a large number of address wiring electrodes arranged at a predetermined pitch and a predetermined pitch so as to be substantially orthogonal to the address wiring electrodes. A large number of data wiring electrodes, an array substrate having a minimum section surrounded by the address wiring electrodes and the data wiring electrodes as a pixel electrode, and a counter substrate arranged facing the array substrate at a predetermined interval, A matrix type is used which is composed of a liquid crystal composition arranged in a gap between the array substrate and the counter substrate.

An active matrix type liquid crystal display device in which a driving switching element is arranged corresponding to each pixel is also widely used. Non-linear resistance elements (MIMs) and thin film transistors (TFTs) are typical examples of such switching elements. Among them, thin film transistors have excellent high-speed response and are suitable for full-color display.

The structure of the array substrate of such an active matrix type liquid crystal display device is described, for example, in IEICE Technical Report No. 92.
Vol. 110, p. 19. FIG. 4 shows a schematic sectional structure of a switching element portion including a thin film transistor of such an array substrate, and FIG. 5 shows a schematic sectional structure of an address wiring electrode.

In FIGS. 4 and 5, on the insulating substrate 1 made of glass, the gate electrode 2 also serving as the address wiring electrode, the gate insulating films 3a and 3b, the semiconductor layer 4, the insulating protective film 5, the contact layer 6, and the pixel. An electrode 7, a source electrode 8, a drain electrode 9 and a protective film 10 are sequentially formed. In the address wiring electrode portion, first, the Al layer 2a is formed by the sputtering method on the insulating substrate 1 made of glass, and is patterned into a predetermined shape by the photolithography method. Next, an alloy layer 2b of Mo and Ta is similarly formed and patterned so as to completely cover the pattern of Al to form an address wiring electrode and an auxiliary capacitance wiring electrode.

An array substrate including such a thin film transistor and each wiring electrode and having 900 address lines and a diagonal display area of 13.8 inches has an active matrix type liquid crystal display with a pixel aperture ratio of about 30%. The device is said to have been obtained.

[0007]

In such an active matrix type liquid crystal display device, a larger screen and higher definition are being developed. However, as the screen becomes larger, the address wiring length naturally becomes longer. Further, as the number of pixels increases with the increase in definition, the area of one pixel tends to decrease, but the line width of the address wiring also tends to decrease due to the need to secure a pixel aperture ratio above a certain level. Become.

That is, with the increase in screen size and definition,
The length of the address wiring is longer and the line width has to be narrowed. Since the resistance of the electrode is proportional to the length and inversely proportional to the cross-sectional area, the address wiring electrode has a higher resistance. The increase in the resistance of the address wiring electrode distorts the waveform of the address signal, resulting in signal propagation delay. This appears as non-uniformity of the image, leading to deterioration in image quality. In order to deal with this problem, as shown in FIG. 5, the address wiring electrode and the auxiliary capacitance wiring electrode may have a laminated structure of Al and a refractory metal to reduce wiring electrode resistance and signal propagation delay. Proposed.

However, from the manufacturing process of the active matrix type liquid crystal display device having the thin film transistor as the switching element, the gate insulating film must be formed after the formation of the address wiring electrode. This gate insulating film usually needs to be formed at a substrate temperature of 350 ° C. or higher. By this heating step, Al forming the address wiring electrode is deformed. That is, an Al hillock phenomenon occurs in which a part rises in the thickness direction. For this reason, the adhesion to the underlying layer is reduced, resulting in peeling of the film in the subsequent step and reduction of the interlayer insulating property of the insulating film, resulting in a significant decrease in the yield of the array substrate.

The present invention has been made in view of the above problems and has an address wiring electrode structure which has a resistance value equivalent to that of a conventional one and is not deformed even after a thermal process, thereby forming an array substrate. An object of the present invention is to provide a liquid crystal display device that prevents a decrease in yield.

[0011]

SUMMARY OF THE INVENTION According to the present invention, a large number of address wiring electrodes are formed regularly on an insulating substrate with predetermined pitches, and a predetermined number of address wiring electrodes are formed so as to be substantially orthogonal to the address wiring electrodes. A pixel including a large number of data wiring electrodes that are regularly arranged in a pitch, an auxiliary capacitance wiring electrode that is provided independently of the address wiring electrode, and a minimum section surrounded by the address wiring electrode and the data wiring electrode. An array substrate including at least an electrode and a switching element arranged for each pixel, a counter substrate facing the array substrate at a predetermined interval, and a gap between the array substrate and the counter substrate. In the liquid crystal display device including at least the above-described liquid crystal composition, the address wiring electrode has at least a low resistance metal layer having a compressive stress and a high resistance metal layer having a tensile stress. A liquid crystal display device comprising a laminated structure of a point metal layer, laminated to form a film of the address wiring electrodes is a step of forming a low-resistance metal layer having a compressive stress,
And a step of forming a refractory metal layer having a tensile stress having a film forming pressure of 0.5 to 0.8 Pa and a film thickness of 30 to 100 nm.

[0012]

The above-mentioned deformation of Al is caused by the fact that Al has a low melting point so that Al easily moves, degassing from the film formed for the purpose of preventing and protecting the underlying glass substrate from contamination, and gas existing in Al. And the magnitude of thermal stress of the laminated film in contact with Al.

For example, as shown in FIG. 6, the stress of Al as a low resistance metal layer against heat exhibits complicated characteristics with a boundary near 200 ° C. That is, there is a relaxation point of compressive stress in the temperature range of 100 ° C to 200 ° C, and it has a characteristic property of exhibiting hysteresis as the temperature rises and falls.
Therefore, when the refractory metal layer is laminated on the low resistance metal layer having such a compressive stress, the thermal stress characteristic of the refractory metal layer becomes a problem.

Here, since most refractory metal layers formed by the most general-purpose sputtering method have compressive stress, they promote the stress relaxation mechanism of the low resistance metal layer, and It also promotes transformation. This becomes more remarkable in the case of a low melting point metal layer such as Al as the low resistance metal layer.

However, the thermal stress characteristics of this refractory metal layer change depending on the film forming conditions. For example, under film forming conditions of film forming pressure of 0.5 to 0.8 Pa and film thickness of 30 to 100 nm, thermal stress characteristics as shown in FIG. 7 are exhibited. That is, as is apparent from FIG. 7, the tensile stress is maintained up to the manufacturing process temperature of 500 ° C. Therefore, by laminating the refractory metal layer having tensile stress on the low resistance metal layer having compressive stress, the compressive stress of the low resistance metal layer is not relaxed, and the deformation of the low resistance metal layer due to the manufacturing process temperature does not occur. It will be effectively suppressed.

However, the film forming conditions are a film forming pressure of 0.5 to 0.8 Pa,
When the film thickness deviates from the range of 30 to 100 nm, the refractory metal layer becomes
Compressive stress is exhibited within the manufacturing process temperature up to 500 ° C., which promotes the stress relaxation mechanism of the low resistance metal layer and also promotes the deformation of the low resistance metal layer.

Further, another refractory metal layer is formed on these laminated layers, and the side edge portions are formed in a tapered shape, so that the step due to the thickness of the address wiring electrode is reduced and the interlayer insulating property is improved. The decrease can be prevented.

[0018]

Embodiments of the present invention will be described below with reference to FIGS.
Will be described in detail. 1 shows a schematic sectional structure of a switching element portion including a thin film transistor of an array substrate, FIG. 2 shows a schematic sectional structure of an address wiring electrode, and FIG. 3 shows an equivalent circuit structure of an array substrate.

1 to 3, the transparent glass substrate 11
A large number of address wiring electrodes arranged at a predetermined pitch on top
12 and a large number of data wiring electrodes 13 arrayed at a predetermined pitch so as to be substantially orthogonal to the address wiring electrodes 12 are arranged in a matrix, and the auxiliary capacitance wiring electrodes 14 are arranged on the address wiring electrodes 12 substantially. It is formed in parallel. Then, the pixel electrode 16 is formed in the minimum section surrounded by the address wiring electrode 12 and the data wiring electrode 13.

Further, a thin film transistor 15 as a switching element is formed near each intersection of both wiring electrodes. The drain electrode 17 of the thin film transistor 15 is connected to the data wiring electrode 13, and the gate electrode is the address wiring electrode.
Simultaneously formed with 12. Also, thin film transistor
The source electrode of 15 is connected to the display electrode 16 of each pixel, the liquid crystal capacitance 17, and the auxiliary capacitance 18 formed of the auxiliary capacitance wiring electrode 14 and the pixel electrode 16.

Next, the structure of the thin film transistor portion of the array substrate and the address wiring electrodes as described above will be described in the order of manufacturing steps. First, for the purpose of preventing contamination from the glass substrate 11 and protecting the glass substrate 11, an insulating film 21 is formed to a thickness of 300 nm by a sputtering method or a CVD method. On this, by sputtering, Al as the low resistance metal layer 22 is 200 nm,
As the first refractory metal layer 23, Mo is continuously deposited to a thickness of 50 nm. At this time, the film forming pressure of the first refractory metal layer 23
It is important that the first refractory metal layer 23 has a tensile stress within the range of 0.5 to 0.8 Pa. Further, the Al film of the low resistance metal layer 22 is an Al alloy, for example, Cu 1 atom%, Si 0.5
An Al alloy film containing atomic% is also possible, and the Mo film of the first refractory metal layer 23 can be Ti or Ta.

This laminated film is etched by a photolithography method using a mixed acid of phosphoric acid, nitric acid and acetic acid to form an address wiring electrode pattern and an auxiliary capacitance wiring electrode pattern into a predetermined shape. At this time, the side edges of the Al film as the low-resistance metal layer 22 and the Mo film as the first high-melting-point metal layer 23 are etched in a tapered shape due to the difference in etching rate.

Next, an alloy layer of Mo and Ta is formed as the second refractory metal layer 24 to a thickness of 300 nm by the sputtering method. Then, it is etched by photolithography using chemical dry etching (CDE) of a mixed gas of CF ₄ and O ₂ , and its side edge is processed and formed so as to have a tapered shape of 30 degrees or less. The etching conditions at this time are
For example, the O ₂ flow rate is 320 SCCM, the CF ₄ flow rate is 160 SCCM, and the etching pressure is 30 Pa.

Through the above process, the address wiring electrode pattern and the auxiliary capacitance wiring electrode pattern are completed.
The low resistance metal layer 22 forming the address wiring electrode-first
The high-melting-point metal layer 23-the second high-melting-point metal layer 24 also serves as the gate electrode of the thin film transistor 15 as a switching element.

Subsequently, in order to form the thin film transistor 15, plasma chemical vapor deposition (CV
D) method, SiOx, SiN as the gate insulating films 25 and 26
x, amorphous silicon (a-S
i), four layers of SiNx as the insulating protection film 28 which also serves as an etching stopper layer are continuously formed. Then, after patterning SiNx as the upper insulating protection film 28 into a predetermined shape and performing pretreatment, the contact layer of the source / drain electrodes is formed.
N + a-Si as 29 is formed by the plasma CVD method. It should be noted that thermal CV is used instead of SiOx as the gate insulating film 26.
It may be used SiO ₂ by D method.

Next, the a-Si film as the semiconductor layer 27 is patterned into a predetermined shape to form a transparent pixel electrode serving as a display electrode.
Indium Tin Oxide (ITO) as 30
Is formed and patterned into a predetermined shape. This electrode is also used as a part of one electrode of the auxiliary capacitance.
Then, the opening of the address wiring pad portion is processed and formed using an HF-based etching solution.

Subsequently, three layers of Mo, Al, and Mo are laminated and formed by a sputtering method, and this is patterned into a predetermined shape as a data wiring, a source electrode 31 and a drain electrode 32. After this, reactive ion etching (RI
By the method E), the n + a-Si film on the back channel is removed. Next, Si that becomes the protective film 33 as passivation is formed.
A film of Nx is formed and patterned into a predetermined shape.

Finally, an alignment film made of polyimide is applied to the entire surface (not shown), and a rubbing alignment treatment of rubbing in one direction with a cotton cloth or the like is performed to complete an array substrate including thin film transistors. Next, a counter electrode made of ITO is formed in a predetermined shape on another glass substrate, and an alignment film made of polyimide is applied to the entire surface,
The counter substrate is completed by performing a rubbing orientation process.

Both of these substrates are arranged facing each other at a predetermined interval so that the rubbing orientation directions are orthogonal to each other, and are bonded and fixed in the peripheral portion of the substrate, leaving a part of the injection port. Then, the nematic liquid crystal composition is injected through the injection port, and finally the injection port is sealed. Furthermore, polarizing plates are arranged outside the both substrates along the respective rubbing alignment directions.
A twisted TN type liquid crystal display device is completed.

As a result of driving this liquid crystal display device under normal driving conditions to display an image, it was confirmed that no image defect due to layer peeling of the address wiring electrode or deterioration of interlayer insulating property occurred. Incidentally, the address wiring electrode had a length of the wiring electrode of 20 cm, an average electrode width of 10 μm, and an address wiring resistance of about 9 KΩ, which was a resistance value equivalent to the conventional value.

[0031]

As described above, according to the present invention, by forming a laminated structure of a low resistance metal layer having a compressive stress and a high melting point metal layer having a tensile stress as an address wiring electrode, a low resistance metal layer can be formed. The relaxation of the compressive stress does not occur, and the deformation of the low resistance metal layer due to the manufacturing process temperature can be effectively suppressed. Further, the address wiring resistance is maintained at the same level as the conventional one, and the occurrence of layer defects in the low resistance metal layer due to the subsequent heat treatment step is effectively suppressed, and the deterioration of the interlayer insulation due to the step of the address wiring electrode is prevented. be able to.

[Brief description of drawings]

FIG. 1 is a schematic sectional configuration showing a switching element portion including a thin film transistor of an array substrate according to an embodiment of the present invention.

FIG. 2 is a cross-sectional configuration diagram showing an address wiring electrode portion of an embodiment of the present invention.

FIG. 3 is an equivalent circuit configuration diagram showing an array substrate according to an embodiment of the present invention.

FIG. 4 is a schematic sectional configuration showing a switching element portion including a thin film transistor of a conventional array substrate.

FIG. 5 is a cross-sectional configuration diagram showing an address wiring electrode portion of a conventional example.

FIG. 6 is a characteristic diagram showing thermal stress due to temperature of a low resistance metal layer.

FIG. 7 is a characteristic diagram showing thermal stress depending on the temperature of the refractory metal layer.

[Explanation of symbols]

 11 ... Glass substrate 12 ... Address wiring electrode 13 ... Data wiring electrode 14 ... Auxiliary capacitance wiring 15 ... Thin film transistor 16 ... Display pixel electrode 21 ... Insulating film 22 ... Low resistance metal layer 23 ... First refractory metal layer 24 ... Second Refractory metal layer

Claims (2)

[Claims] 1. A large number of address wiring electrodes which are regularly arrayed and formed on an insulating substrate with predetermined pitches, and regularly arrayed and formed with predetermined pitches so as to be substantially orthogonal to the address wiring electrodes. A large number of data wiring electrodes, an auxiliary capacitance wiring electrode provided independently of the address wiring electrode, a pixel electrode formed of a minimum section surrounded by the address wiring electrode and the data wiring electrode, and arranged for each pixel. An array substrate including at least the switching element, a counter substrate arranged to face the array substrate at a predetermined distance, and a liquid crystal composition arranged in a gap between the array substrate and the counter substrate. In the provided liquid crystal display device, the address wiring electrode has a laminated structure of at least a low resistance metal layer having a compressive stress and a high melting point metal layer having a tensile stress. A liquid crystal display device characterized by the following. 2. The method of manufacturing a liquid crystal display device according to claim 1, wherein the laminated film formation of the address wiring electrodes comprises a step of forming a low resistance metal layer having a compressive stress, and a film forming pressure of 0.5.
A process for forming a refractory metal layer having a tensile stress of about 0.8 Pa and a film thickness of 30 to 100 nm, and a method for manufacturing a liquid crystal display device.