JPH0777242B2 - Container for semiconductor element - Google Patents
Container for semiconductor elementInfo
- Publication number
- JPH0777242B2 JPH0777242B2 JP61150790A JP15079086A JPH0777242B2 JP H0777242 B2 JPH0777242 B2 JP H0777242B2 JP 61150790 A JP61150790 A JP 61150790A JP 15079086 A JP15079086 A JP 15079086A JP H0777242 B2 JPH0777242 B2 JP H0777242B2
- Authority
- JP
- Japan
- Prior art keywords
- wall member
- container
- protrusion
- container base
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子用容器に関する。TECHNICAL FIELD The present invention relates to a container for semiconductor devices.
一般に半導体素子用容器は高周波化が進むにつれ容器を
構成する容器基体の小型化が進むが、同時に機密性ある
いは組立作業性についての問題が生じる。Generally, as the frequency of semiconductor device containers increases, the size of the container substrate that constitutes the container decreases, but at the same time, problems with respect to airtightness and assembling workability arise.
従来の半導体素子用容器について第２図を参照して説明
する。第２図は特に機密性を重視した容器として例え
ば、パワーFETの場合についての一例を示す縦断面図で
ある。第２図において、熱伝導のよい導電性の容器基体
91上に固着された絶縁性の壁部材92及び93を積層構造と
しこの壁部材92の上面には入出力電極の外部導出用金属
化層98をもち、入出力側それぞれで入出力線材４により
外部に電極が引き出される。容器基体91は凸形状をな
し、中央部の突部上面に半導体素子12を素子固着金属化
層で固着する。半導体素子12の電極は電極配線用線９に
より近傍する壁部材92の上面にある電極導出用金属化層
98に接続されて入出力線材４により引き出される。また
キャップ封止部６は壁部材93の上面に設けた封止用金属
化層とキャップ90の周辺部に設けた封止用金属化層とで
封止金属、例えば金スズをはさんで熔着することにより
容器基体91とキャップ90との気密封止を実現する。壁部
材92・93の形状の単純化、並びに電極配線用線９の配線
作業の容易性から壁部材92の上面は容器基体91の突部上
面とほぼ同一平面をなす。従って、絶縁性の壁部材93上
の封止面は凸形で導電性の容器基体の上面である素子搭
載面より高い位置にある構造になっている。A conventional semiconductor device container will be described with reference to FIG. FIG. 2 is a vertical cross-sectional view showing an example of the case of a power FET, for example, as a container in which the airtightness is particularly emphasized. In FIG. 2, an electrically conductive container substrate having good heat conduction
Insulating wall members 92 and 93 fixed on 91 are laminated to have a metallization layer 98 for external lead-out of input / output electrodes on the upper surface of the wall member 92. The electrode is pulled out to the outside. The container base 91 has a convex shape, and the semiconductor element 12 is fixed to the upper surface of the protrusion in the central portion by an element fixing metallization layer. The electrode of the semiconductor element 12 is a metallization layer for electrode lead-out on the upper surface of the wall member 92 that is closer to the electrode wiring line 9.
It is connected to 98 and pulled out by the input / output wire 4. The cap sealing portion 6 is composed of a sealing metallization layer provided on the upper surface of the wall member 93 and a sealing metallization layer provided on the peripheral portion of the cap 90, and a sealing metal, for example, gold tin, is sandwiched therebetween. By attaching them, the container base 91 and the cap 90 are hermetically sealed. The upper surface of the wall member 92 is substantially flush with the upper surface of the projecting portion of the container base 91 because of the simplification of the shapes of the wall members 92 and 93 and the ease of wiring work of the electrode wiring line 9. Therefore, the sealing surface on the insulative wall member 93 has a convex shape and is located higher than the element mounting surface, which is the upper surface of the conductive container base.
上述した従来の半導体素子用容器は絶縁性の壁部材を積
層してキャップ封止部を容器基体および入出力線材から
離して配することにより、例えば金スズのような封止金
属を使用して気密性に優れた容器が実現できるが、封止
面が半導体素子の搭載面より高いためキャップ封止直前
の、半導体素子配設時に使用するアームあるいはコレッ
トが、また電極配線用線の接続工程時のウェッジあるい
はキャピラリーがこの壁部材に接触するため組立工程の
作業を悪くし、自動化への大きな障害になるという問題
点があった。本発明の目的は上記問題点を解決し気密性
においても又組立作業性においてもすぐれた構造をもつ
半導体素子用容器を提供することにある。The conventional semiconductor device container described above uses a sealing metal such as gold tin by stacking insulating wall members and disposing the cap sealing portion away from the container base and the input / output wire rod. Although a container with excellent airtightness can be realized, since the sealing surface is higher than the mounting surface of the semiconductor element, the arm or collet used when arranging the semiconductor element immediately before the cap is sealed, and during the process of connecting the electrode wiring line Since the wedges or capillaries contact the wall member, the work of the assembling process is deteriorated and there is a problem that it becomes a great obstacle to automation. An object of the present invention is to solve the above problems and to provide a container for a semiconductor device having a structure excellent in airtightness and assembling workability.
本発明の特徴は、中央部に突部を有し該突部上面に半導
体素子を固着する導電性の容器基体と、高部分と低部分
とからＬ字形をなし、該高部分が前記突部に対峙しかつ
該高部分の上面の高さが前記突部上面の高さとほぼ等し
く、底面が前記容器基体に固着している絶縁性の第１の
壁部材と、前記第１の壁部材の前記高部分の前記上面か
ら前記低部分の上面にかけて形成された電極導出用金属
化層と、前記第１の壁部材の前記低部分の前記上面に固
着され、かつ前記第１の壁部材の前記高部分の前記上面
および前記容器基体の前記突部上面とほぼ等しい高さの
上面を有する絶縁性の第２の壁部材と、前記第１の壁部
材の前記低部分の前記上面に形成された前記電極導出用
金属化層であって前記第２の壁部材の外側の箇所に接続
された入出力線材と、前記第２の壁部材の前記上面で封
止用金属化層により気密封止するキャップとを有した半
導体素子用容器にある。A feature of the present invention is that an electrically conductive container base having a protrusion in the center and fixing a semiconductor element to the upper surface of the protrusion, and a high portion and a low portion form an L shape, and the high portion is the protrusion. Of the insulative first wall member, the height of the upper surface of the high portion is substantially equal to the height of the upper surface of the protrusion, and the bottom surface of the first wall member is fixed to the container base. An electrode lead-out metallization layer formed from the upper surface of the high portion to the upper surface of the lower portion, and fixed to the upper surface of the lower portion of the first wall member, and the metal of the first wall member An insulating second wall member having an upper surface of substantially the same height as the upper surface of the high portion and the upper surface of the protruding portion of the container base, and the upper surface of the lower portion of the first wall member. An input / output wire rod that is the metallization layer for leading out the electrode and is connected to a portion outside the second wall member. , In the container for semiconductor element and a cap for hermetically sealing the sealing metal layer in said top surface of said second wall member.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の一実施例を示す縦断面図である。第１
図において、半導体素子用容器は容器基体１、壁部材２
・３、およびキャップ10で構成される。容器基体１はほ
ぼ中央部で上方向へ凸形をなす突部13を有する導電体で
突部13の上面には素子固着用金属層11をもって半導体素
子12のペレットを固着する。壁部材２とＬ字形をなす絶
縁性のもので、Ｌ字形の左の面になる外壁が突部13の外
側壁面に対峙し、底面が容器基体１の上面に接して固着
する。壁部材２の最上面は容器内部の突起13の最上面と
ほぼ同一平面をなして半導体素子12の電極と接続する電
極配線用線９を接着する電極導出用金属化層８が布設さ
れる。電極導出用金属化層８は壁部材２の上面で容器の
外方向端辺まで布設され入出力線材４により容器外へ引
出される。壁部材３は壁部材２の底面の上面に配設され
る絶縁体で、上面は突部13の最上面および壁部材２の最
上面とほぼ同一平面上にある。容器は容器基体１、壁部
材２・３により側面が密閉され、上面にほぼ同一平面を
なして突部13、壁部材２・３のそれぞれの最上面が見え
る。半導体素子12はペレットとして中央の突部13の最上
面に素子固着用金属化層11で固着され、次いで電極配線
用線９により壁部材２の金属化層８へ電極が導出され
る。次いで容器は側面外壁をなす壁部材３の上面並びに
キャップ10の壁部材３との接着面を封止用金属化層と
し、これらの金属化層間に例えば金スズを挟み熔着する
キャップ10の金属封止により気密封止される。FIG. 1 is a vertical sectional view showing an embodiment of the present invention. First
In the figure, a semiconductor element container is a container base 1 and a wall member 2.
・ It is composed of 3 and cap 10. The container base 1 is a conductor having an upwardly projecting protrusion 13 at a substantially central portion, and a pellet of a semiconductor element 12 is fixed to the upper surface of the protrusion 13 with an element fixing metal layer 11. The wall member 2 is L-shaped and insulative and has an outer wall serving as a left surface of the L-shape, which faces the outer wall surface of the protrusion 13, and a bottom surface of which is in contact with and fixed to the upper surface of the container base 1. The uppermost surface of the wall member 2 is substantially flush with the uppermost surface of the protrusion 13 inside the container, and an electrode lead-out metallization layer 8 for bonding an electrode wiring line 9 connected to an electrode of the semiconductor element 12 is laid. The electrode lead-out metallized layer 8 is laid on the upper surface of the wall member 2 up to the outer edge of the container and is drawn out of the container by the input / output wire 4. The wall member 3 is an insulator disposed on the upper surface of the bottom surface of the wall member 2, and the upper surface is substantially flush with the uppermost surface of the protrusion 13 and the uppermost surface of the wall member 2. The side surface of the container is hermetically sealed by the container base 1 and the wall members 2 and 3, and the upper surfaces of the protrusion 13 and the wall members 2 and 3 are substantially flush with the upper surface. The semiconductor element 12 is fixed as a pellet to the uppermost surface of the central protrusion 13 by the element fixing metallization layer 11, and then the electrode is led to the metallization layer 8 of the wall member 2 by the electrode wiring line 9. Next, in the container, the upper surface of the wall member 3 forming the outer side wall and the adhesive surface of the cap 10 to the wall member 3 are used as a metallizing layer for sealing, and metal such as gold and tin is sandwiched between these metallized layers and welded. It is hermetically sealed by sealing.
以上説明したように本発明は半導体素子の搭載面であ
る。容器基体上面と封止面である壁部材上面とをほぼ同
一の高さに形成することにより、組立の作業性がよく、
しかも側面外壁をなす壁部材の上面でキャップを封止用
金属化層により気密封止しているから、ガラス封止と比
較して気密性にもすぐれた高信頼度で量産性のある容器
が実現できる効果がある。As described above, the present invention is a mounting surface of a semiconductor element. By forming the upper surface of the container base and the upper surface of the wall member, which is the sealing surface, at substantially the same height, the workability of assembly is improved,
Moreover, since the cap is hermetically sealed by the metallizing layer for sealing on the upper surface of the wall member forming the outer side wall, a highly reliable and mass-producible container that is superior in hermeticity to glass sealing can be obtained. There is an effect that can be realized.
第１図は本発明による半導体素子用容器の一実施例を示
す縦断面図、第２図は従来の一例を示す縦断面図であ
る。 1,91……容器基体、2,3,92,93……壁部材、8,11,98……
金属化層、10,90……キャップ、12……半導体素子、13
……突部。FIG. 1 is a vertical cross-sectional view showing an embodiment of a semiconductor device container according to the present invention, and FIG. 2 is a vertical cross-sectional view showing a conventional example. 1,91 …… Container base, 2,3,92,93 …… Wall member, 8,11,98 ……
Metallized layer, 10,90 ... Cap, 12 ... Semiconductor element, 13
…… Protrusion.
Claims (1)
子を固着する導電性の容器基体と、 高部分と低部分とからＬ字形をなし、該高部分が前記突
部に対峙しかつ該高部分の上面の高さが前記突部上面の
高さとほぼ等しく、底面が前記容器基体に固着している
絶縁性の第１の壁部材と、 前記第１の壁部材の前記高部分の前記上面から前記低部
分の上面にかけて形成された電極導出用金属化層と、 前記第１の壁部材の前記低部分の前記上面に固着され、
かつ前記第１の壁部材の前記高部分の前記上面および前
記容器基体の前記突部上面とほぼ等しい高さの上面を有
する絶縁性の第２の壁部材と、 前記第１の壁部材の前記低部分の前記上面に形成された
前記電極導出用金属化層であって前記第２の壁部材の外
側の箇所に接続された入出力線材と、 前記第２の壁部材の前記上面で封止用金属化層により気
密封止するキャップとを有したことを特徴とする半導体
素子用容器。1. An electrically conductive container base having a protrusion in the center and fixing a semiconductor element to the upper surface of the protrusion, and a high portion and a low portion which form an L shape, and the high portion is formed on the protrusion. An insulative first wall member facing each other and having a height of an upper surface substantially equal to that of the upper surface of the protrusion and a bottom surface fixed to the container base; An electrode lead-out metallization layer formed from the upper surface of the high portion to the upper surface of the lower portion, and fixed to the upper surface of the lower portion of the first wall member,
And an insulative second wall member having an upper surface of substantially the same height as the upper surface of the high portion of the first wall member and the upper surface of the protruding portion of the container base, and the first wall member An input / output wire rod that is formed on the upper surface of the lower portion and is connected to an outer portion of the second wall member that is the electrode leading metallization layer, and is sealed by the upper surface of the second wall member. And a cap for hermetically sealing with a metallizing layer for semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150790A JPH0777242B2 (en) | 1986-06-26 | 1986-06-26 | Container for semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61150790A JPH0777242B2 (en) | 1986-06-26 | 1986-06-26 | Container for semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS636861A JPS636861A (en) | 1988-01-12 |
| JPH0777242B2 true JPH0777242B2 (en) | 1995-08-16 |
Family
ID=15504488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61150790A Expired - Lifetime JPH0777242B2 (en) | 1986-06-26 | 1986-06-26 | Container for semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0777242B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0273653A (en) * | 1988-09-08 | 1990-03-13 | Nec Corp | Package for semiconductor device |
| US5223741A (en) * | 1989-09-01 | 1993-06-29 | Tactical Fabs, Inc. | Package for an integrated circuit structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59121841U (en) * | 1983-02-03 | 1984-08-16 | 日本電気株式会社 | Package for IC chip |
-
1986
- 1986-06-26 JP JP61150790A patent/JPH0777242B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS636861A (en) | 1988-01-12 |
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