JPH077425A - A/d converter - Google Patents

Abstract

PURPOSE:To attain an A/D converter having almost the same circuit size as a conventional one and shorter conversion time. CONSTITUTION:This A/D converter is provided with the 1st conversion circuits 4, 8, 12 for binarizing an upper bit part in the 1st step, the 2nd conversion circuits 1 to 3 for binarizing a lower bit part by the 2nd step, the 3rd conversion circuit 100 for executing binarization corresponding to one selected data out of binary data for upper bits in the 2nd step, and an encoding circuit 240 for correcting data consisting of binary data C4, C8, C12 for upper bit parts and binary data C1 to C3 for lower bit parts in accordance with an output value Cp from the circuit 100 and encoding the corrected data and constituted so that the time (T1-T0) of the 1st step is shorter than time (almost T2-T1) required for the stabilization of the 1st conversion circuits 4, 8, 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more specifically, a so-called two-step flash type A
/ D converter improvement.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a parallel A / D converter. This is a basic one before the 2-step flash type A / D converter. Specifically, the plurality of reference voltage signals D1 to D15 are generated by the ladder resistors R0 to R15.
And the sample and hold circuit 16 samples the analog signal A in accordance with the timing signal T0 to obtain the analog signal A ', and the comparators 1 to 15 are arranged in parallel to compare the reference voltage signals D1 to D15 with the analog signal A'. Perform actions at once. Then, the latch 18 outputs the 15-bit binary data C1-15 from the comparators 1-15.
Is latched in accordance with the timing signal T1, and the encoder 19 encodes it into a 4-bit binary number and outputs it. As a result, the value of the analog signal A is converted into the digital value E.

FIG. 4 shows a waveform example of the above A / D converter. This is an example when the value of the analog signal A ′ is extremely close to the reference voltage signal D12. In this case, the reference voltage signal D10 having a value relatively distant from the value of the analog signal A ',
Comparators D11, D13, D14, etc. and the analog signal A'are binarized to make comparators 10, 11, 13, 14
Etc. are the binarized data C10, C11, C1 which are outputs.
3, C14, etc. quickly stabilize. On the other hand, in the comparator 12 that performs the binarization by comparing the reference voltage signal D12 close to the value of the analog signal A ′ and the analog signal A ′, the binarized data C12 that is an output is not stable. Therefore, it usually takes about 100 ns from the timing signal T0 to the timing signal T1.

FIG. 5 shows a circuit example of a conventional 2-step flash type A / D converter. This performs the comparison operation in two steps, a first step from timing signal T0 to timing signal T1 and a second step from timing signal T1 to timing signal T2.
In the first step, the first conversion circuit compares and converts the binarized data for the upper 2 bits of the digital value E, and in the second step, the second conversion circuit converts the digital value E. The binary data for the lower 2 bits are compared and converted. Then, these binary data are converted into a binary digital value E and output.

More specifically, the first conversion circuit is a circuit mainly composed of the comparators 4, 8 and 12. The comparators 4, 8 and 12 include a first set of three reference voltage signals D4, D8 and D12 corresponding to the upper 2 bits of the digital value E among the plurality of reference voltage signals D1 to D15, and a timing signal. Upon receiving the analog signal A ′ sampled according to T0, parallel comparison is performed, and binarized data C4, C8, and C12 are output according to the comparison result. The latch 21 latches and holds these binarized data in accordance with the timing signal T1. As a result, in the first step, binarization is performed on the 3-bit binarized data necessary for the upper 2-bit portion of the digital value.

The selection circuit includes a selection signal generation circuit 22 and a switch group provided corresponding to each connection point of the ladder resistors R0 to R15. The selection signal generation circuit 22 generates a selection signal corresponding to the binarized data from the first conversion circuit, and each switch group is opened and closed according to this selection signal. Then, four sets of reference voltage signals (D1, D2, D3), (D
5, D6, D7), (D9, D10, D11), (D1
3, D14, D15) is selected. What is selected is one set of the values immediately above the reference voltage signal input to the comparator outputting the highest "1" of the binarized data C4, C8, C12. This is the reference voltage signal D1 ', D2', D3 '. As a result, the second set of reference voltage signals D1 ′, D2 ′, D3 ′ corresponding to the lower 2 bits of the digital value E among the plurality of reference signals D1 to D15 are sent to the comparators 1, 2, 3. It

The second conversion circuit includes comparators 1, 2, and
It is a circuit mainly composed of 3. Comparators 1, 2, 3
Receives the reference voltage signals D1 ', D2', D3 'and the analog signal A', performs parallel comparison and outputs binarized data C1, C2, C3 according to the comparison result. The latch 23 latches and holds these binarized data in accordance with the timing signal T2. As a result, in the second step, binarization is performed on the 3-bit binarized data required for the remaining lower 2-bit portion of the digital value.

The encoder 24 converts the 3-bit binary data from the latch 21 into a binary number to obtain the upper 2 bits of the digital value E, and further converts the 3-bit binary data from the latch 23 into a binary number. Lower 2 of digital value E converted
Bit. Then, a 4-bit digital value E obtained by combining these is output. In this way, 4-bit A / D
In the case of performing conversion, the basic parallel comparison type requires 15 comparators, and by performing the comparison operation in two steps, the two-step flash type A / D converter requires only six comparators.

[0009]

Such a conventional two-step flash type A / D converter has a large number of comparators including a large number of transistors and a large circuit scale as compared with a complete parallel type A / D converter. Less,
There is an advantage that it is cheaper. However, parallel type A
While the / D converter completes the comparison operation in one step, the two-step flash type A / D converter
Since the comparison operation is performed in two steps, there is also a disadvantage that the conversion time is twice as long and long. Due to such a limit of performance, the applicable range is limited, which is inconvenient.
The object of the present invention is to solve the above-mentioned problems of the prior art, and to solve the problems of the conventional two-step flash type A.
An object of the present invention is to realize an A / D converter whose circuit scale is almost the same as that of the A / D converter and the conversion time is short.

[0010]

The structure of the A / D converter of the present invention for attaining this object is such that the comparison operation is performed in the order of the first and second steps to convert the value of the analog signal into a digital value. In the A / D converter for conversion, a first conversion circuit that performs binarization for the high-order bit portion of the digital value in the first step, and the remaining low-order bits of the digital value in the second step A second conversion circuit for performing binarization for the portion, and one of the binarized data for the upper bits selected in the second step according to the output of the first conversion circuit. From the third conversion circuit, and a third conversion circuit for performing binarization corresponding to the above, and data consisting of the binarized data for the upper bit part and the binarized data for the lower bit part. Corrected according to the output value of An encoding circuit for encoding and generating the digital value, wherein the time of the first step is shorter than the time required for stabilization of the first conversion circuit, and the time of the second step. Is longer than the time of the first step.

A more specific configuration is an A / D for converting the value of the analog signal into a digital value by performing a comparison operation between a plurality of reference voltage signals and the analog signal twice in the order of the first and second steps. In the converter, a parallel comparison between a first set of reference voltage signals corresponding to the high-order bit portion of the digital value of the plurality of reference voltage signals and the analog signal is performed in the first step to perform the digital comparison. A first conversion circuit for performing binarization on the binarized data necessary for the upper bit portion of the value; and a first conversion circuit corresponding to the remaining lower bit portion of the digital value from the plurality of reference voltage signals. The two sets of reference voltage signals are selected according to the output value of the first conversion circuit, and any of the values of the second set of reference voltage signals is selected from the first set of reference voltage signals. Beyond And a selection circuit for selecting the smallest single reference voltage signal and outputting these selected reference voltage signals; and the second set of reference voltage signals and the analog signals from the selection circuit. A parallel conversion in the second step to perform binarization on the binarized data needed for the remaining lower bit portion, and the single conversion circuit from the selection circuit. A third conversion circuit that performs comparison between a reference voltage signal and the analog signal in the second step to perform binarization on one piece of binarized data; and the upper bit from the first conversion circuit. Binarized data corresponding to the lower bit portion from the second conversion circuit by replacing corresponding one bit of the binarized data corresponding to the portion with the binarized data from the third conversion circuit. Is the third conversion circuit An encoding circuit for generating the digital value by encoding the data composed of these binarized data while keeping or suppressing the output value according to the first conversion step. The binarization in the circuit is shorter than the time it takes for all the bits to stabilize there and is stable for all remaining bits except the one bit which is the slowest to binarize in the first conversion circuit. And the second step ends in a time longer than the time required for the binarization in the second conversion circuit to be stable for all bits therein. Is.

[0012]

In the A / D converter of the present invention having such a configuration, in addition to the conventional two-step flash type A / D converter, only one extra binary data is added in the second step. Ask. For this reason, a third conversion circuit for performing one binarization is added, and the encoding circuit is enlarged by the amount corresponding to the binarized data. However, the increase in the circuit size to this extent is slight as compared with the circuit size of the entire A / D converter that performs binarization on a large number of binarized data. Therefore, it can be said that the circuit scale is almost the same as that of the conventional two-step flash A / D converter.

The conversion operation is performed in two steps as in the conventional case, but unlike the conventional case, the time of the first step is shorter than the time of the second step, unlike the conventional case. This reduces the overall conversion time.
It should be noted that unstable binarized data may occur in the first step due to the shortened time of the first step, but this is due to the binary value extraly obtained in the second step. There is no inconvenience because it is excluded by the digitized data.
Therefore, the A / D converter of the present invention is
Compared with the step flash type A / D converter, the circuit scale is almost the same, but the conversion time is short.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 shows an example of a 4-bit A / D converter. This is obtained by adding a comparator 100 and switches 101, 102, 103 for switching a reference voltage signal input to the conventional two-step flash type A / D converter in FIG. Further, along with this, the latch 230 is expanded to 4 bits and the encoder 240 is expanded. The same components as those of the conventional example are denoted by the same reference numerals as those of the conventional example, and the difference from the conventional example will be mainly described.

The first conversion circuit comprises comparators 4, 8,
12 as the main, and the first 2 of the digital values in the first step
3-bit binary data C required for the bit part
Binarization of 4, C8 and C12 is performed. The second conversion circuit is mainly composed of comparators 1, 2 and 3, and is for the 3-bit binarized data C1, C2 and C3 necessary for the remaining lower 2 bits of the digital value in the second step. Binarize. These are the same as conventional ones.

The selection circuit comprises a selection signal generation circuit 22 and a switch group provided corresponding to the connection points of the ladder resistors R0 to R15, and the lower 2 bits of the digital value E among the reference signals D1 to D15. A second set of reference voltage signals D1 ', D2', D3 'corresponding to the part is sent to the comparators 1, 2, 3. This point is the same as before. However, switches 101, 102, and 103 are provided for the connection points of the resistors R3 and R4, the connection points of the resistors R7 and R8, and the connection points of the resistors R11 and R12, respectively, and the first set of reference voltage signals (D4 , D8, D12) of the second set of reference voltage signals (D1 ′, D2 ′, D3 ′) that exceeds any value and is the smallest single reference voltage signal Dp. It is expanded to select and send to the comparator 100. Note that the switches 101 and 10
Since 2 and 103 can be composed of several transistors, the increase in the circuit scale due to the addition of these transistors is slight.

The third conversion circuit is a circuit mainly composed of the comparator 100. The comparator 100 receives the selected reference voltage signal Dp and the analog signal A ′,
These values are compared and one binary data Cp is output according to the comparison result. The latch 230 converts the binarized data Cp into the binarized data C according to the timing signal T2.
It is latched and held together with 1, C2 and C3. As a result, the binarization corresponding to the selected one of the binarized data C4, C8, C12 for the upper 2 bits is performed in the second step. For this reason, one extra comparator is required, and in the case of performing 4-bit A / D conversion, the number of comparators required in the basic parallel comparison type was increased from seven to seven instead of six. However, the difference from the conventional 2-step flash type is small.

The encoder 240 functions as an encoding circuit. 2 bits of 3-bit binary data from the latch 21
The basic function part of converting the binary value into the high-order 2 bits of the digital value E and converting the 3-bit binary data from the latch 230 into the binary number into the low-order 2 bits of the digital value E is the same as the conventional one. It is the same. However, the binarized data C
Among the four, C8, and C12, 1 bit corresponding to the binarized data Cp is replaced with the binarized data Cp, and the binarized data Cp and the binarized data replaced by this have the same value. Sometimes, the binary data C1, C2, C3 is directly encoded into a binary number, and when the binary data Cp and the binary data replaced by this are different values, the binary data C1, C2, C3. Is extended so that the value of "000" is suppressed and encoded into a binary number.

Here, the difference between the binarized data Cp and the binarized data replaced by the binarized data is that the analog signal is the same as described in connection with the parallel A / D converter in the conventional example. Only for a comparator that compares A'with a reference voltage signal that is very close to this value.
Therefore, even if unstable binarized data is generated in the first step due to the above-mentioned expansion for replacing the output value of the comparator, the inconvenience caused by the unstable binarized data is generated in the second step. Eliminated by Cp. Note that this expansion requires only a few gate circuits, so the increase in circuit scale is slight.

The timing signal generating circuit 200 is the same as the conventional one in that the pulse of the timing signal T2 is generated 100 ns after the pulse of the timing signal T1.
This is different from the conventional one in that the pulse of the timing signal T1 is generated 50 ns after the pulse of the timing signal T0. As a result, from the timing signal T0 to the timing signal T2
The conversion time of the A / D converter is shortened from the conventional 200 ns to 150 ns.

The operation of the A / D converter having such a configuration will be described. First, a case where the value of the analog signal A'is not close to any of the reference voltage signals D4, D8, D12 will be described. In this case, the conversion operation is basically similar to the conventional one. That is, the timing signal T0
Then, the sample and hold circuit 16 samples the analog signal A into an analog signal A ', and the comparators 4, 8 and 12 are arranged in parallel and binarized data C4, C8 and C1.
Compare and convert 2 Since the value of the analog signal A ′ is not close to any of the reference voltage signals D4, D8, D12, the accurate binary data C within 50 ns
4, C8 and C12 are obtained.

Further, the latch 2 is activated by the timing signal T1.
1 latches the binarized data C4, C8, C12
The second step is started at the end of the step of, and the comparators 1, 2, 3, and 100 perform parallel comparison and conversion on the binarized data C1, C2, C3, and Cp. The binarized data C1, C2, C3, Cp are all stable within 100 ns. Then, at the timing signal T2, the latch 230 causes the binarized data C1, C2, C
3, Cp are latched, and the binarized data C1, C2, C3
The encoder 240 uses C4, C8, and C12 as 4-bit 2
Coding into a base number, the second step ends. As a result, the value of the analog signal A is accurately converted into the digital value E.

Next, a case where the value of the analog signal A'is close to any one of the first set of reference voltage signals D4, D8 and D12 will be described. As a specific example, it is assumed that the analog signal A'has a value slightly higher than the reference voltage signal D8. In this case, the binarized data C8 and the binarized data Cp may take different values, and in connection with this, some operations different from the conventional ones are performed. At the timing signal T0, the sample and hold circuit 16 samples the analog signal A to obtain the analog signal A '.

Then, the comparators 4, 8 and 12 perform parallel comparison and conversion on the binarized data C4, C8 and C12. Since the value of the analog signal A ′ is close to the reference voltage signal D8, the value of the binarized data C4 and C12 is 5
An accurate value can be obtained within 0 ns, but the binarized data C8
Is required to be close to 100 ns, and it is difficult to obtain an accurate value within 50 ns (waveform diagram (d) in FIG. 2,
(See (e) and (f)). Therefore, the binarized data C4, C
8, C12 may be "100" as opposed to the original "110".

The latch 21 latches the binarized data C4, C8 and C12 with the timing signal T1 and outputs the binarized data C4, C8 and C12 to the selection signal generating circuit 22 and the encoder 240. The selection signal generating circuit 22 corresponds to the reference voltage between the reference voltage signal D4 and the reference voltage signal D8 in response to the binary data C4 being "1" and the binary data C8 being "0". Signal D5
A selection signal for selecting ~ D7 is generated. Then, the reference voltage signals D5, D6, D7 are turned on / off according to the selection signal so that the reference voltage signals D5 ', D2', D of the second set correspond to the lower 2 bits of the digital value E.
It is output as 3 '.

Further, the switch 1 is operated by the same selection signal.
03 becomes conductive. Therefore, the first set of reference voltage signals D
4, D8, D12 of the second set of reference voltage signals D
As a single reference voltage signal Dp which is the smallest and exceeds any of 1 ′, D2 ′ and D3 ′,
The reference voltage signal D8 is selected. Then, the comparators 1, 2, 3, 100 are arranged in parallel and binarized data C1, C
2, C3, Cp are compared and converted. As a result, the comparison / conversion between the analog signal A ′ and the reference voltage signal D8 is performed again by the comparator 100, and the resulting value “1” is obtained as the binarized data Cp within 100 ns (the waveform diagram in FIG. 2). (See (g)).

The latch 230 latches the binarized data C1, C2, C3, Cp by the timing signal T2 and sends it to the encoder 240. In the encoder 240, since the binarized data Cp and the binarized data C8 are different,
The value of the binarized data C8 is replaced with the value of the binarized data Cp, and the values of the binarized data C1, C2, C3 are suppressed to "0".
00 ". As a result, the binarized data C1, C2,
The final values of C3, C4, C8 and C12 are "00011
0 ". This is divided into 3 bits each and converted into a 2-bit binary number, and then combined to obtain a 4-bit binary number" 0100 ".

The digital value E thus obtained is an accurate value. The value of the analog signal A ′ is the reference voltage signal D4,
The same applies to the case of being close to any of D12. Therefore, the conversion time, which conventionally required 200 ns, is 15
Only 0 ns is required, and the performance of conversion speed can be improved. Although the 4-bit A / D converter has been described above as a specific example, the same operational effect can be obtained even when the number of bits such as 8 bits and 12 bits is used. It is also arbitrary whether positive logic or negative logic is assigned to the logical values of "0" and "1".

[0029]

As can be understood from the above description, in the A / D converter of the present invention, the first conversion circuit for performing the binarization for the upper bit part in the first step, and the first conversion circuit A second conversion circuit that performs binarization for the lower bit portion in step 2 and a binarization corresponding to the selected one of the binarized data for the upper bit in the second step. The third conversion circuit to be performed and the data composed of the binarized data for the upper bit portion and the binarized data for the lower bit portion are modified according to the output value from the third conversion circuit, and the data is corrected. And a coding circuit for coding, and the time of the first step is shorter than the time required for stabilization of the first conversion circuit (which is approximately equal to the time of the second step). As a result, there is an effect that it is possible to realize an A / D converter whose circuit scale is substantially the same as that of the conventional two-step flash type A / D converter and the conversion time is short.

[Brief description of drawings]

FIG. 1 is a block diagram of a circuit of an embodiment of an A / D converter having a configuration of the present invention.

FIG. 2 is a waveform diagram for explaining the operation.

FIG. 3 is a block diagram of a basic parallel type A / D converter.

FIG. 4 is a waveform diagram for explaining the operation.

FIG. 5 is a conventional two-step flash type A /
It is a block diagram of a D converter.

[Explanation of symbols]

 1 to 15 comparator 16 sample and hold circuit 17 timing signal generating circuit 18 latch 19 encoder 20 timing signal generating circuit 21 latch 22 selection signal generating circuit 23 latch 24 encoder 100 comparator 101 to 103 switch 200 timing signal generating circuit 230 latch 240 encoder

Claims (2)

[Claims] 1. An A / D converter for converting a value of an analog signal into a digital value by performing a comparing operation in the order of a first step and a second step, wherein an upper bit portion of the digital value is converted in the first step. A first conversion circuit that performs binarization for the purpose of: and a second conversion circuit that performs binarization for the remaining low-order bit portion of the digital value in the second step,
A third conversion circuit that performs binarization corresponding to one selected from the binarized data for the upper bit in the second step, according to the output of the first conversion circuit; The data consisting of the binarized data for the upper bit portion and the binarized data for the lower bit portion is converted into the third data.
An encoding circuit for correcting the output value from the converting circuit and encoding it to generate the digital value, wherein the time of the first step is the time required for stabilizing the first converting circuit. An A / D converter characterized in that the time of the second step is shorter than the time of the first step. 2. An A / D converter for converting a value of the analog signal into a digital value by performing a comparison operation of a plurality of reference voltage signals and an analog signal twice in the order of a first step and a second step. Of the reference voltage signal corresponding to the high-order bit portion of the digital value and the analog signal are parallel-compared in the first step to perform the high-order bit portion of the digital value. A first conversion circuit for performing binarization on the binarized data necessary for: a second set of references corresponding to the remaining lower bit parts of the digital value among the plurality of reference voltage signals. A voltage signal is selected according to the output value of the first conversion circuit, and further exceeds any value of the second set of reference voltage signals from the first set of reference voltage signals. The smallest A selection circuit for selecting a single reference voltage signal and outputting these selected reference voltage signals; and a parallel comparison of the second set of reference voltage signals from the selection circuit with the analog signal. A second conversion circuit for performing the binarization on the binarized data necessary for the remaining lower bit part in step 2, and the single reference voltage signal from the selection circuit and the analog A third conversion circuit for performing binarization on one piece of binarized data by performing comparison with a signal in the second step, and a binary corresponding to the high-order bit part from the first conversion circuit The corresponding 1 bit of the binarized data is replaced with the binarized data from the third conversion circuit, and the binarized data corresponding to the lower bit portion from the second conversion circuit is converted into the third transformed data. Depending on the output value from the circuit An encoding circuit which, as it is or suppresses, encodes data consisting of these binarized data to generate the digital value, and wherein the first step comprises the binarization in the first conversion circuit. Is shorter than the time required to stabilize all the bits there, and is less than the time required to stabilize all the remaining bits except the one bit that is the slowest to be binarized in the first conversion circuit. A /, characterized in that the second step ends in a longer time than the time required for the binarization in the second conversion circuit to be stable for all bits therein. D
converter.