CN112653461A

CN112653461A - First order memoryless dynamic element matching technique

Info

Publication number: CN112653461A
Application number: CN202011074702.6A
Authority: CN
Inventors: A·巴尔; R·辛格; V·特里帕蒂
Original assignee: STMicroelectronics International NV Switzerland
Current assignee: STMicroelectronics International NV Switzerland
Priority date: 2019-10-10
Filing date: 2020-10-09
Publication date: 2021-04-13

Abstract

Embodiments of the present disclosure relate to first order memoryless dynamic element matching techniques. A quantizer generates a thermometer encoded signal from an analog voltage signal. The output DWA signal is generated by controlling the operation of the crossbar switch controlled by the switch control signal, implementing a Data Weighted Average (DWA) of the thermometer-coded signal. The output DWA signal is latched to generate a latched output DWA signal that is processed in a feedback loop along with bits of the thermometer-coded input signal to generate the switch control signal. The latch-out DWA signal is performed in an input register of a digital-to-analog converter that operates to convert the latch-out DWA signal to a feedback analog voltage from which an analog voltage signal is generated. Based on the detection of the ending logical transition of the latched DWA signal, the switch control signal specifies the bit position of the beginning logical transition of the period of the output DWA signal.

Description

First order memoryless dynamic element matching technique

Cross Reference to Related Applications

This application claims priority from U.S. provisional patent application No. 62/913,252, filed on 10/2019, the disclosure of which is incorporated herein by reference.

Technical Field

The present disclosure relates to the field of data conversion processing, and in particular to a first order Dynamic Element Matching (DEM) technique and a DEM architecture for implementing the same. The DEM architecture may be used for a continuous-time sigma-delta modulator, such as for an analog-to-digital converter.

Background

High speed data converters typically employ a Data Weighted Averaging (DWA) algorithm as a solution to achieve first order Dynamic Element Matching (DEM). Fig. 1 illustrates a comparison of the operation of data converter 102 without a DWA and data converter 104 without a DWA. The data word 110 is received and processed by a converter circuit to selectively actuate unary Output Elements (OE)124, 134 of a digital-to-analog converter (DAC). In this example, each DAC includes seven unary output elements.

For data converter 102, data word 110 is decoded by thermometer decoder 120 to generate thermometer control signal 122 whose data bits selectively actuate unary output element 124. If the data word has a value of 3 (binary format <0,1,1>), thermometer decoder 120 decodes the word to generate a 7-bit thermometer control signal 122 having a value of <1,1,1,0,0,0,0>, the 7-bit thermometer control signal 122 causing the first three unary output elements 124 from the left to be actuated. Shaded boxes indicate output elements that are activated, while unshaded boxes indicate output elements that are disabled. If the next data word has a value of 1 (binary format <0,0,1>), the thermometer decoder 120 decodes the word to generate a seven-bit thermometer control signal 122 having a value <1,0,0,0,0,0,0>, the seven-bit thermometer control signal 122 causing a first one-bit output element 124 from the left to be actuated. The operation of the next data word with

values

5 and 4 is also shown.

It should be noted that the data converter 102 disproportionately actuates the plurality of unary output elements 124 of the DAC in response to the data word input 110. In other words, the unary output element on the left side of the DAC is actuated more frequently by the control signal 122 than the unary output element on the right side of the DAC. This is not a problem in an ideal scenario when all unary output elements 124 of the DAC are identical (i.e., matched). However, in practical designs, mismatches exist and appear at the output as the noise floor of the output signal increases. This can negatively impact the performance of the DAC and result in a reduced signal-to-noise ratio.

However, the use of the DWA algorithm by the data converter 104 ensures that mismatches across the unary output element 124 are high-passed and pushed out of the band of interest. This is similar to first order noise shaping. Data word 110 is processed by a Dynamic Element Matching (DEM) circuit 130 implementing a Data Weighted Averaging (DWA) algorithm to generate a control signal 132 having data bits of control signal 132 that selectively actuate an Output Element (OE) 134. If the data word has a value of 3 (binary format <0,1,1>), DEM circuitry 130 decodes the word to generate a 7-bit DWA control signal 122 having a value of <1,1,1,0,0,0,0>, the 7-bit DWA control signal 122 causing the first three unary output elements 134 from the left to be activated. Shaded boxes indicate output elements that are activated, while unshaded boxes indicate output elements that are disabled. At this time, there is no difference in the operation of the data converter 104 compared to the data converter 102. If the next data word has a value of 1 (binary format <0,0,1>), DEM circuitry 130 decodes the word to generate seven-bit DWA control signals 132 having a value of <0,0,0,1,0,0,0>, the seven-bit DWA control signals 132 causing the next sequential unary output element (i.e., only the fourth unary output element) of unary output elements 134 to be actuated. If the next data word has a value of 5 (binary format <1,0,1>), DEM circuitry 130 decodes the word to generate a 7-bit DWA control signal 132 having a value <1,1,0,0,1, 1>, the 7-bit DWA control signal 132 causing the next sequential five unary output elements (i.e., the last three unary output elements and the first two unary output elements) of unary output elements 134 to be actuated (in this case, a wrap-around from right to left is required). The operation of the next data word of value 4 is also shown, which causes the next sequential four unary output elements 134 to be actuated. It should be noted that the data converter 104 actuates all unary output elements 134 of the DAC relatively equally over time.

Despite the mismatch with respect to the unary output elements 134 of the digital-to-analog converter, the data weighted averaging algorithm still spreads actuation relatively equally across all unary output elements 134. The noise due to output element mismatch is shaped by the DWA, which advantageously averages the mismatch error in the band of interest.

Circuits for implementing high speed data converters are known in the art that use a data weighted average algorithm to achieve first order dynamic element matching. Examples of such circuits are disclosed by U.S. patent nos. 7,868,807; dayanik et al, "A5 GS/s 156MHz BW 70dB DR Continuous-Time Sigma-Delta Modulator with Time-Interleaved Reference Data-Weighted Averaging", 2017Symposium on VLI Circuits, 2017; and "High-speed Low-compatibility Implementation for Data Weighted Averaging Algorithm" by Da-Huei Lee et al, IEEE Asia-Pacific Conference on ASIC (AP-ASIC), 2002, pp 283 to 286 (all the foregoing are incorporated by reference). The problems with these solutions include: the long conversion time results in cumbersome operations, which limits throughput and performance; circuit implementation is inefficient in terms of area and power; and the use of interleaving introduces a high degree of complexity. Decoder and adder logic that performs the dynamic indexing function is required to further illustrate the complexity. Interleaving using multiple parallel paths can also adversely affect circuit performance.

Referring now to fig. 2, there is shown a block diagram of a prior art Data Weighted Averaging (DWA) circuit 200 as taught by U.S. patent No. 10,050,640 (incorporated by reference). The circuit includes a data bus 202 carrying a multi-bit input data word DT < N-1:0> having a thermometer coded format (where the data word DT < N-1:0> may be supplied, for example, from a quantizer circuit 203 clocked by a data clock signal clk (clk)). In an example, N ═ 16; however, it should be understood that the solution disclosed herein is extensible for any value of N. The data bus 202 is connected to the data inputs of the crossbar 204. The outputs of crossbar 204 are connected to a data bus 206, and data bus 206 carries a multi-bit output data word DW < N-1:0>, which is a data weighted average conversion of a thermometer-coded, multi-bit input data word DT < N-1:0 >. DWA control circuit 210 receives both multi-bit input data word DT < N-1:0> and multi-bit output data word DW < N-1:0>, and data clock signal CLK, and DWA control circuit 210 operates to generate multi-bit select signal Sel < N-1:0> that is applied to control inputs of crossbar matrix 204 through data bus 212. In response to multi-bit select signal Sel < N-1:0>, crossbar 204 operates to selectively map switch inputs to switch outputs to implement data weighted average conversion and to implement Dynamic Element Matching (DEM).

The physical configuration of crossbar 204 is well known to those skilled in the art. Crossbar 204 effectively includes a plurality of switching elements that can be controlled to selectively couple a given one of the switching inputs to a given one of the switching outputs. The complexity of the switching element circuit permits any individual one of the switch inputs to be connected to any given one of the switch outputs in response to the data value of the multi-bit select signal Sel < N-1:0 >.

The operation of crossbar 204 may be logically represented by N multiplexers 240(0) through 240(N-1), where each multiplexer 240 is an N:1 multiplexer (as shown in FIG. 3). The bit input data words DT < N-1:0> on the data bus 202 are identified as DT (N-1), … …, DT (0). The bits of the multi-bit output data word DW < N-1:0> are identified as DW (N-1), … …, DW (0). The select control input of each multiplexer 240 receives a multi-bit select signal Sel < N-1:0 >. It should be noted that the surrounding sequence order of the bits of the multi-bit input data word DT < N-1:0> at the input of each multiplexer is different. As an example, for multiplexer 240(N-1), the order of the bits of the multi-bit input data word DT < N-1:0> at the input is DT (N-1), DT (N-2), … …, DT (0). For multiplexer 240(N-2), the order of the bits of the multi-bit input data word DT < N-1:0> at the input is DT (N-2), DT (N-3), … …, DT (0), DT (N-1). For multiplexer 240(1), the order of the bits of the multi-bit input data word DT < N-1:0> at the input is DT (1), DT (0), DT (N-1), … …, DT (3), DT (2). For multiplexer 240(0), the bit order of the multi-bit input data word DT < N-1:0> at the input is DT (0), DT (N-1), DT (N-2), … …, DT (2), DT (1). Those skilled in the art will recognize that the concatenation of the bit sequences of the multi-bit input data word DT < N-1:0> is effectively barrel shifted across the N multiplexers 240(0) through 240 (N-1). This has the effect that the crossbar operates to selectively connect bits of the multi-bit input data word DT < N-1:0> to bits of the multi-bit output data word DW < N-1:0>, wherein the barrel shift position is selectable by the value of the multi-bit select signal Sel < N-1:0 >.

DWA control circuit 210 generates multi-bit select signal Sel < N-1:0> such that only one of the N bits in the select signal (e.g., a logic 1) may be asserted at a time, while all other bits are de-asserted (e.g., a logic 0). By selectively connecting the multiplexer inputs (reference numerals 0 through N-1), N multiplexers 240(0) through 240(N-1) are responsive to an asserted bit of a multi-bit select signal Sel < N-1:0>, which corresponds to an asserted bit of the multiplexer output. The single asserted bit of multi-bit select signal Sel < N-1:0> specifies a barrel shift positional relationship between the bit sequence of multi-bit input data word DT < N-1:0> and the bit sequence of multi-bit output data word DW < N-1:0 >. This may be better understood by reference to some examples.

First consider a multi-bit select signal Sel < N-1:0> of value <0,0, …,0,1>, where only Sel (0) is 1. In response to the value of the multi-bit select signal Sel < N-1:0>, multiplexer 240(0) connects DT (0) to output DW (0), multiplexer 240(1) connects DT (1) to output DW (1), multiplexer 240(N-2) connects DT (N-2) to output DW (N-2), and multiplexer 240(N-1) connects DT (N-1) to output DW (N-1).

Now consider a multi-bit select signal Sel < N-1:0> of value <0,0, …,1,0>, where only Sel (1) is 1. In response to the value of the multi-bit select signal Sel < N-1:0>, multiplexer 240(0) connects DT (N-1) to output DW (0), multiplexer 240(1) connects DT (0) to output DW (1), multiplexer 240(N-2) connects DT (N-3) to output DW (N-2), and multiplexer 240(N-1) connects DT (N-2) to output DW (N-1).

For a multi-bit select signal Sel < N-1:0> with a value <0,1, …,0,0>, where only Sel (N-2) ═ 1. In response to the value of the multi-bit select signal Sel < N-1:0>, multiplexer 240(0) connects DT (2) to output DW (0), multiplexer 240(1) connects DT (3) to output DW (1), multiplexer 240(N-2) connects DT (0) to output DW (N-2), and multiplexer 240(N-1) connects DT (1) to output DW (N-1).

Finally, if the value of the multi-bit selection signal Sel < N-1:0> is <1,0, …,0,0>, where only Sel (N-1) ═ 1. In response to this value of multi-bit select signal Sel < N-1:0>, multiplexer 240(0) connects DT (1) to output DW (0), multiplexer 240(1) connects DT (2) to output DW (1), multiplexer 240(N-2) connects DT (N-1) to output DW (N-2), and multiplexer 240(N-1) connects DT (0) to output DW (N-1).

The operation of crossbar 204 to connect the bits of multi-bit input data word DT < N-1:0> to the bits of multi-bit output data word DW < N-1:0> can be mathematically represented by:

DW(n,k)＝DT(mod(N+n-k,N))

where N, k e (0, N-1), N is the output, and k is selected such that DW (N, k)) is the switch address connecting input DT ((N + N-k) modulo N) to output DW (N).

Consider the first example given above where the multi-bit select signal Sel < N-1:0> has a value <0,0, …,0,1>, where only Sel (0) is 1 and thus k is 0. For N-0 and N-16, the output bit DW (0) will be connected to the input bit DT (0) because (16+ 0-0/16-1, the remainder is 0, and thus the modulus is 0). For N-1 and N-16, output bit DW (1) will be connected to input bit DT (1) because (16+ 1-0/16-1, remainder 1, and thus modulus is 1. The foregoing corresponds to the results noted above, where multiplexer 240(0) connects DT (0) to output DW (0), multiplexer 240(1) connects DT (1) to output DW (1), multiplexer DT (N-2) connects DT (N-2) to output DW (N-2), and multiplexer 240(N-1) connects DT (N-1) to output DW (N-1). In this configuration, consecutive bits DT (0) through DT (N-1) of a multi-bit input data word DT < N-1:0> are mapped to bits DW (0), DW (1), … …, DW (N-1), respectively, of a multi-bit output data word DW < N-1:0> via crossbar 204 with k ═ 0.

Now consider a multi-bit select signal Sel < N-1:0> of value <0,0, …,1,0>, where only Sel (1) equals 1, and thus k equals 1. For N-0 and N-16, the output bit DW (0) will be connected to the input bit DT (15) because (16+ 0-1/16-0, the remainder is 15, and thus the modulus is 15. For N-1 and N-16, output bit DW (1) will be connected to input bit DT (1) because (16+ 1-1/16-1, the remainder is 0, and thus the modulus is 0. The foregoing corresponds to the above-mentioned result, wherein multiplexer 240(0) connects DT (N-1) to output DW (0), multiplexer 240(1) connects DT (0) to output DW (1), multiplexer 240(N-2) connects DT (N-3) to output DW (N-2), and multiplexer 240(N-1) connects DT (N-2) to output DW (N-1). In this configuration, consecutive bits DT (0) through DT (N-1) of a multi-bit input data word DT < N-1:0> are mapped to bits DW (N-1), DW (0), … …, DW (N-2), respectively, of a multi-bit output data word DW < N-1:0> via crossbar 204 with k ═ 1.

For a multi-bit select signal Sel < N-1:0> with a value <0,1, …,0,0>, where only Sel (N-2) equals 1, and thus k equals 14. For N-0 and N-16, the output bit DW (0) will be connected to the input bit DT (2) because (16+ 0-14/16-0, the remainder is 2, and thus the modulus is 2). For N-1 and N-16, the output bit DW (1) will be connected to the input bit DT (3) because (16+ 1-14/16-0, the remainder 3, and thus the modulus 3). The foregoing corresponds to the results noted above, where multiplexer 240(0) connects DT (2) to output DW (0), multiplexer 240(1) connects DT (3) to output DW (1), multiplexer 240(N-2) connects DT (0) to output DW (N-2), and multiplexer 240(N-1) connects DT (1) to output DW (N-1). In this configuration, for k 14, consecutive bits DT (0) to DT (N-1) of multi-bit input data word DT < N-1:0> are mapped to bits DW (2), DW (3), … …, DW (1), respectively, of multi-bit output data word DW < N-1:0> by cross-switch matrix 204 of k 14.

Finally, if the value of the multi-bit selection signal Sel < N-1:0> is <1,0, …,0,0>, where only Sel (N-1) is 1, and thus k is 15. For N-0 and N-16, the output bit DW (0) will be connected to the input bit DT (1) because (16+ 0-15/16-0, the remainder is 1, and thus the modulus is 1). For N-1 and N-16, output bit DW (1) will be connected to input bit DT (2), since (16+ 1-15/16-0, remainder 2, and therefore modulus 2. The foregoing corresponds to the above-mentioned result, wherein multiplexer 240(0) connects DT (1) to output DW (0), multiplexer 240(1) connects DT (2) to output DW (1), multiplexer 240(N-2) connects DT (N-1) to output DW (N-2), and multiplexer 240(N-1) connects DT (0) to output DW (N-1). In this configuration, consecutive bits DT (0) to DT (N-1) of a multi-bit input data word DT < N-1:0> are mapped to bits DW (1), DW (2), … …, DW (0), respectively, of a multi-bit output data word DW < N-1:0> via a crossbar matrix 204 with k ═ 15.

Referring now to fig. 4, a circuit diagram of the DWA control circuit 210 is shown. The DWA control circuit 210 includes a clock generation circuit 300, a combinational logic circuit 302, and N flip-flops 304(0) to 304(N-1) forming an output register. In order to conform to the example provided above, in fig. 4, N ═ 16. However, it should be understood that the solution disclosed herein is extensible for any value of N. The output of each flip-flop 304 corresponds to one bit of the multi-bit select signal Sel < N-1:0 >. All flip-flops 304 operate simultaneously as output registers to load a data bit output from combinational logic circuit 302 in response to an edge of the load clock signal LD _ CLK and make the loaded data bit available at the flip-flop outputs for inclusion in the multi-bit select signal Sel < N-1:0 >. The load clock signal LD _ CLK is generated by the clock generation circuit 300 in response to the clock signal CLK and the bits of the multi-bit input data word DT < N-1:0 >.

The clock generation circuit 300 includes a clock GATE circuit (C-GATE) having a clock input configured to receive a data clock signal CLK; and an enable input EN configured to receive the enable signal 310. When the enable signal 310 is asserted, the clock gate circuit operates to pass the data clock signal CLK as the load clock signal LD _ CLK and the flip-flops 304(0) through 304(N-1) will be triggered at the appropriate clock edge to load the data bit output from the combinational logic circuit 302 in the output register. Conversely, when the enable signal 310 is deasserted, the clock gate circuit operates to hold the current logic state of the load clock signal LD _ CLK and to suspend or disable flip-flop operations that load data bits output from the combinational logic circuit 302 into the register.

The circuitry that generates the enable signal 310 includes a logical NAND gate 312, the logical NAND gate 312 having inputs connected to receive the bits of the multi-bit input data word DT < N-1:0> on the data bus 202. When all bits of the multi-bit input data word DT < N-1:0> are logic 1, the output 314 of the NAND gate 312 is logic 0 (otherwise the output 314 is logic 1). The circuit that generates the enable signal 310 also includes a logical OR gate 322, the logical OR gate 322 having inputs connected to receive the bits of the multi-bit input data word DT < N-1:0> on the data bus 202. The output 324 of OR gate 322 is logic 0 when all bits of the multi-bit input data word DT < N-1:0> are logic 0 (otherwise the output 324 is logic 1). Logic AND gate 332 logically combines the output of NAND gate 312 with the output of OR gate 322 to generate enable signal 310. The enable signal 310 has a logic 0 state (indicating that all bits of the multi-bit input data word DT < N-1:0> are detected as logic 1) only when the output of the NAND gate 312 is logic 0, OR the output of the OR gate 322 is logic 0 (indicating that all bits of the multi-bit input data word DT < N-1:0> are detected as logic 0). When the enable signal 310 has a logic 0 state, the clock GATE circuit C-GATE is disabled to hold the current value of the load clock signal LD _ CLK. Under all other conditions of the bits of the multi-bit input data word DT < N-1:0>, enable signal 310 has a logic 1 state and the clock GATE circuit C-GATE is enabled (to pass the clock signal CLK as the load clock signal LD _ CLK).

The combinational logic circuit 302 is formed of N logic AND gates 350(0) through 350(N-1), the logic AND gates 350(0) through 350(N-1) operating to generate a multi-bit input select signal Sel _ in < N-1:0>, which is applied to corresponding inputs of the N flip-flops 304(0) through 304 (N-1). A first input of each AND gate 350 is connected to a logical inverse of a corresponding bit DW (x) of a multi-bit output data word DW < N-1:0> received on data bus 206. The second input 350 of each AND gate is connected to an adjacent bit DW (x-1) of a multi-bit output data word DW < N-1:0> received on data bus 206. For example, AND gate 350(0) has a first input connected to receive the logical inverse of the corresponding bit DW (0); and a second input connected to receive an adjacent bit DW (N-1) (which may be bit DW (15) in the example where N ═ 16). The output of AND gate 350(0), which provides one bit of the multi-bit input select signal Sel _ in < N-1:0>, is connected to the input of corresponding flip-flop 304(4) for flip-flop FF 0. Likewise, AND gate 350(N-1) (which may be AND gate 350(15) in the example of N-16) has a first input connected to receive the logical inverse of the corresponding bit DW (N-1) (which may be bit DW (15) in the example of N-16); and a second input connected to receive an adjacent bit DW (N-2) (which may be bit DW (14) in the example of N-16). The output of AND gate 350(N-1), which provides the other bit of the multi-bit input select signal Sel _ in < N-1:0>, is connected to the input of the corresponding flip-flop 304(N-1) for flip-flop FF 15. Likewise, other AND gates 350 are connected to the logic inverse AND adjacent bits of the multi-bit output data word DW < N-1:0>, AND generate corresponding bits of the multi-bit input select signal Sel _ in < N-1:0 >.

The combinational logic circuit 302 operates to find the most significant bit positions in the received multi-bit output data word DW < N-1:0> having a logic 1 value. In other words, this is the bit position at which the ending logic transition (from logic 1 to logic 0) of the logic 1 bit string in the multi-bit output data word DW < N-1:0> occurs. The AND gate 350, whose second input receives the logic 1 value AND whose first input receives a logic 0 value from the next adjacent upper bit in the received multi-bit output data word DW < N-1:0>, will output a logic 1 value. All other AND gates 350 will output a logic low value because at least one of their first or second inputs receives a logic 0 input. This operation may be better understood by considering the following example, where the multi-bit output data word DW < N-1:0> has a value <0,0, …,0,1,1,1,0 >. In this example, bit DW (3) is the most significant bit with a logic 1 value (the next bit DW (4) has a logic 0 value), and this is the bit position where the ending logic transition occurs. AND gate 350(4) will have a first input that receives the logical inverse of bit DW (4) (i.e., receives a logical 1 value at the first input); and a second input that will receive an adjacent bit DW (3) having a logic 1 value. Thus, the output of AND gate 350(4) will be a logic 1 value, while all other AND gates 350 will output a logic 0 value.

As noted above, AND gate 350(0) has a first input connected to receive the logical inverse of the corresponding bit DW (0); and a second input connected to receive an adjacent bit DW (N-1). This is important because the connection enables a wrap around operation to find the most significant bit position. To appreciate this feature, consider the example where the multi-bit output data word DW < N-1:0> has a value <1,1,1, … 0,0,0 >. In this example, bit DW (N-1) is the most significant bit having a logic 1 value, and this is the bit position where the ending logic transition occurs. Due to wrap around, the next adjacent upper bit is a DW (0) bit having a logic 0 value. AND gate 350(0) will have a first input that receives the logical inverse of bit DW (0) (i.e., receives a logical 1 value at the first input); and a second input receiving an adjacent bit DW (N-1) having a logic 1 value. Thus, the output of AND gate 350(0) will be a logic 1 value, while all other AND gates 350 will output a logic 0 value.

When the edge of the load clock signal LD _ CLK is received, the N flip-flops 304(0) through 304(N-1) will load data output from a corresponding logic gate of the N logic AND gates 350(0) through 350 (N-1). The outputs of logic AND gates 350(0) through 350(N-1) form the bits of multi-bit select signal Sel < N-1:0 >. Since only one AND gate output has a logic 1 value at a time, this means that only one bit at a time in the multi-bit select signal Sel < N-1:0> has a logic 1 value. This one bit of multi-bit select signal Sel < N-1:0> having a logic 1 value specifies the location of the operation (as described above, reference k) for controlling crossbar matrix 204 to connect the bits of multi-bit input data word DT < N-1:0> to the bits of multi-bit output data word DW < N-1:0> in a particular order. Examples of this operation are discussed in detail above. In effect, the location provided by multi-bit select signal Sel < N-1:0> identifies the bit position of the next multi-bit output data word DW < N-1:0> at which the start logic transition should occur to achieve a data weighted average. This will be the position in the next data word DW where the logic 1 bit string should start.

As noted above, when the enable signal 310 is a logic 0 (i.e., deasserting this signal), the clock gate circuit operates to hold the current logic state of the load clock signal LD _ CLK and to suspend or disable flip-flop operations that load data bits output from the combinational logic circuit 302. In this mode, LD _ CLK bar register 304 is loaded with the SEL bits when all of the bits of multi-bit input data word DT < N-1:0> are either logic 1 or logic 0. This is mandatory because the AND logic of combinational logic circuit 302, which operates to generate the SEL signal, will generate all bits having a logic value for the above-described input condition of either a full logic 1 or a full logic 0 of the multi-bit input data word DT < N-1:0 >. Importantly, as discussed herein with respect to circuit operation, this action occurs in the previous cycle, thus relieving the burden of the critical timing path.

The operation of the DWA circuit 200 is driven by the data clock signal CLK. Referring now to FIG. 5, a timing diagram illustrating this operation is shown. An operation occurs with respect to the time period t of the data clock signal CLK. The DWA circuit 200 is in the current time period t_iIn receiving a multi-bit input data word DT<N-1:0>And is used in the current time period t_iMulti-bit selection signal Sel usable in (1)<N-1:0>At a time period t_iIn-out multi-bit output data word DW<N-1:0>. At the current time period t_iIn (1) a multi-bit selection signal Sel<N-1:0>According to a preceding time periodt_i-1A multi-bit output data word DW generated in<N-1:0>And (4) generating. This operation may be better understood by considering the operation of circuit 200 over multiple successive time periods.

At the beginning of the operation of the circuit 200, the current time period t₀(i.e., felt)₀) Internal multi-bit select signal Sel<N-1:0>Can be initialized to a desired value, such as a value<0,0,…,0,0,1>. In this example case, since the bit Sel (0) is logic 1, k is 0. Since there has not been a previous time period t_i-1Starting multi-bit output data word DW<N-1:0>So such initialization is required for the current time period t₀In generating a multi-bit selection signal Sel<N-1:0>. Crossbar 204 responds by having an initialized value for DT (0) connected to output DW (0), DT (1) connected to outputs DW (N-2), … …, DT (N-2) connected to output DW (N-2), and DT (N-1) connected to output DW (N-2)<0,0,…,0,0,1>Is selected from the multiple bits of the selection signal Sel<N-1:0>. For a time period t₀Of the received value is<0,0,0,…,0,1,1,1>Of a multi-bit input data word DT<N-1:0>(i.e., thermometer encoded value of data word is 3, binary<0,1,1>) The circuit 200 is in the time period t₀Has a medium output value of<0,0,0,…,0,1,1,1>Is a multi-bit output data word DW<N-1:0>(i.e., DTt₀). Multibit input data word DT<N-1:0>Is converted into a multi-bit output data word DW<N-1:0>With the bit position beginning the logical transition at bit DW (0) and the bit position ending the logical transition at bit DW (2).

Now, assume that during time period t₁Received multi-bit input data word DT<N-1:0>(i.e., DTt₁) Has a value of<0,0,…,1,1,1,1,1,1>(i.e. thermometer coded value of 6, binary, for a data word)<1,1,0>). DWA control circuit 210 from a previous time period t₀(i.e., DWt)₀) Starting for a value of<0,0,0,…,0,1,1,1>Is a multi-bit output data word DW<N-1:0>Processing is performed to identify the most significant bit (i.e., the location at which the logical transition ends) that has a logical 1 value. In this case, the most significant bit is found through AND gate 350(3)A bit out DW (2), the AND gate 350(3) having a first input receiving a logic inverse DW (3); and a second input that receives bit DW (2). Thus, during a time period t₁(i.e., Sel _ int₁) In (1), generating a multi-bit selection input signal Sel _ in<N-1:0>. Flip-flop 304 is loaded with the output of AND GATE 350 in response to the loading clock signal LD _ CLK (generated from the data clock signal CLK by clock GATE C-GATE). Only flip-flop 304(3) coupled to the output of AND gate 350(3) is set to a logic 1 value. Thus, the generated multi-bit selection signal Sel<N-1:0>At a time period t₁(i.e., felt)₁) Will be of value<0,0,…,1,0,0,0>. Therefore, since the bit Sel (3) is logic 1, k is 3. Cross-switch matrix 204 response has values by connecting DT (13) to output DW (0), DT (14) to outputs DW (1), … …, DT (11) to output DW (N-2), and DT (12) to output DW (N-2)<0,0,…,1,0,0,0>Is selected from the multiple bits of the selection signal Sel<N-1:0>. The circuit 200 is in the time period t₁(i.e., DWt)₁) Has a medium output value of<0,0,0,…,0,1,1,1,1,1,1,0,0,0>Is a multi-bit output data word DW<N-1:0>. Thus, a multi-bit input data word DT<N-1:0>Is converted into a multi-bit output data word DW<N-1:0>With the bit position beginning the logical transition being the DW (3) bit and the bit position ending the logical transition being the DW (8) bit.

Suppose that during a time period t₂To a received multi-bit input data word DT<N-1:0>Has a value of<1,1,1,…,1,1,1,1,1,1>(i.e., all bits are a logic 1 value). DWA control circuit 210 from a previous time period t₁Starting for a value of<0,0,0,…,0,1,1,1,1,1,1,0,0,0>Is a multi-bit output data word DW<N-1:0>Processing is performed to identify the most significant bit (i.e., the location at which the logical transition ends) that has a logical 1 value. In this case, the most significant bit may be bit DW (8) found by AND gate 350(9), the AND gate 350(9) having a first input receiving a logic inversion DW (9); and a second input receiving bit DW (8). Thus, during a time period t₂(i.e., Sel _ int₂) Internally generating a multi-bit selection input signal Sel _ in<N-1:0>. In response to the loading clock signal LD _ CLK (Generated from the data clock signal CLK by the clock GATE C-GATE), the flip-flop 304 is loaded with the output of the AND GATE 350. Only the flip-flop 304(9) coupled to the output of the AND gate 350(9) is set to a logic 1 value. Thus, the generated multi-bit selection signal Sel<N-1:0>At a time period t₂(Selt₂) Has an internal value of<0,0,…,0,1,0,0,0,0,0,0,0,0,0>. Therefore, since the bit Sel (9) is logic 1, k is 9. By connecting DT (7) to output DW (0), DT (8) to outputs DW (1), … …, DT (5) to output DW (N-2), and DT (6) to output DW (N-2), cross-over switch matrix 204 response has values<0,0,…,0,1,0,0,0,0,0,0,0,0,0>Is selected from the multiple bits of the selection signal Sel<N-1:0>. The circuit 200 is in the time period t₂Internal output value of<1,1,1,…,1,1,1,1,1,1>(i.e., all bits are logic 1 values) of a multi-bit output data word DW<N-1:0>(i.e., DWt)₂). Thus, a multi-bit input data word DT<N-1:0>The 16 logical 1 value bits DWA of are converted into a multi-bit output data word DW<N-1:0>With the bit position at which the logical transition is started at bit DW (9) and the bit position at which the logical transition is ended at bit DW (8).

At this time, the NAND gate 312 of the clock generation circuit 300 detects the data word DT for the multi-bit input<N-1:0>Is/are as follows<1,1,1,…,1,1,1,1,1,1>(i.e., all bits are a logic 1 value) and generates a signal 314 having a logic 0 value, thereby causing the clock GATE circuit C-GATE to be disabled. Will not transfer the data clock signal CLK and in the next time period t₃The middle load clock signal LD _ CLK does not present an edge that triggers the operation of the flip-flop 304.

Now, consider the time period t₃To a received multi-bit input data word DT<N-1:0>Has a value of<0,0,0,…,0,0,0,1>(i.e., thermometer encoded value of data word is 1, binary<0,0,1>). DWA control circuit 210 from a previous time period t₂Starting for a value of<1,1,1,…,1,1,1,1,1,1>(i.e., all bits are logic 1 values) of a multi-bit output data word DW<N-1:0>Processing is performed to identify the most significant bit (i.e., the location at which the logical transition ends) that has a logical 1 value. In this case, there is no bit because all bits have a logic 1 valueSuch a bit. All flip-flops 304 will output logic 0 values, which may result in erroneous operation of the switch matrix. However, this is in conjunction with the control circuit 212 at the current time period t₃Internally generating a multi-bit select signal Sel<N-1:0>The operation of the time is irrelevant. The reason for this is that it is currently in the time period t₃The clock GATE C-GATE is disabled and therefore no loading of a new value into the flip-flop 304 is performed. Instead, the flip-flop 304 is triggered from the previous time period t₂A starting reserve value of<0,0,…,0,1,0,0,0,0,0,0,0,0,0>Previous multi-bit select signal Sel<N-1:0>The previous multi-bit selection signal Sel<N-1:0>Indicating the location where the logical transition is to be ended. Therefore, since the bit Sel (9) is logic 1, k is 9. Cross-over switch matrix 204 has values in response by connecting DT (7) to output DW (0), DT (8) to output DW (1), DT (5) to output DW (N-2), and DT (6) to output DW (N-2)<0,0,…,0,1,0,0,0,0,0,0,0,0,0>Is selected from the multiple bits of the selection signal Sel<N-1:0>. The circuit 200 is in the time period t₃Has a medium output value of<0,0,…,0,1,0,0,0,0,0,0,0,0,0>Is a multi-bit output data word DW<N-1:0>(i.e., DWt)₃). Thus, a multi-bit input data word DT<N-1:0>Is converted into a multi-bit output data word DW<N-1:0>The bit position where the logical transition is started is at bit DW (9), and the bit position where the logical transition is ended is also at bit DW (9).

As shown herein, AND logic 350 is used as a type of edge detector that detects data input transitions from 1 to 0 (rather than 0 to 1) that occur at bit positions where a logic transition begins. Since inputs with all logic 1 values or all logic 0 values will not exhibit such bit transitions, the output of AND logic 350 is all logic 0 under such conditions. If the output is not detected and blocked, the output causes the deselection of all of the switches in the crossbar to be deselected. To handle this scenario, LD _ CLK is disabled for all logic 1 inputs or all logic 0 inputs, and the previous state of select signal Sel is maintained.

Now, consider an operation at a later point in time, in which a multi-bit output data word DW<N-1:0>Before oneTime period t_i-1Having a value of<0,0,1,1,1,1,…,0,0,0>. Suppose that during the current time period t_iReceived multi-bit input data word DT<N-1:0>Has a value of<0,0,…,0,1,1,1,1>(i.e., thermometer encoded value of data word is 4, binary<1,0,0>). DWA control circuit 210 pairs the previous time period t_i-1Starting value is<0,0,1,1,1,1,…,0,0,0>Is a multi-bit output data word DW<N-1:0>Processing is performed to identify the most significant bit (i.e., the location at which the logical transition ends) that has a logical 1 value. In this case, this may be bit DW (N-3) or bit DW (13) found by AND gate 350(14), where N ═ 16, the AND gate 350(14) having a first input that receives the logically inverted phase DW (14); and a second input receiving bit DW (13). Thus, during the current time period t_i(i.e., Sel _ int_i) In the first step, a multi-bit selection input signal Sel _ in is generated<N-1:0>. Flip-flop 304 is loaded with the output of AND GATE 350 in response to the loading clock signal LD _ CLK (generated from the data clock signal CLK by clock GATE C-GATE). Only the flip-flop 304(14) coupled to the output of the AND gate 350(14) is set to a logic 1 value. Thus, the generated multi-bit selection signal Sel<N-1:0>Has a value of<0,1,0,…,0,0,0,0>. Therefore, since the bit Sel (14) is logic 1, k is 14. Cross-over switch matrix 204 response has values by connecting DT (2) to output DW (0), DT (3) to outputs DW (1), … …, DT (1) to output DW (N-2), and DT (0) to output DW (N-2)<0,1,0,…,0,0,0,0>Is selected from the multiple bits of the selection signal Sel<N-1:0>. The circuit 200 is at the current time period t_iHas a medium output value of<1,1,0,…,0,0,0,0,0,1,1>Is a multi-bit output data word DW<N-1:0>(i.e., DWt)_i). Thus, a multi-bit input data word DT<N-1:0>Converts the four logic 1 value bits DWA into a multi-bit output data word DW<N-1:0>With the bit position where the logical transition begins at bit DW (14) and the wrap-around ends at the bit position where the logical transition ends at bit DW (1).

As another example of the operation of the circuit 200 where N ═ 16, consider the following multi-bit input data word DT<15:0>Multi-bit output data word DW<15:0>And a multi-bit select signalSel<15:0>At a time from t₀To t₆The value in the time period of (c):

-a multi-bit input data word DT <15:0>

t₀:0000000000000111

t₁:0000000111111111

t₂:0000000000000011

t₃:0000000001111111

t₄:1111111111111111

t₅:0000000000001111

-a multi-bit output data word DW <15:0>

t_init:0000000000000000

t₀:0000000000000111

t₁:0000111111111000

t₂:0011000000000000

t₃:1100000000011111

t₄1111111111111111 chooses to be held by this value

t₅:0000000111100000

-a multi-bit selection signal Sel <15:0>

t₀0000000000000001 initializes the selection

t₁:0000000000001000

t₂:0001000000000000

t₃:0100000000000000

t₄:0000000000100000

t₅0000000000100000 selecting from t₄Start of hold

t₆:0000001000000000

It should be noted that at time t_initAt, a multi-bit output data word DW<15:0>Has no value and is in time period t₀In this case, the multi-bit selection signal Sel is selected using the start value of DWA conversion with k being 0<15:0>Initialization is performed. At a time period t₀At a multi-bit input data word DT<15:0>Thermometer code value ofIs composed of<0000000000000111>And where k is 0, crossbar 204 is controlled to be at time period t₁Will have a value of<0000000000000111>Of a multi-bit input data word DT<15:0>Mapping to a value of<0000000000000111>Is a multi-bit output data word DW<15:0>。

At time t₀The multi-bit output data word DW<15:0>At time t₁Is given a value of<000000000001000>Is selected from the multiple bits of the selection signal Sel<15:0>And k is 3. At time t₁At a multi-bit input data word DT<15:0>Has a thermometer code value of<0000000111111111>And in the case where k is 3, the crossbar 204 is controlled to be at time t₁Will have a value of<0000000111111111>Of a multi-bit input data word DT<15:0>Mapping to a value of<0000111111111000>Is a multi-bit output data word DW<15:0>。

At time t₁The multi-bit output data word DW<15:0>At time t₂Is given a value of<0001000000000000>Is selected from the multiple bits of the selection signal Sel<15:0>And k is 12. At time t₂At a multi-bit input data word DT<15:0>Has a thermometer code value of<0000000000000011>And in the case where k is 12, the crossbar 204 is controlled to be at time t₂Will have a value of<0000000000000011>Of a multi-bit input data word DT<15:0>Mapping to a value of<0011000000000000>Is a multi-bit output data word DW<15:0>。

At time t₂The multi-bit output data word DW<15:0>At time t₃Is given a value of<0100000000000000>Is selected from the multiple bits of the selection signal Sel<15:0>And k is 14. At time t₃At a multi-bit input data word DT<15:0>Has a thermometer code value of<0000000001111111>And in the case where k is 14, the crossbar 204 is controlled to be at time t₃Will have a value of<0000000001111111>Of a multi-bit input data word DT<15:0>Mapping to a value of<1100000000011111>Is a multi-bit output data word DW<15:0>. Note the wrap around of the bits.

At time t₃The multi-bit output data word DW<15:0>At time t₄Is given a value of<0000000000100000>Is selected from the multiple bits of the selection signal Sel<15:0>And k is 5. At time t₄At a multi-bit input data word DT<15:0>Has a thermometer code value of<1111111111111111>And in the case where k is 5, the crossbar 204 is controlled to be at time t₄Will have a value of<1111111111111111>Of a multi-bit input data word DT<15:0>Mapping to a value of<1111111111111111>Is a multi-bit output data word DW<15:0>。

Detecting time t by clock generation circuit 300₄Has a value of<1111111111111111>The multi-bit output data word DW of<15:0>The clock generation circuit 300 responds by disabling the clock GATE circuit C-GATE. Thus, the data clock signal CLK is prevented from being transferred. Without the load clock signal LD _ CLK, time t₄Has a value of<1111111111111111>Is a multi-bit output data word DW<15:0>Will not result in the multi-bit selection signal Sel<15:0>Any change occurs, the multi-bit selection signal Sel<15:0>At time t₅Is maintained at a value of<0000000000100000>And k is 5. Time t₅At a multi-bit input data word DT<15:0>Has a thermometer code value of<0000000000001111>And in the case where k is 5, the crossbar 204 is controlled to be at time t₅Will have a value of<0000000000001111>Of a multi-bit input data word DT<15:0>Mapping to a value of<0000000111100000>Is a multi-bit output data word DW<15:0>。

At time t₅Has a value of<0000000111100000>Is a multi-bit output data word DW<15:0>At time t₆Is given a value of<0100000000000000>Is selected from the multiple bits of the selection signal Sel<15:0>And k is 9.

Refer again to fig. 5 for checking the timing relationship.

For Input_delayReferences to (d) refer to the delay from the external data source providing the thermometer data DT. This is some finite time for the timing of the data relative to the data clock to reach the circuit 200. At the edge and temperature of the data clockThere is no temporal timing relationship between the presentation of the meter data DT.

To XbarSW_delayReferences to (1) refer to the delay between data input to the crossbar and data output from the crossbar. This delay is both visible and consequent when the selection of the crossbar is stable. For first data input-output only (only at t)₀Post-initialization) and such a condition occurs if all bits of the input are logic 1 or logic 0. At other times, the select signal Sel will be unstable and will be part of the critical path.

For t_criticalReferences herein refer to the functional critical path of the design (not during initialization nor when all bits are logic 1's or all logic 0's) that includes the clock-to-flip-flop Q output delay of flip-flop 304 and the select-to-output delay of the crossbar.

To AND_delayReferences to (1) refer to the delay for the data weighted average output in response to selecting the Sel _ in signal. Basically, this is the delay associated with the operation of the AND logic circuit. It will be appreciated that this delay is not part of the critical path, as its value stabilizes at the current output and stabilizes much before the subsequent clock rising edge. Sel _ in is loaded onto flip-flop 304 in a subsequent cycle.

Thus, the waveforms in fig. 5 and the illustrated timing relationships show that the DWA output is available in a short time span of the presentation input. This small transition time can be attributed primarily to the clock-to-Q delay of the flip-flops, as well as the select-to-output delay of the crossbar. Although output computation directly involves processing by logic 350 and circuit 300 (clock gating logic), with the proposed architecture, these tasks are excluded from timing critical paths.

Referring now to fig. 6, a block diagram of a continuous-time sigma-delta analog-to-digital converter circuit 400 is shown. An analog input voltage Vin is received at a first input of the summing circuit 402. A second input of the summing circuit 402 receives an analog feedback voltage Vfb. The summing circuit 402 is used to determine the difference between the analog input voltage Vin and the analog feedback voltage Vfb and generate an analog difference voltage Vdif (i.e., Vdif is Vin-Vfb). A loop filter 404, implementing, for example, an integration function, receives the analog difference voltage Vdif and outputs an analog filtered voltage Vfltr. The multi-bit quantizer circuit 406 quantizes the analog filtered voltage Vfltr to generate a multi-bit input data word DT on a rising edge of the clock signal CLK (i.e., the multi-bit quantizer circuit 406 is clocked by the clock signal). The multi-bit quantizer circuit 406 corresponds to the quantizer 203 of fig. 2. The multi-bit input data word DT is applied to a Data Weighted Average (DWA) circuit 408, such as the circuit 200 shown in fig. 2. The DWA circuit 200 outputs a data word DW that may be processed (e.g., decimated and digitally filtered) in a manner known to those skilled in the art to generate a digital signal corresponding to the conversion of the analog input voltage Vin. In the feedback loop, the data word DW is input to a digital-to-analog converter circuit 410, which digital-to-analog converter circuit 410 converts the data word DW to generate an analog feedback voltage Vfb. Digital-to-analog converter circuit 410 includes an input register 412 that latches data word DW on the falling edge of clock signal CLK (i.e., input register 412 is clocked by the logical inverse of the clock signal (CLK bar)). The latched output of data word DWL provides digital information that is converted to an analog feedback voltage Vfb by digital to analog converter circuit 410.

Disclosure of Invention

This summary is provided to introduce a selection of concepts that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in limiting the scope of the claimed subject matter.

In an embodiment, a circuit includes a crossbar having an input configured to receive a thermometer-coded signal and an output configured to output a data-weighted average signal, wherein switching between the input and the output of the crossbar is controlled by a crossbar select signal; a data register configured to latch the output data weighted average signal and generate a latched data weighted average signal; and a control circuit configured to receive the latched data weighted average signal and determine a bit position within the latched data weighted average signal at which an ending logic transition occurs from bits of the latched data weighted average signal, and to generate a crossbar selection signal to control switching between the inputs and outputs of the crossbar to select the bit position within the output data weighted average signal at which a beginning logic transition occurs.

In an embodiment, a circuit includes an input data bus carrying a multi-bit input data word having a thermometer encoded format; a crossbar having switch inputs coupled to the input data bus to receive the multi-bit input data word; and a switch output configured to output a multi-bit output data word, the multi-bit output data word being a Data Weighted Average (DWA) conversion of a thermometer-coded, multi-bit input data word; a data register configured to latch a multi-bit output data word and generate a latched multi-bit output data word; and a DWA control circuit configured to receive the latched multi-bit output data word and to generate a multi-bit selection signal from the latched multi-bit output data word, the multi-bit selection signal being applied to a control input of the crossbar by a selection data bus; wherein the crossbar is configured to operate in response to the multi-bit select signals to selectively map the switch inputs to the switch outputs to enable DWA conversion of the thermometer-coded multi-bit input data word to output a multi-bit output data word.

In an embodiment, a method comprises: receiving a thermometer coded signal; converting the thermometer encoded signal to an output data weighted average signal in response to the selection signal; latching the output data weighted average signal to generate a latched data weighted average signal; determining an ending bit position of the latched data weighted average signal for ending logic conversion according to all bits of the latched data weighted average signal; and generating a selection signal to control the switching to select a start bit position at which the output data weighted average signal occurs to start the logical switching.

Drawings

Fig. 1 compares the operation of a data converter without a Data Weighted Averaging (DWA) algorithm with a data converter without a DWA.

Fig. 2 is a block diagram of a prior art DWA circuit.

Fig. 3 is a logical representation of a multiplexer using a crossbar switch as used in the DWA circuit of fig. 2.

Fig. 4 is a circuit diagram of a DWA control circuit as used for the DWA circuit of fig. 2.

Fig. 5 is a timing diagram of the operation of the DWA circuit of fig. 2.

Fig. 6 is a block diagram of a continuous-time sigma-delta analog-to-digital converter circuit utilizing the DWA circuit of fig. 2 in a feedback loop.

Fig. 7 is a block diagram of a DWA circuit.

Fig. 8 is a circuit diagram of a DWA control circuit as used for the DWA circuit of fig. 7.

FIG. 9 is a block diagram of a continuous-time sigma-delta analog-to-digital converter circuit utilizing the DWA circuit of FIG. 7 in a feedback loop.

Fig. 10 is a timing diagram of the operation of the continuous-time sigma-delta analog-to-digital converter circuit of fig. 9.

Detailed Description

In the following detailed description and the accompanying drawings, specific details are set forth in order to provide a thorough understanding of the present disclosure. However, it will be appreciated by one skilled in the art that in some instances the present disclosure may be practiced without such specific details. In other instances, well-known elements have been illustrated in schematic or block diagram form in order not to obscure the present disclosure in unnecessary detail. Additionally, in most cases, specific details, etc., are omitted, as such details are not necessary to obtain a complete understanding of the present disclosure, and are considered to be within the understanding of persons of ordinary skill in the relevant art.

Referring now to fig. 7, a block diagram of a Dynamic Weighted Averaging (DWA) circuit 200' is shown. The circuit includes a data bus 202, the data bus 202 carrying a multi-bit input data word DT < N-1:0> having a thermometer coded format (where the data word DT < N-1:0> may be supplied, for example, from a quantizer circuit 203 clocked by a data clock signal clk (clk)). In an example, N ═ 16; however, it should be understood that the solution disclosed herein is extensible for any value of N. The data bus 202 is connected to the data inputs of the crossbar 204. The outputs of crossbar matrix 204 are connected to data bus 206, and data bus 206 carries a multi-bit output data word DW < N-1:0>, which is a data weighted average conversion of thermometer-coded multi-bit input data word DT < N-1:0 >. Register 214 'receives the multi-bit output data word DW < N-1:0> and a logical inverse of the data clock signal CLK (CLK bar), and register 214' operates to latch data of the received multi-bit data output data word DW < N-1:0> and output the latched multi-bit output data word DWL < N-1:0 >. DWA control circuit 210 'receives the most significant bits and the least significant bits of the multi-bit input data words DT < N > and DT <0>, as well as the latched multi-bit output data words DWL < N-1:0> and the logical inverse of the data clock signal CLK (CLK bar), and DWA control circuit 210' operates to generate a multi-bit select signal Sel < N-1:0> that is applied to the control inputs of crossbar matrix 204 via data bus 212. Crossbar 204 operates in response to multi-bit select signal Sel < N-1:0> to selectively map switch inputs to switch outputs to achieve data weighted average conversion and to achieve first order Dynamic Element Matching (DEM).

The physical configuration of crossbar 204 is shown in FIG. 4 and, as described above, operates in response to multi-bit select signal Sel < N-1:0 >.

Referring now to FIG. 8, a circuit diagram of registers 214 'and DWA control circuit 210' is shown. The register 214' includes N flip-flops FF 504(0) through 504(N-1), and N flip-flops FF 504(0) through 504(N-1) are clocked by a logical inverse of the data clock signal CLK (CLK bar). In order to conform to the example provided above, in fig. 8, N ═ 16; however, it should be understood that the solution disclosed herein is extensible for any value of N. Flip-flops FFs 504 each receive a bit of a multi-bit output data word DWL < N-1:0> from data bus 206 and output a corresponding bit of a latched multi-bit output data word DWL < N-1:0 >.

DWA control circuit 210' includes clock logic circuit 500 and combinatorial logic circuit 502. Combinational logic circuit 502 is formed from N logic AND gates 550(0) through 550(N-1), which N logic AND gates 550(0) through 550(N-1) operate to generate multi-bit select signals Sel < N-1:0>, which are applied to control the switching operation of crossbar 204. A first input of each AND gate 350 is connected to a logical inversion of a corresponding bit of the latched multi-bit output data word DWL < N-1:0>, which is output by flip-flop 504 of register 214'. A second input of each AND gate 550 is connected to adjacent bits of the latched multi-bit output data word DWL < N-1:0 >. For example, AND gate 550(0) has a first input connected to receive the logical inverse of the corresponding bit DWL (0); and a second input connected to receive a neighbor bit DW (N-1), which in the example where N ═ 16 may be DWL (15). The output of AND gate 550(0) is the input to clock logic circuit 500, AND clock logic circuit 500 generates an output as one bit (Sel (0)) of a multi-bit input select signal Sel _ in < N-1:0 >. Likewise, AND gate 550(N-1) (which may be AND gate 550(15) in the example where N ═ 16) has a first input connected to receive the logical inverse of the corresponding bit DWL (N-1) (which may be a DWL (15) bit in the example where N ═ 16); and a second input connected to receive an adjacent bit DWL (N-2) (which may be bit DWL (14) in the example where N-16). The output of AND gate 550(N-1) provides the other bit (Sel (15)) of the multi-bit input select signal Sel _ in < N-1:0 >. Likewise, other AND gates 550 are connected to the logic inverse AND adjacent bits that latch the multi-bit output data word DWL < N-1:0>, AND generate corresponding bits of the multi-bit input select signal Sel _ in < N-1:0 >.

The combinational logic circuit 502 operates to find the most significant bit position in the received latched multi-bit output data word DWL < N-1:0> having a logic 1 value. In other words, this is the bit position where the logic 1 bit string in the latched multi-bit output data word DWL < N-1:0> occurs to end the logic transition (from logic 1 to logic 0). The second input receives the logic 1 value AND the first input will output a logic 1 value from AND gate 550 which receives a logic 0 value from the next adjacent upper bit in the latched multi-bit output data word DWL < N-1:0 >. All other AND gates 550 will output a logic low value because at least one of their first or second inputs will receive a logic 0 input. The connection of AND gate 550(0) to receive the logical inversion of the corresponding bit DWL (0) AND the adjacent bit DWL (N-1) is important because this connection enables wrap-around of the operation of finding the most significant bit position. The operation performed by the combinational logic circuit 502 to find the most significant bit positions is substantially the same as that discussed above for the combinational logic circuit 302 and fig. 4.

The clock logic circuit 500 includes an exclusive nor logic gate 520, the exclusive nor logic gate 520 having a first input that receives the least significant bit (bits 0: DT (0)) of a multi-bit input data word DT < N-1:0 >; and a second input receiving the most significant bits (bits N-1: DT (N-1)) of a multi-bit input data word DT < N-1:0 >. The signal output from the exclusive nor logic gate 520 is applied to the data input of a D-type flip-flop 522 clocked by the logic inverse (CLK bar) of the data clock signal CLK. Thus, the D-type flip-flop 522 captures the logic state of the output signal from the xor logic gate 520 at the falling edge of the clock signal CLK and makes the logic state value available at the Q output of the flip-flop 522. OR logic gate 524 has a first input that receives the Q output of flip-flop 522; AND a second input that receives the output of AND gate 550(0) in combinational logic circuit 502. The signal output by OR logic gate 524 is the Sel (0) bit of the multi-bit input select signal Sel _ in < N-1:0 >.

The operation of the clock logic 500 is as follows: the exclusive nor logic gate 520 determines when both the least significant bit (bit 0: DT (0)) and the most significant bit (bit N-1: DT (N-1)) of the multi-bit input data word DT < N-1:0> are logic 0 or logic 1. For thermometer encoded data, this operation only occurs when all bits of the data word DT < N-1:0> are logic 0's or when all bits of the data word DT < N-1:0> are logic 1's. Clock logic circuit 500 captures this occurrence because when all bits of data word DT < N-1:0> are logic 0 or all bits of data word DT < N-1:0> are logic 1, there is no transition from 1 to 0 in data word DW < N-1:0>, so all AND gates 550 of combinational logic circuit 502 will output a logic 0 value for the multi-bit input select signal NOR. In this case, all switches within crossbar 204 are deselected and the signal lines of data words DW < N-1:0> at the inputs of register 214' will float. Such switch deselection and floating output conditions must be avoided.

The logic state of the output signal from the exclusive nor logic gate 520 is logic 1 when both the least significant bit (bit 0: DT (0)) and the most significant bit (bit N-1: DT (N-1)) of the multi-bit input data word DT < N-1:0> are logic 0 or logic 1. The logic state is captured and held by the D-type flip-flop 522 at the falling edge of the clock signal. In response to a logic 1 output from flip-flop 522, OR logic gate 524 forces at least one of the bits of multi-bit input select signal Sel _ in < N-1:0> to a logic 1. Any of these bits may be used in this case, and the example shown in FIG. 8 uses an OR logic gate 524 connected to the signal line of the Sel (0) bit to force a logic 1 state. The logic state of the output signal from the exclusive nor logic gate 520 is a logic 0 under any other combinational logic condition of the least significant bit (bit 0: DT (0)) and the most significant bit (bit N-1: DT (N-1)) of the multi-bit input data word DT < N-1:0>, and the logic state is captured and held by the D-type flip-flop 522 at the falling edge of the clock signal CLK. The OR logic gate 524 then permits the logic state of the Sel (0) bit of the multi-bit input select signal Sel _ in < N-1:0> to follow the logic state of the signal output by AND gate 550(0) in the combinational logic circuit 502.

In response to a falling edge of the clock signal CLK, the N flip-flops 504(0) through 504(N-1) of the register 214' will load N bits of the multi-bit output data word DW < N-1:0> AND output a corresponding N bits of the latched multi-bit output data word DWL < N-1:0> for processing by the logic AND gates 350(0) through 350(N-1) of the combinational logic circuit 502 to generate the multi-bit input select signal Sel _ in < N-1:0 >. Since only one AND gate output will have a logic 1 value at a time, this means that only one bit at a time of the multi-bit select signal Sel < N-1:0> has a logic 1 value. This one bit of multi-bit select signal Sel < N-1:0> having a logic 1 value specifies the location of the operation of crossbar 204 (as described above, reference k) for controlling the connection of the bits of multi-bit input data word DT < N-1:0> to the bits of multi-bit output data word DW < N-1:0> in a particular order. Examples of this operation are discussed in detail above. In effect, the location provided by multi-bit select signal Sel < N-1:0> identifies the bit position of the next multi-bit output data word DW < N-1:0> at which the start logic transition should occur to achieve the data weighted average. This is where the logic 1 bit string in the next data word DW should start.

However, the foregoing operation is modified in the event that the least significant bit (bits 0: DT (0)) and the most significant bit (bits N-1: DT (N-1)) of the multi-bit input data word DT < N-1:0> have the same logic state. This condition is detected by the XOR logic gate 520 of the clock logic circuit 500, which XOR logic gate 520 forces the logic state of the Sel (0) bit to logic 1 in order to ensure that at least one bit of the multi-bit select signal Sel < N-1:0> will have a logic 1 value.

Referring now to fig. 9, a block diagram of a continuous-time sigma-delta modulator (analog-to-digital converter) circuit 400' is shown. An analog input voltage Vin is received at a first input of the summing circuit 402. A second input of the summing circuit 402 receives an analog feedback voltage Vfb. The summing circuit 402 is used to determine the difference between the analog input voltage Vin and the analog feedback voltage Vfb and generate an analog difference voltage Vdif (i.e., Vdif is Vin-Vfb). A loop filter 404, implementing, for example, an integration function, receives the analog difference voltage Vdif and outputs an analog filtered voltage Vfltr. The multi-bit quantizer circuit 406 quantizes the analog filtered voltage Vfltr to generate a multi-bit input data word DT on a rising edge of the clock signal CLK (i.e., the multi-bit quantizer circuit 406 is clocked by the clock signal). The multi-bit quantizer circuit 406 corresponds to the quantizer 203 of fig. 7. The multi-bit input data word DT is applied to a Data Weighted Average (DWA) circuit 408, such as the circuit 200' shown in fig. 7. The circuit 200' outputs a data word DW that can be processed (e.g., decimated and digitally filtered) in a manner well known to those skilled in the art to generate a digital signal corresponding to the conversion of the analog input voltage Vin. In the feedback loop, data word DW is input to digital-to-analog converter circuit 410, which converts data word DW to generate analog feedback voltage Vfb. Digital-to-analog converter circuit 410 includes an input register 412 that latches data word DW on the falling edge of clock signal CLK (i.e., input register 412 is clocked by the logical inverse of the clock signal (CLK bar)). The input register 412 corresponds to the register 214' shown in fig. 7 and 8. The latched output of data word DWL provides digital information that is converted to an analog feedback voltage Vfb by digital to analog converter circuit 410. Further, the latched output of data word DWL and the least significant bits (bits 0: DT (0)) and the most significant bits (bits N-1: DT (N-1)) of multi-bit input data word DT < N-1:0> provide digital information that is processed by DWA control circuit 210' in connection with the generation of multi-bit select signal Sel < N-1:0 >.

Fig. 10 illustrates timing relationships for the operation of a continuous-time sigma-delta analog-to-digital converter circuit 400'. It should be noted that the switch selection is already asserted before the rising edge of the clock CLK, so only the input-to-output delay of the (cross-bar) switch enters the critical timing path. Further, the switching delay is very small, and therefore there is enough time for the quantizer to operate.

The implementation of fig. 7-9 has several advantages over the prior art implementation of fig. 2, 4 and 6: a) the memory elements provided by flip-flops 304 for storing the select logic of the crossbar are eliminated; b) no clock-to-Q output delay in the critical timing path; c) the circuit operates with very low computational delay (only switching delay) and therefore may permit operation at very high data rates (e.g., up to 6 GHz); d) the circuit does not require decoders and adders using components of conventional DWA circuits; e) the circuit supports operation in a high-speed feedback topology; f) the regular modular structure of the circuit permits a fast implementation; g) the circuit operates with low power and low area consumption; and h) advantageously using the input registers of the DAC circuit to support operation of the DWA control circuit.

Although the foregoing description has been described herein with reference to particular circuits and embodiments, it is not intended to be limited to the details disclosed herein; the present invention is not limited to the disclosed embodiments; rather, it extends to all functionally equivalent structures, methods and uses, such as are within the scope of the appended claims.

Claims

1. A circuit, comprising:

a crossbar having: an input configured to receive a thermometer encoded signal; and an output configured to output a data weighted average signal, wherein switching between the inputs and the outputs of the crossbar is controlled by a crossbar select signal;

a data register configured to latch the output data weighted average signal and generate a latched data weighted average signal; and

a control circuit configured to receive the latched data weighted average signal and determine a bit position within the latched data weighted average signal at which an ending logic transition occurs based on bits of the latched data weighted average signal and to generate the crossbar select signal to control switching between the inputs and the outputs of the crossbar to select a bit position within the output data weighted average signal at which a beginning logic transition occurs.

2. The circuit of claim 1, wherein the latched data weighted average signal comprises a plurality of bits, and wherein the control circuit comprises a combinational logic circuit configured to logically combine the plurality of bits of the latched data weighted average signal to detect the bit position of the latched data weighted average signal at which the ending logic transition occurs.

3. The circuit of claim 2, wherein the combinational logic circuit comprises a plurality of AND gates, each AND gate having: a first input coupled to receive one bit of the latched data weighted average signal; and a second input coupled to receive another bit of the latched data weighted average signal, wherein the one bit and the other bit are adjacent bits within the latched data weighted average signal.

4. The circuit of claim 3, wherein the plurality of AND gates generate a select input signal specifying the bit position of the latched data weighted average signal at which the start logic transition occurs.

5. The circuit of claim 4, wherein the select input signals generated by the plurality of AND gates are applied directly to select inputs of the crossbar.

6. The circuit of claim 2, further comprising a quantization circuit configured to generate the thermometer-coded signal at one of a rising edge or a falling edge of a clock signal, and wherein the data register latches the output data weighted average signal at the other of the rising edge or the falling edge of the clock signal.

7. The circuit of claim 6, further comprising a clock logic circuit comprising:

a detection circuit configured to detect a full logic 1 state or a full logic 0 state of a bit of the thermometer encoded signal; and

a logic circuit configured to force a particular logic state of one bit of the select input signal in response to detection of the full logic 1 state or the full logic 0 state of a bit of the thermometer encoded signal by the detection circuit, the forced logic state being different from a logic state of the one bit of the select input signal generated by the combinational logic circuit.

8. The circuit of claim 7, wherein the logic circuit comprises a flip-flop configured to store a value of a signal output by the detection circuit in response to the other of the rising edge or the falling edge of the clock signal.

9. The circuit of claim 8, wherein the logic circuit further comprises a logical OR gate configured to logically combine the output of the flip-flop and the one bit of the select input signal generated by the combinational logic circuit.

10. The circuit of claim 1, wherein the thermometer coded signal comprises a plurality of bits, and wherein the output data weighted average signal comprises a plurality of bits, the crossbar being operative to selectively connect the bits of the thermometer coded signal to the bits of the output data weighted average signal in an order having barrel shift positions specified by the cross select signal.

11. The circuit of claim 10, wherein the barrel shift position positions locate the bit position for the beginning logic transition of the output data weighted average signal adjacent to the bit position for the ending logic transition of the latched data weighted average signal.

12. The circuit of claim 1, further comprising:

a digital-to-analog converter circuit having an input register formed by the data register, the digital-to-analog converter circuit configured to convert the latched data weighted average signal to a first analog voltage.

13. The circuit of claim 12, further comprising:

a summing circuit configured to receive the first and second analog voltages and to generate a difference analog voltage from the first and second analog voltages;

a loop filter configured to filter the difference analog voltage to generate a filtered analog voltage; and

a quantization circuit configured to quantize the filtered analog voltage to generate the thermometer-encoded signal.

14. The circuit of claim 13, wherein the quantization circuit generates the thermometer-encoded signal at one of a rising edge or a falling edge of a clock signal, and wherein the data register latches the output data weighted average signal at the other of the rising edge or the falling edge of the clock signal.

15. A circuit, comprising:

an input data bus carrying a multi-bit input data word having a thermometer encoded format;

a crossbar having: a switch input coupled to the input data bus to receive the multi-bit input data word; and a switch output configured to output a multi-bit output data word that is a data weighted average, DWA, conversion of the thermometer-encoded multi-bit input data word;

a data register configured to latch the multi-bit output data word and generate a latched multi-bit output data word; and

a DWA control circuit configured to receive the latched multi-bit output data word and to generate a multi-bit selection signal from the latched multi-bit output data word, the multi-bit selection signal applied to a control input of the crossbar by a selection data bus;

wherein the crossbar matrix is configured to operate in response to the multi-bit select signals to selectively map the switch inputs to the switch outputs to effect the DWA conversion of the thermometer-encoded multi-bit input data word to output the multi-bit output data word.

16. The circuit of claim 15, wherein the DWA control circuit is configured to receive bits of the thermometer-coded multi-bit input data word and to force a particular mapping of switch inputs to the switch outputs if the received thermometer-coded multi-bit input data word indicates that all bits of the thermometer-coded multi-bit input data word are logic 1's or logic 0's.

17. The circuit of claim 16, wherein the DWA control circuit comprises a clocked logic circuit comprising:

an exclusive-nor gate configured to receive the bits of the thermometer-encoded multi-bit input data word;

a flip-flop configured to store an output from the exclusive nor gate in response to a clock signal, the clock signal further controlling latching by the data register; and

an OR gate responsive to an output of the flip-flop and configured to generate a bit of the multi-bit selection signal.

18. The circuit of claim 15, wherein the DWA control circuit is configured to generate the multi-bit selection signal in a manner such that only one bit of the multi-bit selection signal is asserted at a time.

19. The circuit of claim 18, wherein the crossbar is operative to selectively connect bits of the thermometer-coded multi-bit input data word to bits of the multi-bit output data word in an order of barrel shift positions specified by the one bit of the multi-bit select signal being asserted.

20. The circuit of claim 19, wherein the DWA control circuit comprises a combinational logic circuit configured to find a bit position for an ending logical transition of the bits of the latched multi-bit output data word, and wherein the multi-bit selection signal specifies a bit position for a beginning logical transition of the bits of the multi-bit output data word.

21. The circuit of claim 20, wherein the barrel shift position positions position the bit position for the starting logical transition of the multi-bit output data word adjacent to the bit position for the ending logical transition of the latched multi-bit output data word.

22. The circuit of claim 15, further comprising:

23. The circuit of claim 22, further comprising:

24. The circuit of claim 23, wherein the quantization circuit generates the thermometer-encoded signal at one of a rising edge or a falling edge of a clock signal, and wherein the data register latches the multi-bit output data word at the other of the rising edge or the falling edge of the clock signal.

25. A method, comprising:

receiving a thermometer coded signal;

converting the thermometer encoded signal to an output data weighted average signal in response to a selection signal;

latching the output data weighted average signal to generate a latched data weighted average signal;

determining, from all bits of the latched data weighted average signal, an ending bit position at which an ending logic transition occurs in the latched data weighted average signal within the latched data weighted average signal; and

the selection signal is generated to control the switching to select a start bit position at which the output data weighted average signal occurs to start a logical switch.

26. The method of claim 25, wherein generating the selection signal comprises: outputting the select signal having a plurality of bits, wherein only one bit corresponding to the start bit position has a first logic state and all other bits have a second logic state.

27. The method of claim 25, wherein determining comprises: logically combining all bits of the latched data weighted average signal to detect the ending bit position of the latched data weighted average signal at which the ending logic transition occurs.

28. The method of claim 27, wherein logically combining comprises: AND performing logic AND operation on adjacent bit pairs of the data weighted average signal.

29. The method of claim 27, further comprising: quantizing the analog voltage at one of a rising edge or a falling edge of the clock signal to generate the thermometer-encoded signal, and wherein latching comprises: latching the output data weighted average signal at the other of the rising edge or the falling edge of the clock signal.

30. The method of claim 29, further comprising:

detecting a full logic 1 state or a full logic 0 state of a bit of the thermometer encoded signal; and

forcing a particular logic state of one bit of the select input signal in response to detecting the full logic 1 state or the full logic 0 state of a bit of the thermometer encoded signal, the forced logic state being different from a logic state of the one bit of the select input signal generated as a result of the logical combination.

31. The method of claim 30, further comprising: storing a value from the detecting in response to the other of the rising edge or the falling edge of the clock signal.

32. The method of claim 25, wherein converting the thermometer encoded signal to the output data weighted average signal comprises: cross-switching in response to the select signal.

33. The method of claim 32, wherein the crossbar comprises: bits of the thermometer-coded signal are selectively connected to bits of the output data weighted average signal in an order specified by the select signal to have barrel shift positions at the start bit positions.

34. The method of claim 25, further comprising: the latched data weighted average signal is converted to a first analog voltage.

35. The method of claim 34, further comprising:

determining a difference analog voltage according to the first analog voltage and the second analog voltage;

filtering the difference analog voltage to generate a filtered analog voltage; and

quantizing the filtered analog voltage to generate the thermometer encoded signal.

36. The method of claim 35, quantizing is performed at one of a rising edge or a falling edge of a clock signal, and wherein latching is performed at the other of the rising edge or the falling edge of the clock signal.