JPH0773677A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To accelerate access to a RAM. CONSTITUTION:The potential of a common base line 111 of transistors 53, 54 controlling read currents of a pair of digit lines 101, 102 of a memory cell 1 is controlled synchronizing with a pair of complementary external clocks 112, 113 for fetching address. Thus, an output 115 of a clock buffer 2 synchronizing with the clock is supplied to the common base line 111 through a capacitor 3 for differential. Thus, since the currents of the digit lines 101, 102 are increased at the time of active transition of clock, the read currents are transmitted to an input of a sense amplifier rapidly. Since the currents are decreased at the time of non-active transistion of clock, no current consumption is increased totally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit for speeding up reading of a memory.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a schematic structure of a memory device including a semiconductor integrated circuit. In FIG. 4, the address signal 201 is taken into the address register 61 by a pair of complementary clock signals 112 and 113. This fetched address signal 202 is a RAM
The data is sent to an address buffer 62 in a macro (which includes a memory cell array and its peripheral circuits and has a configuration having a RAM function independently) 6 and is used as an address signal of the RAM macro 6. As can be seen from the above configuration, the RAM is synchronized with the clock signals 112 and 113.
An address signal is supplied to the macro 6.

Such a RAM macro 6 has a structure in which a part of its circuit is shown in FIG. 5. In particular, FIG.
6 is a circuit diagram showing a configuration of a read current portion of read data from FIG.

The reference voltage generating circuit 7 is connected to the bases of the transistors 53 and 54 by a line 111. The emitters of transistors 53 and 54 are connected to resistors 57 and 58 by lines 108 and 109, respectively. The other of the resistors 57 and 58 is commonly connected to the VEE potential 103.

The collectors of the transistors 53 and 54 are connected to the emitters of the transistors 51 and 52, respectively. The bases of transistors 51 and 52 are line 1
10 are commonly connected, and each collector is connected to digit lines 101 and 102, respectively. The digit lines 101 and 102 are connected to the emitters of the transistors 11 and 12 included in the memory cell 1, respectively.
Also, the word line 119 is connected to the memory cell 1. Details of the memory cell 1 and the reference voltage generating circuit 7 are omitted because they are not particularly necessary.

An outline of the operation will be described. In the reference voltage generating circuit 7, the transistors 53 and 54 and the resistors 57 and 58 form a constant current source, and a constant read current set by the reference potential of the line 111 is applied to the transistors 53 and 5.
4 (ie line 106 and line 107).

The address input to address buffer 62 in synchronization with clocks 112 and 113 causes line 11
When 0 becomes a high level potential, transistors 51 and 5
A read current flows from 2. At the same time, when the word line 119 is brought to a high level potential by an address, the memory cell 1 is selected, and a read current flows from either one of the transistors 11 and 12, and data can be read.

[0008]

In recent years, due to the speeding up of the device, the RAM macro 6 and the address register 61 are mounted on the same integrated circuit element as shown in FIG.
There is used a method of reducing the delay time from to the RAM macro 6 to speed up the entire device. In this case, the clock signals 112 and 113 are input as set signals to the register 61, but the clock signal has not been used in the RAM macro 6 in the related art, and there is a problem that sufficient speedup is not achieved.

An object of the present invention is to provide a semiconductor integrated circuit device in which the clock signal is positively used at the time of reading data to speed up memory access.

[0010]

A semiconductor integrated circuit device according to the present invention includes a plurality of memory cells and one of the memory cells.
An address register for fetching an address signal for selecting one of the memory cells in synchronization with a clock signal, a read current detecting means for detecting a read current from the memory cell selected by the address signal, and a clock signal in synchronization with the clock signal. And a control means for controlling the read current.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.
FIG. 2 is a block diagram of an embodiment of the present invention. First, referring to FIG. 2, the address signal 201 is set in the address register 61 by a pair of complementary clock signals 112 and 113. The address signal set in the address register 61 is transferred from the line 202 to the RAM.
It is sent to the address buffer 62 of the macro 6 and used as the address signal of the RAM macro 6. The clock signals 112 and 113 are also supplied to the clock buffer 2 in the RAM macro 6.

Next, the circuit of FIG. 1 will be described. Transistors 51-54, resistors 57 and 58, memory cell 1
The part composed of is similar to the conventional example. That is,
The emitters of transistors 53 and 54 are connected to resistors 57 and 58 by lines 108 and 109, respectively.
The collectors of the transistors 53 and 54 are connected to the emitters of the transistors 51 and 52, respectively. The bases of transistors 51 and 52 are commonly connected by line 110 and the collectors are digit lines 101 and 1, respectively.
02 is connected.

The digit lines 101 and 102 are connected to the emitters of the transistors 11 and 12 included in the memory cell 1, respectively. The word line 109 is connected to the memory cell 1.

The output of the reference potential generating circuit 4 is connected to the base of the transistor 59 by the line 105. The collector of the transistor 59 is connected to the GND potential 104, and the emitter potential is connected to the line 111 in common with the base potentials of the transistors 53 and 54. Also, line 111
The anode side of the diode 55 is connected to. On the other hand, the cathode side is connected to the resistor 56 via the line 118. The other terminal of the resistor 56 is at VEE level 103
Connected with.

The clock buffer 2 receives clocks 112 and 113 as inputs, and its output 115 is coupled to the line 111 via the capacitor 3. Clocks 112 and 113 are connected to the bases of transistors 21 and 22, respectively. The emitters of transistors 21 and 22 are both line 11
It is connected by 6 to the collector of the transistor 23. The reference potential 114 is supplied to the base of the transistor 23, and the emitter is connected to the resistor 25 by the line 117. The other end of the resistor 25 is at VEE level 103
It is connected to the.

The collector of the transistor 21 is connected to the GND level 104. The collector of transistor 22 is connected to resistor 24 by line 115. Resistance 2
The other end of 4 is connected to the GND level 104.

A sense amplifier 8 is connected to the digit lines 101 and 102, performs current-voltage conversion in the digit lines 101 and 102, and outputs the read data from the outputs 120 and 121.

An embodiment of the present invention having the above construction will be further described. In addition, the configuration of the reference voltage generation circuit 4,
The internal configuration of the sense amplifier 8 and the internal configuration of the memory cell 1 are not essential features of the present invention, and thus the description thereof is omitted.

FIG. 3 shows a timing diagram of an embodiment of the present invention. The address 201 is set in the address register 61 by the clock 112 and the clock 113 () (). The timing to be set is the falling edge of the clock 112. It is assumed that the address 201 has a sufficient time margin with respect to the clocks 112 and 113. The read data is accessed by this address.

On the other hand, in the clock buffer 2, a constant current source is constituted by the transistor 23 and the resistor 25, and a so-called differential amplifier circuit in which the emitters of the transistors 21 and 22 are commonly connected is formed. That is, when the clock 112 is at high level and the clock 113 is at low level, the output line 115 is at low level, and conversely, the clock 112 is at low level and clock 1
When 13 is at the high level, the output line 115 is at the high level (in this case, the GND level). The waveform of line 115 is shown in FIG.

Memory cell 1, transistors 51-54,
The operation of the circuit composed of the resistors 57 and 58 is similar to that of the conventional example. That is, the output line 105 of the constant voltage generation circuit 4
Since the constant voltage dropped by the voltage between B and E of the transistor 57 is supplied to the line 111 from the level of, the circuit including the transistor 53 and the resistor 57 and the circuit including the transistor 54 and the resistor 58 constitutes a constant current source. ing.

Here, when the line 110 becomes high potential by the address input to the address buffer 62 in synchronization with the clocks 112 and 113, the transistors 51 and 5 are connected.
A read current flows from 2. At this time, when the word line 119 is brought to a high potential by this address, the memory cell 1 is selected and a read current flows from either the transistor 11 or 12.

This depends on the memory holding state of the memory cell 1. If, for example, the transistor 12 flows, one read current flows from the sense amplifier 8 through the digit line 101, and the other read current flows in the word. It flows from line 119 through transistor 12 and not from sense amplifier 8.

The sense amplifier 8 outputs a low level from the output 120 when the read current flows from the digit line 101, and outputs a high level when the read current does not flow. This relationship also applies to the digit line 102 and the output 121.

As described above, the constant voltage generating circuit 4, the transistor 59, the diode 55 and the resistor 56 constitute a constant voltage source, and the GND level 104 → the transistor 59.
A very small current path (about 100 μA) is formed between the diode 55, the resistor 56, and the VEE level 103, and the line 111 is supplied with the reference potential.

However, since the line 111 is coupled to the output line 115 of the clock buffer via the capacitor 3 as described in the configuration, this capacitive coupling causes
As shown in FIG. 3, the potential of the line 111 is the clock 112.
It fluctuates up and down in synchronization with.

Therefore, the read current flowing through the transistors 51 and 52 also increases or decreases in synchronization with the clock 112.
As shown in FIG. 3, the read current increases in synchronization with the falling edge of the clock 112 (portion a), and the read current decreases in synchronization with the rising edge (portion b). Since the read current immediately after the address is set in the register 61 by the clock 112 is larger than usual, as shown in FIG. 3, the sense amplifier 8 reacts faster than in the normal case not synchronized with the clock, and the read time is shortened. To be done.

On the other hand, when the read current decreases, the amplitude difference between the outputs 120 and 121 of the sense amplifier 8 becomes a little smaller than usual (portion c).

The transistor 59 is interposed between the constant voltage generating circuit 4 and the line 111 in order to speed up the reaction to capacitive coupling. Therefore, the transistor 5
9, the diode 55 should be small.

The rate of increase / decrease of the read current and its duration can be arbitrarily set by the potential difference generated in the resistor 24 and the capacitance value of the capacitor 3.

[0032]

As described above, according to the present invention,
Since the address register and the RAM macro are provided and the read current of the RAM macro is increased in synchronization with the clock for setting the address register, the access time can be shortened.

Since the read current is repeatedly increased and decreased in synchronization with the clock, the total power consumption does not increase. That is, by using the clock signal which has not been used until now in the RAM macro, there is an effect that the access time of the memory is shortened with the same power consumption.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention.

FIG. 2 is an overall block diagram of an embodiment of the present invention.

FIG. 3 is an operation time chart of the embodiment of the present invention.

FIG. 4 is an overall block diagram of a conventional example.

FIG. 5 is a specific circuit diagram of a conventional example.

[Explanation of symbols]

 1 Memory Cell 2 Clock Buffer 3 Capacity 4, 7 Reference Voltage Generation Circuit 6 RAM Macro 8 Sense Amplifier 11, 12 Memory Cell Transistor 51-54 Read Transistor 61 Address Register 101, 102 Digit Line 119 Word Line 112, 113 Clock Signal ( Complementary) 201 Address signal

Claims (3)

[Claims] 1. A plurality of memory cells, an address register for taking in an address signal for selecting one of the memory cells in synchronization with a clock signal, and a read current from the memory cell selected by the address signal. And a control means for controlling the read current in synchronization with the clock signal. 2. The semiconductor integrated circuit device according to claim 1, wherein the control means has means for increasing the read current when the clock signal transits to the active state. 3. The read current detection means has a sense amplifier for detecting the current of a pair of digit lines of the memory cell, and the control means synchronizes the current of the pair of digit lines with the clock signal. The semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device is configured to be controlled by the following method.