JPH0772887B2 - Priority determination device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] This is a priority order determination method, and in the case where access requests to shared resources, which are resources shared by the system, are simultaneously issued from a plurality of processing devices, a single processing device is provided to each processing device. In order to solve the problem that when assigning one priority level and comparing the priority levels for access requests, it is not possible to give a clear priority to the processing request source that issues the processing request to each processing device. In addition, by configuring the priority of the access request to the shared resource according to the priority of the processing request source sent from each of the conflict processing devices, it is possible to give a clear priority to the processing request source. Becomes

[Industrial application field]

The present invention relates to an information processing system in which a plurality of processing devices that execute a processing request from a processing request source are operated in parallel, and particularly to a priority determination method of access requests to shared resources that are simultaneously generated from the processing devices.

For example, a plurality of input / output devices (corresponding to the processing request source,
When a plurality of processing requests are sent from the I / O device) to the processing device (e.g., equivalent to DMAC) in the direct storage access mode, the processing device determines the priority order and requests one processing request. Select and execute.

In executing the processing request, the processing device accesses the shared resource (for example, memory), exchanges a predetermined signal (data) with the shared resource, and executes the processing request.

When such processing execution is executed in parallel by a plurality of processing devices, a request for access to a memory (shared resource) also determines its priority by, for example, memory bus use right determination means in the memory (shared resource). Then, the usage right is given to one access request.

In order to improve the processing efficiency of the system, the priority order determination in such a case is required to be executed with a clearer priority, which also reflects the priority order of the processing request of the processing request source.

[Conventional technology]

FIG. 3 is a block diagram illustrating a conventional example, and FIG. 4 is a diagram illustrating an outline of an information processing system.

FIG. 4 is a schematic diagram of an information processing system showing the field of this example, and its configuration corresponds to, for example, a memory which is a shared resource in the information processing system, and the priority order of a plurality of access request MRQs for these is set. A shared resource 1 (0) to 1 (n) having a priority determination unit 11 and a plurality of processing requests RQ0a to RQnn are processed by the internal priority determination unit 21 in order of priority and time-division processing. 2 (0) to 2 (n).

For example, an access request MR to the predetermined shared resource 1 (i)
Each of the shared resources 1 (0) to 1 (n) is provided with a priority determination unit 11 to determine its priority when Q occurs simultaneously from a plurality of processing devices 2 (0) to 2 (n). Has been.

The priority determination in the priority determination unit 11 is performed by assigning a single priority level to each of the processing devices 2 (0) to 2 (n) and comparing them.

For example, the access request MRQ from the processing device 2 (0)
(0) is always the access request MR from the processing device 2 (1)
It is assumed that the priority level is assigned so as to give priority to Q (1).

In this case, for example, the processing request RQ0a, R is sent to the processing device 2 (0).
Q1a (However, the priority level is RQ0a> RQ1a
Assuming that the processing request RQ0b is given to the processing device 2 (1), the processing device 2 (0) performs the processing for the processing request RQ0a, and the processing device 2 (1) performs the processing request RQ0b in parallel.
Start processing for.

In this case, the processing request RQ1a has to wait until the processing of the processing request RQ0a is completed, so the processing start order is RQ0a →
Since RQ0b → RQ1a, RQ0b is processed with priority over RQ1a.

On the other hand, if the processing of RQ0b and RQ1a is performed in parallel and the access request MRQ to one shared resource 1 (i) competes with each other, RQ1a is prioritized over RQ0b depending on the priority level.

FIG. 3 is a diagram for explaining the detailed example described above. In this figure, the shared resource 1 (i) is a memory and a DMA data bus (b), the processing devices 2 (0) and 2 (1) are DMACs, and the processing request sources are I / O devices 3a (0) to 3a (3). ), 3b (0) to 3b (3).

In order to access the memory 1 (i) by DMA, it is necessary to obtain the right to use the memory bus (a) and the DMA data bus (b). And the DMA data bus usage right decision circuit 11b are provided in the priority decision unit 11.

Also, the priority of the processing requests from the I / O devices 3a (0) to 3a (3), 3b (0) to 3b (3) is determined by DMAC2 (0), 2 (1).
It is carried out by the priority determination unit 21 within.

The access requests from the DMAC2 (0), 2 (1) to the memory 1 (i) and the DMA data bus (b) are access requests MRQa and MRQb to the memory bus (a) and access to the DMA data bus (b). This is done by request DBRQa, DBRQb. As a permission response signal for this access, MGR
It is responded with a, MGRb and DBGRa, DBGRb.

Further, the memory bus usage right decision circuit 11a transmits an access request via NOR1, and the decision of the access permission is NOT1, AND1,
It is performed by a logic circuit composed of AND2, FF1 and FF2.

Furthermore, the determination by the DMA data bus usage right determination circuit 11b is NO.
It is performed by a logic circuit composed of T2, AND3, AND4, FF3, FF4.

[Problems to be solved by the invention]

In the case of access request processing to the shared resource 1 (i) (memory) as described above, processing request sources (I / O devices 3a (0) to 3
In any case, a clear priority cannot be attached to a (3), 3b (0) to 3b (3).

That is, the shared resource 1 from the processing devices 2 (0), 2 (1)
(I) The priority of the processing request from the processing request source depends on the access request status to the (memory).

[Means for solving problems]

 FIG. 1 shows a block diagram illustrating the principle of the present invention.

According to the present invention, the above problem is caused by one processing device 2 (n).
Of the plurality of processing requests RQ (0) to RQ (n) are determined by the first priority determining means 22 inside the processing device 2 (n), and the selected one processing request RQ (n).
In the information processing device capable of operating a plurality of the processing devices 2 (0) to 2 (n) in parallel, the one processing request RQ (n selected by the first priority determination means 22. ), The first priority determining means 22 determines the priority order among the plurality of access request MRQs generated from the respective processing devices 2 (0) to 2 (n) with respect to the shared resource 10 (n). The second priority judgment means 12 for judging in response to the selection result is provided, and priority is given to a plurality of access request MRQs generated from the processing devices 2 (0) to 2 (n) to the shared resource 10 (n). It is achieved by a priority determination device characterized by determining a ranking.

[Action]

Access request for shared resources 10 (0) to 10 (n)
The priority of the shared resource 10 (0) to 10 (n) is determined according to the processing request source code which is sent from each of the processing devices 2 (0) to 2 (n) with which the MRQ competes and whose processing execution is selected. With such a configuration, it becomes possible to always give a clear priority to the processing request source.

〔Example〕

The gist of the present invention will be specifically described below with reference to the embodiments shown in FIGS.

FIG. 2 shows a block diagram illustrating an embodiment of the present invention.
The same reference numerals denote the same objects throughout the drawings.

FIG. 2 shows shared resources 10 (0) to 10 (n) as described above.
Is a memory and a DMA data bus (b), the processing request source is the I / O device 3a (0) to 3a (3), 3b (0) to 3b (3), and the memory 10 (0) to 10 (n) Is to be accessed by DMA.

The configuration of the priority determination unit 12 shown in the embodiment of FIG. 2 has the same function as that described with reference to FIG.
A memory bus use right decision circuit 12a consisting of 1,2, AND1,2, FF1, FF2 and one NOR1, NOT1 and a function similar to that described in FIG.
DMA data bus usage right decision circuit 12b consisting of 3,4, AND3, 4, FF3, FF4 and one NOT2, and I / O devices 3a (0) to 3a (3), 3b (0) which are processing request sources
˜3b (3) (shown in FIG. 3) sub-channel (composed of four in this embodiment) identifiers (ID) a, b are encoded (for example, if DMA request 0a (0b)) 00 ₂ ", DMA request 3a (3
b) If "11 _2") were comprises a comparator 12c which compares what is constructed.

I / O devices 3a (0) to 3a for DMAC2 (0) and 2 (1)
DMA processing requests 0a to 3a, 0 from (3), 3b (0) to 3b (3)
b to 3b are controlled by time division, and the response to this is a DMA response
It is given by 0a to 3a and 0b to 3b.

Further, each I / O device 3a (0) to 3a (3), 3b in this embodiment
DMA processing request 0 from (0) to 3b (3) (shown in FIG. 3)
The priorities of a to 3a and 0b to 3b are 0a>0b>1a>1b> 2a.
>2b>3a> 3b.

Pre-Priority Determining Unit 22 in DMAC2 (0), 2 (1)
Selects one of the DMA processing requests 0a to 3a and 0b to 3b (0a
>1a>2a> 3a or 0b>1b>2b> 3b).

The comparator 12c compares the values of the identifiers (ID) a and b of the sub-channels selected by the DMAC2 (0) and 2 (1) with each other, and IDa ≧ ID
b, that is, when the transfer of the sub-channel being processed by DMAC2 (0) has a higher priority than that of DMAC2 (1), the memory bus usage right decision circuit 12a with the higher priority is sent via NOT1 and NOT2. And to the OR1,3 of the DMA data bus usage right decision circuit 12b.

When the number of parallel processes of DMAC2 (0), 2 (1) is two, the comparator 12c of the identifiers (ID) a, b is sufficient for one comparator, but when the number of parallel processes is three or more, the shared access is made. It is necessary to compare the identifier (ID) for each resource (memory).

Also, DMAC2 (0) and 2 (1) are shared resources, memory 1
0 (i) and I / O devices 3a (0) to 3a (3), 3b (0) to 3b
In order to control the data transfer with (3) by DMA, the interface with the memory 10 (i) (memory bus (a)) and the I / O devices 3a (0) to 3a (3), 3b. (0) ~ 3b
(3) is connected to a DMA data bus (b) for transmitting and receiving data.

Further, since other access devices (not shown) are connected to the memory bus (a), the priority with them is also determined.

Memory bus use request MRQa, MR from DMAC2 (0), 2 (1)
Qb and DMA data bus use request DBRQa, b are sent out, and their permission response signals MGRa, b, DBGRa, b are received from the memory bus use right decision circuit 12a and the DMA data bus use right decision circuit 12b, respectively.

The memory bus use right decision circuit 12a decides which DMAC2 (0), 2 (1) can use the bus during memory access by DMA. If only one of the memory bus use requests MRQa, MRQb is on. , Give permission signal MGRa, b to that person.

When the two memory bus use requests MRQa and MRQb are both on, the permission response signal MGRa, b is given to the one selected by comparing IDa and IDb. The DMA data bus right-of-use determination circuit 1
In the case of 2b, the same priority selection is performed.

As described above, when the processing devices 2 (0) and 2 (1) are multiplexed, various derived access requests for executing the main processing request reflect the priority of the main processing request. It is possible to give a clear priority to the processing request source.

〔The invention's effect〕

According to the present invention as described above, it is possible to give a clear priority to a processing request source.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention, FIG. 2 is a block diagram illustrating an embodiment of the present invention, FIG. 3 is a block diagram illustrating a conventional example, and FIG. 4 is an outline of an information processing system. And FIG. In the figure, 1 (0) to 1 (n), 10 (0) to 10 (n) are shared resources (memory), 2 (0) to 2 (n) are processing devices, and 3a (0) to 3a (3). ), 3b (0) to 3b (3) are I / O devices, 11,12,21,22 are priority determination sections, 11a and 12a are memory bus use right determination circuits, and 11b and 12b are DMA data bus use right determinations. A circuit, 12c is a comparator, respectively.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Ryona Tanigawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited (56) References JP 61-138352 (JP, A) JP 55- 56221 (JP, A)

Claims (1)

[Claims] 1. A priority of a plurality of processing requests (RQ (0) to RQ (n)) for one processing device (2 (n)) is set to a first priority inside the processing device (2 (n)). The one processing request (RQ selected by the determination means (22) is selected.
(N)) to execute the processing device (2 (0) to 2 (2))
In an information processing device capable of operating a plurality of (n)) in parallel, in order to execute the one processing request (RQ (n)) selected by the first priority determining means (22),
A plurality of access requests (MR) generated from the processing devices (2 (0) to 2 (n)) to the shared resource (10 (n))
Second priority judging means (12) for judging the priority order among Q) by receiving the ID added by the first priority judging means (22) is provided, and each processing device (2 (0)-
2 (n)) to determine a priority among a plurality of access requests (MRQ) generated from a shared resource (10 (n)).