JPH1049479A - Master device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a master device which serves as a bus master to perform the DMA(direct memory access) transfer of two data to an external bus and also reduces the interrupt notification frequency to the external bus. SOLUTION: The DMA transfer data are allocated to the DMA transfer parts 101 and 102. When the using right of an external bus is given to a device, a DMA selection part 104 selects one of both parts 101 and 102 to instruct it to perform the DMA transfer of data. At the same time, the part 104 compares the remaining transfer sizes of the parts 101 and 102 with each other and selects one of both parts 101 and 102 that has a larger remaining transfer size. An interrupt control part 105 notifies the external bus of an interrupt when both parts 101 and 102 end the transfer of allocated data respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master device, and more particularly, to a master device connected to an external bus and acting as a bus master for the bus to perform DMA transfer.

[0002]

2. Description of the Related Art A bus master for an external bus,
A device that performs bus access independently of the PU is a master device. Direct memory access (DM) between the external bus and internal memory using a master device
A) By performing the transfer, the load on the CPU can be reduced.

FIG. 3 is a block diagram showing a configuration of a conventional master device. 3 includes a DMA transfer unit 301, a DMA transfer unit 302, and a memory 303. The device shown in FIG. 3 is connected to an external bus together with the CPU and other devices. However,
This external bus is a bus that allows a plurality of devices to access asynchronously.

[0004] DMA transfer unit 301 and DMA transfer unit 3
In a case 02, the data allocated to each of the external bus and the memory 303 is DMA-transferred, and when the transfer is completed, the completion of the transfer is notified to the external bus using an interrupt signal. The memory 303 is a storage medium from which data can be read / written.

The operation of the device shown in FIG. 3 for performing DMA transfer of two data will be described below. Here, the two data means continuous code strings stored at different positions in the memory space (the same applies to the following description). By designating an address in the memory space, one of the two data is assigned to the DMA transfer unit 301 and the other data is assigned to the DMA transfer unit 302.

[0006] When the right to use the external bus is given to the device shown in FIG.
One of the transfer unit 301 and the DMA transfer unit 302, for example, the DMA transfer unit 301 starts the DMA transfer of the allocated data. During transfer, if another device wants to access the external bus, the right to use the external bus is granted to the other device. At this time, the DMA transfer unit 301 interrupts the transfer before ending the DMA transfer of the assigned data.

When another device finishes accessing the external bus and the right to use the external bus is given to the device shown in FIG. 3 again, the DMA transfer unit 302 starts DMA transfer of the allocated data. . During transfer, if another device wants to access the external bus, the right to use the external bus is granted to the other device. At this time, the DMA transfer unit 302 suspends the transfer before ending the DMA transfer of the allocated data.

When another device terminates the access to the external bus and is given the right to use the external bus again to the device in FIG. 3, the DMA transfer unit 301 and the DMA transfer unit 3
02, for example, the DMA transfer unit 301 starts the DMA transfer of the remaining data excluding the transferred data among the allocated data. Thereafter, each time the right to use the external bus is given to the device in FIG.
And one of the DMA transfer units 302 sequentially DMA-transfers the remaining data excluding the transferred data of the data allocated to each.

When the transfer of the allocated data is completed, each of the DMA transfer unit 301 and the DMA transfer unit 302 notifies the external bus of the end of the transfer using an interrupt signal. Then, the CPU connected to the external bus
Performs predetermined interrupt processing.

[0010]

As described above, in the device of FIG. 3, when two data are DMA-transferred,
Each of the MA transfer unit 301 and the DMA transfer unit 302 issues an interrupt notification when the transfer of the data allocated to itself is completed. Therefore, the DMA transfer unit 30
1 and the DMA transfer unit 302 perform interrupt notification at different timings, and the CPU needs to perform an interrupt process each time the DMA transfer unit 301 and the DMA transfer unit 302 complete the transfer.

In the device shown in FIG. 3, when one data is DMA-transferred, the data is transferred to the DMA transfer unit 30.
1 or the DMA transfer unit 302. At that time, the DMA transfer unit (301 or 302)
Each time the device of FIG. 3 is given the right to use the external bus,
The data is sequentially transferred, but every time the transfer is interrupted and then restarted, it is necessary to perform processing for address calculation and buffer management, so that there is a problem that the transfer takes time.

Accordingly, an object of the present invention is to provide a master which is connected to an external bus, acts as a bus master for the external bus, DMA-transfers a plurality of data, and notifies the external bus of an interrupt less frequently. Is to provide a device.

Another object of the present invention is to provide a case where one data is DMA-transferred in the master device.
It is to shorten the time required for the transfer.

[0014]

A first aspect of the present invention is a master device connected to an external bus, acting as a bus master for the bus, and performing direct memory access (DMA) transfer. A plurality of DMAs to which data to be transferred are assigned, respectively, and the assigned data are DMA-transferred according to an instruction.
Each time the transfer means and the right to use the external bus are given, one of the plurality of DMA transfer means that performs the DMA transfer is determined based on the remaining data amount of the data allocated to each of the transfer means excluding the transferred data. Select and direct transfer DM
A selection means and interrupt control means for detecting that the transfer of the assigned data has been completed by each of the plurality of DMA transfer means and notifying the external bus of an interrupt.

As described above, in the first invention, a plurality of D
Data to be transferred is assigned to the MA transfer unit in advance. Each time the right to use the external bus is given, the DMA selecting means selects one of the plurality of DMA transfer means.
A DMA transfer is selected based on the remaining data amount of the data allocated to each of the DMAs except for the transferred data, and the transfer is instructed. The DMA transfer means instructed to transfer DMA-transfers the remaining data of the data allocated to itself except for the transferred data. The interrupt control unit detects that each of the plurality of DMA transfer units has finished transferring the assigned data, and notifies the external bus of the interrupt.

As described above, each time the right to use the external bus is given, the channel to be transferred among the plurality of DMA channels is changed to the remaining data amount excluding the transferred portion of the data allocated to each channel. , It is possible to manage the timing of terminating the transfer of the data allocated to each channel.

According to a second aspect, in the first aspect, the DM
The A selecting means is characterized by selecting, from the plurality of DMA transfer means, the one having the largest amount of remaining data excluding the transferred data among the data allocated to each of the plurality of DMA transfer means.

Thus, the timings at which the channels end the data transfer can be brought closer to each other.

The third invention is the second invention, wherein the DM
The A selection means holds a predetermined threshold value, and when the difference between the data amounts of the data allocated to the plurality of DMA transfer means, excluding the transferred data, is equal to or greater than the threshold value. Is characterized in that selection is made irrespective of the amount of remaining data.

This prevents a channel having a small remaining data amount from being selected for a long time when the difference between the remaining data amounts of the data allocated to each channel excluding the transferred data is relatively large. Can be.

In a fourth aspect based on the second aspect, the interrupt control means notifies the interrupt when it detects that at least two of the plurality of DMA transfer means have completed the transfer. It is characterized by:

As described above, even if one channel ends the transfer of the assigned data, the interrupt is not notified at that time, and the interrupt is notified at the time when the other at least one channel ends the transfer. I do. As a result, the number of times of notifying an external bus of an interrupt can be further reduced.

In a fifth aspect based on the third aspect, the interrupt control means holds a threshold value similar to that held by the DMA selection means and is assigned to each of the plurality of DMA transfer means. If the difference in the remaining data amount of the transferred data excluding the transferred data is smaller than the threshold value, at least two D
When the MA transfer means detects that the transfer has been completed,
Notify the interrupt, and if it is more than the threshold,
Each time a plurality of DMA transfer means detects that the transfer is completed, an interrupt is notified.

As described above, when the difference between the data amounts of the data allocated to the respective channels, excluding the transferred data, is relatively small, even if one channel has finished transferring the allocated data. , The interrupt is not notified at that time, and the interrupt is notified when at least one other channel has completed the transfer.If the difference between the remaining data amounts is relatively large, each channel ends the transfer. Every time it does, it notifies the interruption. As a result, the number of times of notifying an external bus of an interrupt can be reduced, and
When the difference between the remaining data amounts is relatively large, it is possible to prevent the interruption from being notified for a long time after one channel ends the transfer.

In a sixth aspect based on the first to fifth aspects, one data is divided into a plurality of data,
The apparatus further includes DMA division means for assigning to each of the MA transfer means.

As described above, in the sixth invention, one data to be transferred is divided into a plurality of data by the DMA dividing means, and the divided data are respectively assigned to the plurality of DMA transfer means. In the case of DMA transfer of one data, one of the plurality of channels sequentially transfers the data every time the right to use the external bus is given. Therefore, the channel for transferring the data needs to perform processing for address calculation and buffer management every time the transfer is interrupted and then restarted. Therefore, by dividing the data into a plurality of data and performing DMA transfer on a plurality of channels, while one channel is DMA-transferring certain data obtained by division, other channels are
Processing for address calculation and buffer management when transferring other data obtained by division can be performed in advance. As a result, when one piece of data is DMA-transferred, the time required for the transfer can be reduced.

According to a seventh aspect, in the first to sixth aspects, the external bus is a PCI local bus.

On the PCI local bus, since a plurality of devices can perform asynchronous transfer, a remarkable effect can be obtained.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a master device according to the first embodiment of the present invention. The device shown in FIG.
1, a DMA transfer unit 102, a memory 103, a DMA selection unit 104, and an interrupt control unit 105. The device in FIG. 1 is connected to an external bus together with the CPU and other devices. However, this external bus is a bus that can be accessed asynchronously by a plurality of devices.

DMA transfer unit 101 and DMA transfer unit 1
02 DMA-transfers data allocated to itself between the external bus and the memory 103. Memory 1
03 is a storage medium from which data can be read / written. Each time the device of FIG. 1 is given the right to use the external bus, the DMA selection unit 104
1 and the DMA transfer unit 102 that performs the DMA transfer are selected and the transfer is instructed.

At this time, the DMA selection unit 104 compares the data amounts of the data allocated to the DMA transfer unit 101 and the DMA transfer unit 102 other than the transferred data (hereinafter, the remaining transfer size) with each other. The DMA transfer unit (101 or 1) having the larger remaining transfer size.
02) is selected. When both the DMA transfer unit 101 and the DMA transfer unit 102 complete the transfer of the assigned data, the interrupt control unit 105 notifies the external bus of the end of the transfer using the interrupt signal.

The operation of the device shown in FIG. 1 for DMA transfer of two data will be described below. Data to be DMA-transferred are assigned to the DMA transfer units 101 and 102 in the same manner as in the above-described conventional example.
02 respectively assume that a part of the allocated data has already been transferred. At this time, the DMA selection unit 10
4 is a DMA transfer unit 101 and a DMA transfer unit 102
When the device of FIG. 1 is given the right to use the external bus, these remaining transfer sizes are compared with each other.

When the remaining transfer size of the DMA transfer unit 101 is larger, the DMA selection unit 104
01, and instructs DMA transfer of the remaining data of the allocated data excluding the transferred data.
If the remaining transfer size of the transfer unit 102 is larger,
It instructs the DMA transfer unit 102 to perform DMA transfer of the remaining data of the allocated data excluding the transferred data. In response to the instruction, the DMA transfer unit (101 or 102) starts the DMA transfer of the remaining data of the allocated data excluding the transferred data.

While the DMA transfer unit (101 or 102) is performing DMA transfer of the remaining data, if the right to use the external bus is given to another device, the DMA transfer unit (101 or 1)
02) temporarily suspends the transfer. Then, when another device finishes accessing the external bus and the device of FIG. 3 is given the right to use the external bus again, the DMA selecting unit 104 sets the DMA transfer unit 101 and the DMA transfer unit 10
2 are compared with each other. Thereafter, the device of FIG. 1 repeats the same operation as described above.

The interrupt control unit 105 controls the DMA transfer unit 1
01 and the operation of the DMA transfer unit 102.
When both the DMA transfer unit 101 and the DMA transfer unit 102 complete the transfer of the assigned data, they notify the external bus of the end of the transfer using an interrupt signal. Then, the CPU connected to the external bus performs a predetermined interrupt process.

As described above, in this embodiment, every time the right to use the external bus is given to the device shown in FIG.
Among the MA transfer units (101 and 102), the DMA transfer unit (101 and 102)
Each DM is selected based on the remaining data amount excluding the transferred amount of the data allocated to each DM.
The timing at which the A transfer units (101 and 102) end the transfer of the data assigned to each can be managed.

Further, by selecting one of the two DMA transfer units (101 and 102) having the larger remaining transfer size, each DMA transfer unit (101 and 10) is selected.
2), the timings for terminating the transfer of the allocated data can be brought closer to each other.

Further, even if one of the DMA transfer units (101 or 102) completes the transfer of the assigned data, the interrupt control unit 105 does not notify the interrupt at that time and the other DMA transfer unit (101 or 102) 102 or 101)
By notifying the interrupt at the time when the transfer is completed, the number of times of notifying the interrupt to the external bus can be further reduced.

In this embodiment, two data are stored in D
Although the case of performing the MA transfer has been described, instead, three or more DMA transfer units are provided, and the DMA selection unit 104 selects the DMA having the largest remaining transfer size among the three or more DMA transfer units. The transfer unit is selected, and the interrupt control unit 105 has at least two DMAs.
By notifying an interrupt when the transfer unit has completed the transfer, even when DMA transfer of three or more data is performed,
The number of times of notifying an external bus of an interrupt can be further reduced.

In this embodiment, two DMAs are used.
When the difference between the remaining transfer sizes of the transfer units (101 and 102) is relatively large, the DMA transfer unit (101 or 102) having the smaller remaining transfer size is not selected for a long time, so that inconvenience such as delay may occur. May occur.
The second embodiment described below relates to a master device that can prevent such inconvenience.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. Since the configuration of the master device according to the present embodiment is the same as that of FIG. 1, FIG. 1 will be used in the following description. The DMA selection unit 104 has a predetermined threshold value, and compares the difference between the remaining transfer sizes of the DMA transfer unit 101 and the DMA transfer unit 102 with this threshold value. If the difference between the remaining transfer sizes is smaller than this threshold as a result of the comparison, the DMA selecting unit 104 selects the DMA transfer unit 101 or the DMA transfer unit 102 with the larger remaining transfer size, and selects the remaining transfer size. If the size difference is greater than or equal to this threshold, either one is arbitrarily selected.

The interrupt control unit 105 includes a DMA selection unit 1
04 has a threshold value similar to the threshold value, and compares the difference between the remaining transfer sizes of the DMA transfer units 101 and 102 with this threshold value. When the difference between the remaining transfer sizes is smaller than the threshold value as a result of the comparison, the interrupt control unit 105 determines whether the DMA transfer unit 101 and the DMA transfer unit 102 have finished transferring the assigned data. When an interrupt is notified to the bus and the difference between the remaining transfer sizes is equal to or larger than the threshold value, the DMA transfer unit 101 and the DMA transfer unit 102 generate an interrupt each time the transfer of the assigned data ends. Notice. Other components perform operations similar to those in the first embodiment.

The operation of the device shown in FIG. 1 for DMA transfer of two data will be described below. Data to be DMA-transferred is allocated to the DMA transfer unit 101 and the DMA transfer unit 102 in the same manner as in the first embodiment.
It is assumed that each of the transfer units 102 has already transferred a part of the allocated data. At this time, the DMA selection unit 104 recognizes the remaining transfer size of each of the DMA transfer unit 101 and the DMA transfer unit 102,
When the device of FIG. 1 is given the right to use the external bus, first, the difference between these remaining transfer sizes is compared with the retained threshold value.

If the difference between the remaining transfer sizes is smaller than the threshold value, the DMA selection unit 104
01 and the remaining transfer size of the DMA transfer unit 102 are compared with each other. Hereinafter, the operation of the device of FIG.
This is the same as that in the embodiment.

If the difference between the remaining transfer sizes is equal to or larger than the threshold value, the DMA selecting unit 104
And the DMA transfer unit 102 is arbitrarily selected to perform the transfer, and instructs the transfer. DM instructed to transfer
The A transfer unit (101 or 102) performs the DMA transfer of the remaining data of the data allocated to itself except the transferred data.
The transfer is started, and when the right to use the external bus is given to another device, the transfer is suspended.

When another device terminates the access to the external bus and the right to use the external bus is given to the device in FIG. 1 again, the DMA selecting unit 104
The difference between the remaining transfer sizes of 1 and the DMA transfer unit 102 is compared with the stored threshold value. Thereafter, the device of FIG. 1 repeats the same operation as described above.

[0047] The interrupt control unit 105 controls the DMA selection unit 1
04 has a threshold value similar to the threshold value, and compares the difference between the remaining transfer sizes of the DMA transfer unit 101 and the DMA transfer unit 102 with this threshold value. When the difference between the remaining transfer sizes is smaller than the threshold value, the interrupt control unit 105 notifies the external bus of the interrupt when both the DMA transfer unit 101 and the DMA transfer unit 102 complete the transfer of the allocated data. I do.

If the difference between the remaining transfer sizes is equal to or larger than the threshold value, the interrupt control unit 105
1 and the DMA transfer unit 102 notify the external bus of an interrupt each time the transfer of the assigned data is completed. Then, the CPU connected to the external bus performs a predetermined interrupt process.

As described above, in this embodiment, a predetermined threshold value is set in the DMA selection unit 104. DMA
The selection unit 104 includes two DMA transfer units (101 and 1).
02), when the difference between the remaining transfer sizes is smaller than the threshold value, the DMA transfer unit (101 and 102) selects the one with the larger remaining transfer size to instruct the transfer, and issues the remaining transfer. If the difference between the sizes is equal to or greater than the threshold, the size is selected irrespective of the size of the remaining transfer size. Thereby, each DMA transfer unit (101 and 10)
2), the data transfer end timings can be approached to each other, and when the difference between the remaining transfer sizes of the DMA transfer units (101 and 102) is relatively large, the smaller the remaining transfer size is, It is possible to prevent the DMA transfer unit (101 or 102) from being not selected for a long time.

When the difference between the remaining transfer sizes of the two DMA transfer units (101 and 102) is smaller than the threshold value, the interrupt control unit 105 determines whether one of the DMA transfer units (101 or 102) Even when the transfer of the allocated data is completed, the interrupt is not notified at that time, and the interrupt is notified when the other DMA transfer unit (102 or 101) completes the transfer. On the other hand, if the difference between the remaining transfer sizes is equal to or larger than the threshold,
Each time the transfer unit (101 and 102) completes the transfer,
Signal an interrupt. As a result, the number of times of notifying an external bus of an interrupt can be reduced, and each DMA
When the difference between the remaining transfer sizes of the transfer units (101 and 102) is relatively large, it is possible to prevent the interrupt from being notified for a long time after one of the DMA transfer units (101 and 102) completes the transfer. .

In this embodiment, two data are stored in D
Although the case of performing MA transfer has been described, three or more D
MA transfer unit, and three or more data
MA transfer may be performed. However, in this case, D
The MA selection unit 104 compares the difference between the remaining transfer sizes of the three or more DMA transfer units with a threshold value, respectively. If all the remaining transfer size differences are smaller than the threshold value, Of the three or more DMA transfer units, the one with the largest remaining transfer size is selected and transfer is instructed. If the difference between any of the remaining transfer sizes is greater than or equal to the threshold value, the remaining transfer size is Choose regardless of size.

Further, the interrupt control unit 105 compares the difference between the remaining transfer sizes with the threshold value, and if all the difference between the remaining transfer sizes is smaller than the threshold value, at least two DMA transfer units At the end of the transfer, an interrupt is notified, and if the difference between any of the remaining transfer sizes is equal to or greater than the threshold, each DMA transfer unit
Each time the A transfer is completed, an interrupt is notified.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 11 is a block diagram illustrating a configuration of a master device according to a third embodiment of the present invention. The device of FIG.
Transfer unit 201, DMA transfer unit 202, memory 203, D
MA selection unit 204, interrupt control unit 205, and DMA
A dividing unit 206 is provided. In addition, the device of FIG.
It is connected to an external bus together with the CPU and other devices. However, this external bus is a bus that can be accessed asynchronously by a plurality of devices.

The DMA dividing unit 206 divides one data into two data, and
A is assigned to each of the A transfer units 202. That is, when one of the DMA transfer unit 201 and the DMA transfer unit 202 attempts to perform a DMA transfer of a continuous code string stored at a certain position in the memory space,
The DMA division unit 206 assigns a part of the code string to the DMA transfer unit 201 and assigns the rest to the DMA transfer unit 202 by designating addresses. Other components perform operations similar to those in the first embodiment.

The operation of the device shown in FIG. 2 for dividing one data into two and performing DMA transfer will be described below. When the right to use the external bus is given to the device in FIG. 2, the DMA dividing unit 206 divides one data to be transferred by either the DMA transfer unit 201 or the DMA transfer unit 202 into two data. , DMA transfer unit 201 and DMA transfer unit 202, respectively. However, in the present embodiment, the DMA dividing unit 206
Divides one piece of data into two pieces of data having substantially the same data amount. Hereinafter, the DMA transfer units 201 and D
The operations of the MA transfer unit 202 performing DMA transfer of the allocated data and the interrupt control unit 205 transmitting an interrupt signal are performed by the DMA transfer unit 101, the DMA transfer unit 102, and the interrupt control unit 1 in the first embodiment, respectively.
05.

As described above, in the present embodiment, one data to be transferred is divided by the DMA dividing unit 206 into two data and allocated to the two DMA transfer units (201 and 202). One data is DMA
When transferring, two DMA transfer units (201 and 20)
2) sequentially transfers the data each time the right to use the external bus is given to the device in FIG. Therefore, the DMA transfer unit (201 or 202) that transfers the data needs to perform processing for address calculation and buffer management every time the transfer is interrupted and restarted.

Therefore, the data is divided into two data, and the two DMA transfer units (201 and 202) perform DMA transfer alternately, whereby one DMA transfer unit (201 or 202) is divided. While one of the obtained data is being DMA-transferred, the other DMA transfer unit (202 or 201) performs an address calculation and a buffer management when transferring the other data obtained by division. Can be performed in advance. This allows
When one piece of data is DMA-transferred, the time required for the transfer can be reduced.

In this embodiment, the DMA division unit 20
6 divides one piece of data into two pieces of data having substantially the same data amount.
06 may divide one piece of data into two pieces of data having different data amounts. However, in this case, the DMA transfer unit 201 and the DMA transfer unit 202 transfer the assigned data by DMA, and the interrupt control unit 2
The operations performed by the DMA transfer unit 101 and the DMA transfer unit in the second embodiment are respectively performed by the DMA transfer unit 05 and the DMA transfer unit.
This is the same as that of the transfer unit 102 and the interrupt control unit 105.

In this embodiment, one data is divided into two data and two DMA transfer units (201 and 202) perform the DMA transfer.
An A transfer unit may be provided, one data may be divided into three or more data, and three or more DMA transfer units may perform the DMA transfer.

Each of the master devices shown in FIGS. 1 and 2 has a memory (103, 203).
Alternatively, the memory may be provided outside the master device, and the master device may not include the memory.

When the external bus to which the master device shown in FIGS. 1 and 2 is connected is a PCI local bus, a plurality of devices can perform asynchronous transfer on the PCI local bus, which is remarkable. The effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a master device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a master device according to a third embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a master device according to a conventional example.

[Explanation of symbols]

 101, 102, 201, 202 DMA transfer unit 103, 203 Memory 104, 204 DMA selection unit 105, 205 Interrupt control unit 206 DMA division unit

Claims (7)

[Claims] An external bus is connected to an external bus and serves as a bus master for the bus.
A) A master device that performs transfer, to which data to be transferred is assigned, a plurality of DMA transfer means for respectively transferring the assigned data by DMA according to an instruction, and a right to use an external bus is given. The plurality of DMAs
DMA transfer means for selecting one of the transfer means for performing the DMA transfer based on the remaining data amount excluding the transferred data of the data allocated to each of the transfer means, and instructing the transfer, A master device comprising: interrupt control means for detecting completion of transfer of assigned data, and notifying the external bus of an interrupt. 2. The method according to claim 1, wherein the DMA selection unit includes a plurality of the DMs.
2. The master device according to claim 1, wherein, among the A transfer units, a transfer unit that has the largest remaining data amount except for the transferred portion of the data allocated to each unit is selected. 3. The DMA selection means holds a predetermined threshold value, and the difference between the data amounts of the data allocated to the plurality of DMA transfer means, excluding the transferred data, is determined by the DMA threshold value. 3. The master device according to claim 2, wherein when the data amount is equal to or larger than the threshold value, the selection is made regardless of the remaining data amount. 4. The interrupt control means according to claim 1, wherein
3. The master device according to claim 2, wherein an interrupt is notified when it is detected that at least two of the MA transfer units have completed the transfer. 5. The interrupt control means holds a threshold value similar to the threshold value held by the DMA selection means, and stores a transfer amount of data assigned to each of the plurality of DMA transfer means. Is smaller than the threshold value, the plurality of DMAs
When it is detected that at least two of the DMA transfer means have completed the transfer, an interrupt is notified.
4. The master device according to claim 3, wherein an interrupt is notified each time the A transfer unit detects that the transfer has been completed. 6. A method in which one data is divided into a plurality of data and assigned to each of the plurality of DMA transfer means.
The master device according to claim 1, further comprising an MA dividing unit. 7. The master device according to claim 1, wherein said external bus is a PCI local bus.