JPH0772183A - Waveform data operation device - Google Patents

Abstract

PURPOSE:To cope with a higher frequency input signal when calculating RMS value, etc., using a DSP by obtaining waveform data after generating a sampling clock which is N times larger than the input signal in a PLL circuit. CONSTITUTION:A synchronous clock signal which is output from a waveform shaping circuit 12 of an input signal is divided by a dividing ratio of 1/M corresponding to the frequency of the input signal by a frequency divider 18, thus maintaining the input signal frequency to a PLL circuit 13 to be within a certain range and generating a specific sampling clock by the PLL circuit 13 without being affected by the frequency of input signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform data calculation device for calculating the current and voltage average values or effective values of measured input signals, power parameters, and the like. The present invention relates to a waveform data calculation device that can be performed.

[0002]

2. Description of the Related Art In order to measure the effective values of current and voltage, first, an input waveform is sampled in accordance with a predetermined sampling clock to obtain data for one cycle (or several cycles) of the input waveform, After that, the sampling is temporarily interrupted and the effective value is calculated to obtain the effective value.

In this method, with respect to the one for calculating several cycles of the input waveform, since the averaging process is performed, a highly accurate effective value can be obtained, and the calculation is performed after the data is once stored in the storage memory. If so, it can be evaluated in terms of the degree of freedom in the calculation processing method, but in any case, the effective value obtained is a value every few cycles, so the fluctuation waveform tends to be rough cut, and in real time. The effective value cannot be obtained continuously.

Therefore, DSP (Digital Sig)
1) of the input waveform using
FIG. 3 shows an example in which the effective value is calculated within a cycle and the value can be displayed in the next cycle.

According to this, the input signal to be measured is input to the waveform shaping circuit 12 after being amplified to a predetermined level by the input circuit 11, for example. The waveform shaping circuit 12 is composed of, for example, a zero-cross comparator, in which the input waveform is shaped as a rectangular-wave synchronous clock signal synchronized with its fundamental wave, and the PLL (Phase-LockedLo) of the next stage is formed.
Op) is input to the circuit 13.

The PLL circuit 13 receives the synchronous clock signal, generates a sampling clock having a frequency N times (for example, 512 times) synchronized with the synchronous clock signal, and supplies the same to the sample hold circuit 14.

As a result, the input and hold circuit 14 samples N points of data from one cycle of the input waveform. Then, after the data is converted into digital data by the A / D conversion circuit 15 at the next stage, the arithmetic processing means 16 including the DSP performs a predetermined arithmetic operation, and the arithmetic value is stored in the memory 17. .

[0008]

In this way, for example, the effective value for each cycle is obtained in real time. According to this method, the DSP 16 must perform the arithmetic processing within one cycle of the input signal. However, when the frequency of the input signal becomes high, there is a problem that the arithmetic processing cannot catch up.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and its structural feature is to provide a waveform shaping circuit for shaping an input waveform to generate a synchronous clock signal thereof. A PLL circuit which receives the synchronous clock signal and outputs a sampling clock signal having a frequency N times that of the synchronous clock signal, and A / which samples the input waveform based on the sampling clock signal from the PLL circuit and converts it into digital waveform data A waveform that includes a D conversion circuit and an arithmetic processing unit that performs a predetermined arithmetic processing on the waveform data, obtains n pieces of waveform data from at least one cycle of the input waveform, and calculates an effective value of the input waveform. In the data arithmetic unit, the frequency division is performed by multiplying the synchronous clock signal output from the waveform shaping circuit by 1 / M to be an input signal to the PLL circuit. When the frequency measurement circuit, the frequency division ratio of the frequency divider according to the frequency of the measured the input waveform at the same frequency measurement circuit for measuring the frequency of the input waveform 1
/ M is changed to control the input signal frequency to the PLL circuit within a fixed range.

[0010]

The input waveform is shown in FIG. 2. For example, the waveform in FIG. 2A is 100 Hz, and when this is used as a reference, the division ratio is 1/1. As a result, the input signal to the PLL circuit becomes 100 Hz.
A sampling clock having a frequency of N times (for example, 512 times) synchronized with the circuit is generated from the circuit, and 512 pieces of waveform data are sampled from one cycle (waveform) of the input waveform.

Next, as shown in FIG. 2B, the input signal is 20
At 0 Hz, the value of M is 2, that is, the division ratio is 1/2. According to this, the input waveform is 200 Hz, but since the input signal to the PLL circuit is 100 Hz,
From two cycles of the input waveform, 512 pieces of waveform data are sampled.

Similarly, an input signal of 600 is shown in FIG.
An example of Hz is shown, and in this case, the division ratio is 1/6 when M = 6, and 512 pieces of waveform data are sampled from within 6 cycles.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the waveform data arithmetic unit according to the present invention, in which the same components as those in FIG. 2 described above are designated by the same reference numerals.

This arithmetic unit measures the frequency of an input signal and a frequency divider 18 connected between the waveform shaping circuit 12 and the PLL circuit 13 in addition to the components shown in FIG. Frequency measuring circuit 19 and this frequency measuring circuit 19
CPU (central processing unit) 20 as a control means for changing the frequency division ratio of the frequency divider 18 based on the frequency measured in Step 1.

In this embodiment, the frequency measuring circuit 19
Although the frequency is measured directly from the input signal from the input circuit 11, the frequency may be measured from the synchronous clock signal output from the waveform shaping circuit 12. Further, for convenience of explanation, the CPU 20 uses the frequency divider 18
In order to change the frequency division ratio of the above, it is shown only for that, but it goes without saying that another CPU or the like may also be used.

The frequency division ratio 1 / M (where M is a positive integer) of the frequency divider 18 is set by the CPU 20 according to the frequency of the input signal measured by the frequency measuring circuit 19. In this example, the frequency division ratio can be switched for each frequency range.

For example, in the range of 50 Hz to 100 Hz, M = 1, the frequency division ratio is 1/1, and 200 H exceeds 100 Hz.
Up to z, M = 2 and the division ratio is 1/2.
.. is selected for each 0 Hz range.

Here, assuming that the PLL circuit 13 generates a sampling clock of, for example, 512 times that of the input signal, if the frequency division ratio is 1/1, 512 clocks from within one cycle of the input waveform. Will be sampled at equal intervals.

On the other hand, when the division ratio becomes 1/2,
512 pieces of waveform data are sampled at equal intervals from within two cycles of the input waveform. In short, when the frequency division ratio is 1 / M, 512 pieces of waveform data are sampled at equal intervals from M cycles of the input waveform. It will be.

In this way, the sampled waveform data is converted into digital data by the A / D conversion circuit 15, and the DSP 16 calculates the effective value in real time from the waveform data, and the value is stored in the memory. 17 and is displayed during the next waveform calculation period.

According to the present invention, the number of samples in one cycle is reduced except when the frequency division ratio is 1/1.
The input can be adapted to high frequencies. In addition,
Even if the number of samplings in one cycle is reduced in this way, the DSP 16 processes the waveform calculation within the one cycle. As a result, without zeroing the sample data,
It is possible to continuously perform arithmetic processing in real time.

[0022]

As described above, according to the present invention, the synchronous clock signal output from the waveform shaping circuit of the input signal is divided by the division ratio according to the frequency of the input signal, and the PLL is obtained. By keeping the frequency of the input signal to the circuit within a certain range, the DS
Since the waveform calculation period of P is within a certain range, it is possible to handle an input signal of high frequency.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a waveform data calculation device according to the present invention.

FIG. 2 is a waveform diagram for explaining the operation of the same embodiment.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 11 input circuit 12 waveform shaping circuit 13 PLL circuit 14 sample hold circuit 15 A / D conversion circuit 16 DSP 18 frequency divider 19 frequency measurement circuit 20 CPU

Claims (1)

[Claims] 1. A waveform shaping circuit for shaping an input waveform to generate a synchronizing clock signal thereof, a PLL circuit for receiving the synchronizing clock signal and outputting a sampling clock signal having a frequency N times that of the synchronizing clock signal, and the same PLL circuit. At least the input waveform is provided with an A / D conversion circuit for sampling the input waveform based on the sampling clock signal from the A / D converter and converting it into digital waveform data, and an arithmetic processing means for performing a predetermined arithmetic processing on the waveform data. 1 cycle to n
In a waveform data calculation device that obtains individual waveform data and calculates the effective value of the same input waveform, the synchronization clock signal output from the waveform shaping circuit is set to 1
/ M times the frequency divider that is used as the input signal to the PLL circuit, the frequency measuring circuit that measures the frequency of the input waveform, and the frequency corresponding to the frequency of the input waveform measured by the frequency measuring circuit. A waveform data arithmetic apparatus, comprising: a control means for changing the frequency division ratio 1 / M of the frequency divider to keep the frequency of an input signal to the PLL circuit within a certain range.