JPH08152488A - Time measuring device - Google Patents

Abstract

PURPOSE: To surely measure time between start time and end time of time measurement even if counting number of a counter is insufficient while at least either of the start time and the end time of the time measurement being an event occurrence time point, nearly matching with the rise or the fall of a clock signal at the time when a continuously occurring event time interval is measured. CONSTITUTION: A counter 22 repeatedly counts a clock signal of a specified frequency which a clock generator 20 generates, and the counted value is stored in a memory 14. A sine wave generator 24 generates a sine wave wherein three times of a clock signal cycle is made one cycle, and a phase shift circuit 26 produces a cosine wave of the same cycle. A/D converters 28, 30 convert the amplitude of the sine and cosine waves into a digital value at the time of event occurrence, which is stored in the memory 14. A processing circuit 32 finds a difference of the counted value of the counter 22 at the time of neighboring event occurrence, and gets a time between the times of the neighboring event occurrences from a phase angle for the sine wave at the time of each event occurrence found from the output of the A/D converters 28, 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a time measuring device, in particular
When the clock signal is counted by the counter and the time between multiple event occurrence points is measured, even if the clock signal is generated near the time measurement start point and the time measurement end point, which are the event occurrence points, the clock signal is generated. The present invention relates to an apparatus capable of accurately measuring a time interval between the start time and the end time of time measurement with a resolution higher than that determined by the cycle.

[0002]

2. Description of the Related Art The time interval between successive events, that is,
A clock signal and a counter are used to digitally measure the time between the start of time measurement and the end of time measurement. In this time measurement, first, the counter is reset to zero (zero is loaded into the counter) before the measurement is started, and the number of clocks of the clock signal generated between the time measurement start and the time measurement end is counted. By multiplying this count value by the clock period, the time between the measurement start time and measurement end time can be obtained.

By the way, the counter counts at the rising edge (or falling edge: hereinafter simply referred to as rising edge) of the clock signal. In addition, in general, the start time and end time of the measured time, which is the time when the event occurs, are not synchronized with the clock signal, so the start time and end time of these time measurements almost coincide with the rising edge of the clock signal. There is nothing to do. This state is shown in FIG.

In FIG. 2, waveform A shows a high level gate signal from time T1 at the start of time measurement to time T4 at the end of time measurement, and waveform B shows a clock signal. It should be noted that the waveform A can be generated by clocking a flip-flop with a pulse generated when an event occurs. The waveforms A and B are supplied to the AND gate, and the output signal is counted by the counter. The waveform C shows the rising portion of the clock signal B counted by the counter. Therefore, the count value of the counter is 6 in this case. This is time T
The time from 2 to time T3 is (6-1) × (clock cycle), but only the count value of the counter indicates the time between time T1 and T2 and the time T3 and T4.
The time between is unknown. Therefore, in general, in the measurement using the digital counter, the resolution is determined by the clock cycle, and the counter has an error of +/− 1 in the count value.

Recently, various high resolution time measuring devices have been proposed which can measure between time points T1 and T2 and between time points T3 and T4 of FIG. In the first proposal, a ramp signal is generated for a period equal to or longer than the clock signal period, and the amplitude of the ramp signal at the start of the measurement time (time T1) and the ramp signal at the time of the first clock signal generation (time T2) are calculated. Find the difference from the amplitude. Similarly, when the last clock signal is generated (time T
3) and the amplitude difference of the tilt signal at the end of the measurement time (time T4) is obtained. Corresponding these amplitude differences to time, that is, the phase of the clock signal B, between the time points T1 and T2 and the time point T
The time between 3 and T4 is determined to compensate for the above error time.

A second high-resolution measurement proposal is a delay circuit having a delay time that is gradually increased from the time of one-tenth of the cycle in units of less than the clock signal cycle, for example, one-tenth of the cycle. Are provided, and the clock signal is commonly supplied to these nine delay circuits. Therefore, the resolution of the clock signal can be equivalently multiplied by 10. By determining which delay circuit is closer to the output signal at the start and end of the measurement, as described above, between the time points T1 and T2 and the time point T2.
The time between 3 and T4 can be determined. The third proposal is a method using a sine wave and a cosine wave proposed by the applicant of the present application, which will be described later in detail as a part of the embodiments of the present invention.

[0007]

As described above, the time (corresponding to the phase of the clock signal) between the rising time of the clock signal and the start and end of the time measurement can be measured, but the following problems occur. is there. That is, as shown in FIG. 3, when the rising time (at the start of time measurement) and / or the falling time (at the end of time measurement) of the gate waveform A coincides with or almost coincides with the rising time of the clock signal B, these Whether or not the rising portion of the clock signal B at the time point passes through the AND gate becomes delicate. This is because the clock signal B exceeds or does not exceed the threshold value of the AND gate, a slight time lag, and a slight change in the threshold temperature change.

In such a case, at time T0 and / or time T1, the count of the clock signal by the counter becomes indefinite. Therefore, high-resolution time measurement is performed, and the time difference between the clock signal at the start and end of time measurement is measured. Even if the (phase difference) is obtained, it is unclear whether or not these time differences are the differences between the first and last counting times of the clock signal.

Further, in the device for continuously measuring the time interval at which each event occurs, the counter continuously counts the clock signal, stores the count value of the counter in the memory each time the event occurs, and stores the stored value. The time interval is calculated from the numerical difference and the clock cycle. Also in this device, similarly to the above, the difference between the time at which an event occurs (at the start and end of time measurement) and the time at which the clock signal rises cannot be measured. Further, when the event occurrence time point at the time measurement start time and / or the time measurement end time coincides with or almost coincides with the rising time point of the clock signal, whether or not the counter has counted the clock signal is delicate at these points. Therefore, the count value transferred to and stored in the storage means becomes inaccurate. Therefore, the calculated difference in stored value is also inaccurate.

Therefore, it is an object of the present invention that at least one of the time measurement start time and the time measurement end time at which an event occurs coincides with the counting portion (rising or falling) of the clock signal, and the counting is indefinite. Even if there is, it is to provide a time measuring device capable of surely measuring the time between the start and end of the time measurement.

[0011]

In the time measuring device of the present invention, the counter 22 counts the clock signal of the predetermined frequency generated by the clock generating means 20. Phase measuring means 2
4 to 30 measure the phase at the time measurement start time and the time measurement end time with M times (M is a number larger than 2) as the cycle of the clock signal as one cycle. The processing means 32 obtains the time between the time measurement start time and the measurement end time from the number of clocks counted by the counter between the time measurement start time and the time measurement end time and the phase at the time measurement start time and the time measurement end time measured by the phase measurement means. . At this time, the processing means corrects the number of clocks counted by the counter from the phase difference at the start and end of the time measurement measured by the phase measuring means, and also at the time between the start and end of the time measurement. Find the difference from the clock time.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a preferred embodiment of the present invention. Through the input terminal 10, the event signal is supplied to the data terminal D of the flip-flop 12 and the sampling terminals of the analog-digital (A / D) converters 28 and 30. This event signal is a pulse signal with a short pulse width that is generated each time an event occurs, and the rising time of this pulse signal is the event occurrence time. The present invention is an apparatus for measuring the time interval between the occurrence times of events. The clock generator 24 generates a clock signal whose frequency and duty factor are stable, and supplies the clock signal to the clock terminal C of the flip-flop 12, the clock terminal of the measuring counter 22, and the sine wave generator 24. . The frequency of the clock signal is determined by the resolution required to measure the time interval between the pulses of the event signal, and its period is shorter than the pulse width of the event signal. Further, the number of bits of the counter 22 is determined by the maximum measurement time of the measurement time intervals.

Flip-flop 12 produces a Q output signal which goes high in synchronization with the clock signal when an event signal is generated, ie when the event signal goes high. This Q output signal is
It goes low in synchronization with the clock signal. This Q output signal is transferred to the write control terminal W of the memory 14 which is a storage means.
And to the delay circuit 16. The Q output signal delayed by the delay circuit 16 for a minute time is supplied to the address counter 18
Supply to the clock terminal of. This address counter 1
8 counts the delayed Q output signal, and supplies the count value to the address terminal A of the memory 14 as an address signal.
On the other hand, the measurement counter 22 counts the clock signal from the clock generator 20 and supplies the count value to the first data terminal D1 of the memory 14.

The sine wave generator 24 generates a sine wave whose cycle is three times the cycle of the clock signal from the clock generator 20. The cycle of this sine wave may be longer than twice the clock cycle, but in this embodiment, it will be described as three times. The sine wave generator 24 divides the clock signal into ⅓, generates a pulse having an impact coefficient of 50%, and filters the pulse to convert it into a sine wave. The phase shift circuit 26 shifts the phase of the sine wave signal from the sine wave generator 20 by +90 degrees (or -270 degrees) or -90 degrees (or +270 degrees) to obtain a cosine wave signal.
In this embodiment, it is set to -90 degrees. Phase shift circuit 26
Can be realized by a filter or a delay circuit. This state is shown in FIG. In FIG. 6, a waveform B is a clock signal from the clock generator 20, a waveform D is a pulse signal obtained by dividing the clock signal into ⅓ in the sine wave generator 24, and a waveform W1 is a sine wave. The sine wave from the generator 24, and the waveform W2 is the cosine wave waveform from the phase shift circuit 26.

The A / D converter 28 receives the sine wave signal from the sine wave generator 24 at its input terminal, samples this sine wave signal at each time when the event signal supplied to the sampling terminal is generated, It is converted into a digital signal and supplied to the second data terminal D2 of the memory 14. The A / D converter 30 is
The cosine wave signal from the phase shift circuit 26 is received at the input terminal, the cosine wave signal is sampled at every time when the event signal supplied to the sampling terminal is generated, converted into a digital signal, and stored in the third data of the memory 14. Supply to terminal D3. These sine wave generator 24, phase shift circuit 26, A / D converter 28
And 30 constitute the phase measuring means.

The processing circuit 32, which is a processing means, includes a memory 1
4, the count value of the counter 22 stored in the A / D converter 2
The digital signals from 8 and 30 are received, and the processing described later is performed to correct the clock count value of the counter 22 between the time measurement start time and the time measurement end time. Further, this processing circuit 32
Is the sum of the time between the clock signal generation time point immediately after the time measurement start and the time point immediately after that, and the time between the clock signal generation time point immediately before and the time measurement end time, and the time between the time measurement start time and the time measurement end time is calculated. Accurately seek. This processing circuit 32
Is a microprocessor, RO that stores the program
M, a RAM as a temporary storage device, and the like are included, and the processing result is output to an output device 36 such as a display or a print. An input device 34 such as a keyboard gives an instruction to start measurement.

FIGS. 4 and 7 to 9 are flow charts for explaining the operation of the first embodiment of the present invention. Such a procedure is stored in the ROM in the processing circuit 32, and the micro-circuit in the processing circuit 32 is stored. The processor does the work. When the time measuring device of FIG. 1 is set to the measuring mode by setting the input device 34, the address counter 18 is reset to zero. The measurement counter 22 counts the clock signal from the clock generator 20, returns to zero when the count reaches the maximum value, and repeats counting. On the other hand, the A / D converters 28 and 30 receive a sine wave signal and a cosine wave signal whose period is three times the clock period.

When the first pulse of the event signal is generated at the input terminal 10, the A / D converters 28 and 30 sample the amplitudes of the sine wave signal and cosine wave signal at that time and convert them into digital values. Immediately after that, the memory 14 enters the write state by the clock signal, so the memory 14 sets the address 0 to the count value N1 of the address counter 18,
The output digital value S1 of the A / D converter 28 and the output digital value C1 of the A / D converter 30 are stored. Shortly thereafter,
Since the address counter 18 counts the output signal of the delay circuit 16, the address signal advances by 1.

Similarly, when the second pulse of the event signal occurs, the memory 14 causes the address 1 to count N2 of the address counter 18 and the output digital values S2 and C2 of the A / D converters 28 and 30. Memorize Shortly thereafter,
The address signal advances by one. After that, the same operation is repeated. It should be noted that the interval between the event occurrence points is within the time determined by the product of the maximum count value of the counter 22 and the cycle of the clock signal. FIG. 5 shows the storage state of the memory 14 when such processing is performed.

The processing circuit 32 reads out the contents stored in the memory 14 after all the event signals are generated or during the above-mentioned operation period, and at each interval between the event occurrence points, that is, at the time measurement start time and Perform processing to determine the end time interval. First, in step 40 of FIG. 4, the processing circuit 32 determines from the output digital values S1 and C1 of the A / D converters 28 and 30 stored in the memory 14 the time Tm of the rising portion of the sine wave W1 from zero, That is, the phase θ1 (degrees) is obtained with reference to one rising edge of the pulse of the clock signal B, and the output digital values S2 and C2 of the A / D converter are obtained.
Then, a similar phase θ2 (degree) is obtained from

The method of obtaining θ1 in step 40 will be further described. As shown in FIG. 6, if a sampling pulse, which is an event signal, is generated at time Tn, the A / D converter 28 determines that the amplitude value S of the signal waveform W1.
1 is digitized, and the A / D converter 30 outputs the signal waveform W2
The amplitude value C1 of is digitized. Since the time point Tm between the point where the signal waveform W1 zero-crosses in the rising direction and the point where the signal waveform W2 has the maximum value is the reference point (phase 0 degree),
When the phase between the time points Tm and Tn is θ1, S1 = G * sin θ1 C1 = G * cos θ1. However, G is the amplitude value of the signal waveforms W1 and W2. From this relationship, Φ can be obtained by the following equation. θ1 = tan (-1) (S1 / C1) Note that tan (-1) means arc tangent (inverse tangent). The processing circuit 32 performs the above calculation according to the program stored in the ROM, and obtains the phase of the time point Tn with respect to the time point Tm. The method for obtaining θ2, θ3, ... Is the same.

In this embodiment, the sine wave W1 and the cosine wave W2
Is one cycle of the clock signal. The values of the phase angles θ1 and θ2 are both in the range of 0 degree or more and less than 360 degrees, and the phase difference between the time measurement end point and the time measurement start point is
(Θ2-θ1) + (360 × P) (where P is 0
And a positive integer). Therefore, when θ2-θ1 is positive, the phase difference θ = θ2-θ1 is set, and when θ2-θ1 is negative, θ = θ2-θ1 + 360 is set. Here, it is assumed that the count value of the counter 22 is indefinite as shown in FIG. 2 only when the rising time of the clock signal coincides with the event occurrence time.
In this case, when the phase difference θ between the phase angles θ2 and θ1 is 0 degree or more and less than 120 degrees, the difference N between the count values of the counter 22 is N.
The value N of 2-N1 is a value divisible by 3. When the phase difference θ is 120 degrees or more and less than 240 degrees, the count difference N
Is a number that is left by 1 when divided by 3, that is, a value that is divisible by 3 plus 1. Similarly, the phase difference θ
Is 240 degrees or more and less than 360 degrees, the count difference N is 3
When divided by, the number is a remainder of 2, that is, a value divisible by 3, minus 1.

That is, as shown in FIG. 10, the phase difference θ
Is in the range E (0 degrees or more and less than 120 degrees), even if the count difference of the counter 22 includes an indefinite value, it is sufficient to correct the count difference to the value closest to the count difference among the numbers divisible by 3. Phase difference θ
Is in the range F (120 degrees or more and less than 240 degrees), even if the count difference of the counter 22 includes an indefinite value, it is possible to correct the value that is closest to the count difference among the values obtained by adding 1 to the number divisible by 3 Good. Similarly, the phase difference θ is in the range G (240
If the counter difference is greater than or equal to 360 degrees and less than 360 degrees), even if the count difference of the counter 22 includes an indefinite value, it may be corrected to a value that is closest to the count difference among the values that are divisible by 3 by one. Within the time interval between the time measurement start point and the time measurement end point,
The fraction less than one clock cycle can be obtained from the phase difference θ because 120 degrees is one clock cycle.

The above has described the principle of the present invention, assuming that the count value of the counter 22 is indefinite only when the rising time of the clock signal coincides with the event occurrence time. However, in the actual digital circuit, The count value of the counter 22 becomes indefinite not only when the rising time of the clock signal and the event occurrence time match, but also when they almost match. Therefore,
In the embodiment of the present invention, the range that becomes indefinite is widely considered, and processing is performed as follows.

The process proceeds from step 40 to step 42 in FIG. 4 and the difference between N2 and N1 stored in the memory 14 is divided by 3 to obtain the remainder. When the value of N2 is smaller than the value of N1, that is, when the count value of the counter reaches the maximum value and returns to zero, it may be N2-N1 + (the maximum count value of the counter). In steps 44 and 46, the remainder is judged, and if the remainder is 0, the flow chart of FIG. 7 is proceeded, if the remainder is 1, the flow chart of FIG. 8 is proceeded to, and if the remainder is 2, the flow chart of FIG. 9 is proceeded to. .

In FIG. 7, in step 47, θ2-
It is determined whether θ1 is −180 degrees or less. This difference is -180
If the degree is less than or equal to (YES), the process proceeds to step 48, and the phase difference θ is set to θ2-θ1 + 360. Also, step 4
If the answer is 7 and no, the process proceeds to step 50 and θ2-θ1 is 1
Determine if it is greater than 80 degrees. If the determination result in step 50 is YES, the process proceeds to step 52, where θ is θ2-
θ1 to 360. If the determination step 50 is NO, the process proceeds to step 54, where θ is set to θ2-θ1. After obtaining the phase difference θ in step 48, 52 or 54, the process proceeds to step 56 and the time difference T between the time measurement start point and the time measurement end point is calculated by the formula (N2-N1) × TC + (θ / 360) × 3.
× TC Note that TC is the cycle of the clock signal.

In FIG. 8 where the remainder is 1, it is determined at step 58 whether θ2-θ1 is -60 degrees or less. If the result of this determination is YES, the routine proceeds to step 60, where the phase difference θ is set to θ2-θ1 + 360. Also, step 5
If the answer is 8 and no, the process proceeds to step 62 and θ2-θ1 is 3
It is determined whether it is greater than 00 degrees. If the determination result in step 62 is YES, the process proceeds to step 64, where θ is set to θ
2-θ1-360, and in the case of No, the routine proceeds to step 66, where θ is θ2-θ1. Step 60, 64 or 6
After calculating the phase difference θ in step 6, the process proceeds to step 68, and the time difference T between the time measurement start point and the time measurement end point is calculated by the formula (N2-N1).
-1) × TC + (θ / 360) × 3 × TC

In FIG. 9 where the remainder is 2, it is determined in step 70 whether θ2-θ1 is -300 degrees or less.
If the result of this determination is yes, then proceed to step 72,
The phase difference θ is θ2-θ1 + 360. If the determination result in step 70 is NO, the process proceeds to step 74, where θ
2- Determine if θ1 is greater than 60 degrees. If the determination result in step 74 is YES, the process proceeds to step 76, and θ is set to θ2-θ1 to 360. If the determination result is NO, the process proceeds to step 78 and θ is set to θ2-θ1. Step 72,
After obtaining the phase difference θ by 76 or 78, the process proceeds to step 80, and the time difference T between the time measurement start point and the time measurement end point is calculated by the formula (N2-N1 + 1) × TC + (θ / 360) × 3 × TC.
Ask by

The time difference T thus obtained is output to the output device 36.
To display or print. Next, the time difference between the second event and the third event is obtained from the count values N2 and N3 and the phase angles θ2 and θ3 in the same manner as described above. Thereafter, similar processing is sequentially performed.

In the above description, three times the clock cycle is the cycle of the sine wave, that is, the cycle for obtaining the phase angle, but four times the clock cycle may be the sine wave cycle. in this case,
The sine wave generator 24 divides the clock signal into quarters and converts it into a sine wave by filtering or the like. The processing circuit 32 divides N2-N1 which is the difference between the count values N2 and N1 of the counter 22 by 4 and, in accordance with the value of the remainder, according to the flowcharts shown in FIGS. Perform processing. That is, in step 82 of FIG. 11, the same processing as step 40 described above is performed, and in step 84 (N2-
Find the remainder of N1) / 4. Decision steps 86-90 determine the remainder and proceed to the flow charts of FIGS.
Steps 92 to 102 of FIG. 12 are flowcharts when the remainder is 0, and steps 104 to 114 of FIG. 13 are flowcharts when the remainder is 1. Also, step 1 of FIG.
16 to 126 are flow charts when the remainder is 2.
Steps 128 to 138 of 5 are flowcharts when the remainder is 3. These steps reduce the clock signal by a third
Since it is almost the same as the case where the frequency is divided into, the further description will be omitted.

Although the preferred embodiment of the present invention has been described above, various modifications can be made without departing from the spirit of the present invention. For example, when obtaining the phase angle, 1
In addition to 3 and 4 times the clock signal cycle, the cycle may be any multiple of 2 or more, such as 2.5 times. Further, the phase measuring means may be a circuit which samples the amplitude of the inclined wave and obtains the phase angle from the sampled value, in addition to the circuit for analog / digital conversion using the sine wave and cosine wave described above.

[0032]

As described above, according to the present invention, at least one of the start time and the end time of the time measurement substantially coincides with the counting portion (rising or falling) of the clock signal, and the counting is indefinite. Also, the time between the start and end of the time measurement can be reliably measured.

[Brief description of drawings]

FIG. 1 is a block diagram of a preferred embodiment of the present invention.

FIG. 2 is a waveform diagram illustrating the principle of time measurement.

FIG. 3 is a waveform diagram illustrating a problem of a conventional time measuring device.

FIG. 4 is a flowchart illustrating the operation of the embodiment of the present invention.

5 is a diagram showing stored contents of a memory used in the block diagram of FIG. 1. FIG.

FIG. 6 is a waveform diagram illustrating the operation of the present invention.

FIG. 7 is a flowchart illustrating the operation of the embodiment of the present invention.

FIG. 8 is a flowchart illustrating the operation of the embodiment of the present invention.

FIG. 9 is a flowchart illustrating the operation of the embodiment of the present invention.

FIG. 10 is a diagram illustrating the principle of the present invention.

FIG. 11 is a flowchart illustrating the operation of another embodiment of the present invention.

FIG. 12 is a flowchart illustrating the operation of another embodiment of the present invention.

FIG. 13 is a flowchart illustrating the operation of another embodiment of the present invention.

FIG. 14 is a flowchart illustrating the operation of another embodiment of the present invention.

FIG. 15 is a flowchart illustrating the operation of another embodiment of the present invention.

[Explanation of symbols]

 20 clock generating means 22 counter 24 sine wave generator constituting phase measuring means 26 phase shift circuit constituting phase measuring means 28, 30 A / D converter constituting phase measuring means 32 processing means

Claims (4)

[Claims] 1. A clock generation means for generating a clock signal of a predetermined frequency, a counter for counting the clock signal, and M times the cycle of the clock signal (M is a number greater than 2).
As a cycle, phase measuring means for measuring the phase at the time measurement start and time measurement end, the number of clocks counted by the counter between the time measurement start and the time measurement end, and the phase measurement means measuring A time measuring device comprising processing means for determining a time between the time measuring start and the time measuring end based on the phase at the time measuring start and the time measuring end. 2. The processing means corrects the number of clocks counted by the counter from the phase difference measured by the phase measuring means at the start of the time measurement and at the end of the time measurement. 1 time measuring device. 3. The processing means, based on the phase difference measured by the phase measuring means at the time measurement start and the time measurement end, the time between the time measurement start and the time measurement end and the correction. 3. The time measuring device according to claim 2, wherein the time difference is obtained according to the number of clocks. 4. The storage means further stores a count value of the counter at the time of starting the time measurement and at the end of the time measurement, wherein the processing means calculates the time from the difference between the count values stored in the storage means. 4. The time measuring device according to claim 3, wherein the number of clocks counted by the counter is calculated between the start of the measurement and the end of the time measurement.