JPH0771061B2 - Multiplex circuit clock transfer circuit - Google Patents

Description

DETAILED DESCRIPTION [Outline] First with synchronized high-order group clock and timing pulse
And a clock transfer circuit in the second multiplex circuit, the clock transfer circuit of the multiplex circuit capable of stably outputting the same data even when the phase of the clock supplied to the first and second multiplex circuits is changed. The low-order group data input by the inverter for inverting the low-order group clock generated by the first multiplexing circuit and the clock obtained by inverting the low-order group clock generated by the first multiplexing circuit for the purpose of After the columns are taken in, clock changing means is provided for changing the low-order group clocks generated by the first and second multiplexing circuits, respectively.

[Industrial application field]

The present invention relates to a clock transfer circuit in first and second multiplexing circuits having synchronized high-order group clocks and timing pulses.

In order to maintain the high reliability of the communication system, for example, the multiplex circuit of the transmission device is used, the spare and the redundant are used, and the
A method has widely been adopted in which the same data is output from a spare multiplex circuit so that a failure of one of the multiplex circuits or disconnection of the transmission path can be relieved by the output data of the other multiplex circuit.

When supplying a clock and a timing pulse from a clock source to such a duplicated multiplexing circuit, the same data may not be output if the phase changes for some reason in the process.

Therefore, there is a demand for a clock transfer circuit that absorbs phase variations of clock and timing pulses and stably outputs the same data.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating a time chart of the conventional example.

In the conventional example shown in FIG. 4, a multiplexing circuit 10A that multiplexes input low-order group data strings, an inverter (hereinafter referred to as INV) 31 that inverts a clock (denoted as CLK in the drawing) 31, and a multiplexing circuit 11 The flip-flop circuit (hereinafter referred to as FF circuit) 51 that outputs the higher-order group data multiplexed by the clock 1 as the higher-order group data 1 and the FF circuit that outputs the higher-order group data multiplexed by the multiplexing circuit 11 as the higher-order group data 2 by the clock 2. It consists of 52 and.

The operation of the above circuit will be described with reference to the time chart of FIG.

 It is a clock obtained by inverting clock 1 with INV31.

It is high-order group data that is multiplexed and output with an inverted clock of clock 1.

 It is clock 1 before being inverted.

The timing pulse 1 is for refreshing a pulse generator (not shown) in the multiplexing circuit 11.

The clock 2 and the timing pulse 2 have advanced phases.

The clock 2 and the timing pulse 2 are delayed in phase.

In order to output the shaded data in clock 2, the rising edge of clock 2 must be within the range within the broken line, and the allowable phase difference is less than 1 clock.

[Problems to be Solved by the Invention]

In the conventional example shown in FIG. 4 described above, when the clock phase changes by one clock or more, the same data cannot be output for both clocks and timing pulses.

An object of the present invention is to provide a clock transfer circuit for a multiplex circuit that can stably output the same data even when the phases of clocks supplied to the first and second multiplex circuits change.

[Means for Solving the Problems] FIG. 1 is a block diagram for explaining the principle of the present invention.

Reference numeral 10 in the principle block diagram of the present invention shown in FIG. 1 has a clock 1 and a timing pulse 1, divides the clock 1 to generate a low-order group clock, and multiplexes the input low-order group data. A first multiplexing circuit that outputs high-order group data 1, 20 has a clock 2 and a timing pulse 2, divides clock 2 to generate a low-order group clock, and multiplexes the input low-order group data. Is a second multiplex circuit that outputs high-order group data 2, and 30 is an INV that inverts the low-order group clock generated by the first multiplex circuit 10, and 40 is a low-level group clock that is generated by the first multiplex circuit. INV for next group clock
It is a clock transfer means for taking in the low-order group data sequence input by the inverted clock and then transferring to the low-order group clocks generated by the first and second multiplex circuits 10 and 20, respectively. This is a means for solving this problem.

[Action]

Clock 1 of the first multiplexing circuit 10 is divided to generate a low-order group clock.

This low-order group clock is inverted by INV30, and the low-order group data string is fetched by the inverted clock.

After the data is fetched by the inverted clock, the low-order group clocks respectively generated by the first and second multiplex circuits 10 and 20 are transferred to each other to absorb the phase fluctuation up to near the clock division ratio and to be the same. It becomes possible to output data.

〔Example〕

The gist of the present invention will be specifically described below with reference to the embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating an embodiment of the present invention, and FIG. 3 is a diagram illustrating a time chart of the embodiment of the present invention. The same reference numerals denote the same objects throughout the drawings.

The embodiment of the present invention shown in FIG. 2 corresponds to the first embodiment described in FIG.
The P / S conversion circuit 11 and the divide-by-4 circuit 12 are used as the multiplex circuit 10, and the P / S conversion circuit 21 and the divide-by-four circuit 2 are used as the second multiplex circuit 20.
2. This is an example in which three latch circuits 41 to 43 and INV30 are used as the clock transfer means.

The clock frequency division ratio in this embodiment is 4.

The operation of FIG. 2 will be described with reference to the time chart of FIG.

 It is clock 1.

 Timing pulse 1.

The clock 1'is divided by 4 by the divide-by-4 circuit 12.

 It is a low-order group timing pulse.

 It is an inverted clock 1'inverted from the clock 1 '.

It is a low-order group data string taken into the latch circuit 41 at the inverted clock 1 '. The data strings of the low-order group are input in parallel in four lines, but in the time chart and the figure, the two in the center are deleted and represented by two lines.

It is the output of the latch circuit 42 that latches the output of the latch circuit 41 at the clock 1 ', and is output at approximately the center of the output of the latch circuit 41.

Higher-order group data 1 obtained by multiplexing parallel data latched by the latch circuit 42 by the P / S conversion circuit 11.

The second multiplex circuit is 20 clocks 2 and timing pulses 2.

The clock 2'is divided by 4 by the divide-by-4 circuit 22.

 It is a low-order group timing pulse.

This is the output of the latch circuit 43 which latches the low-order group data string fetched by the latch circuit 41 at the inverted clock 1'at the clock 2 '.

The high-order group data 2 is obtained by multiplexing the parallel data latched by the latch circuit 43 by the P / S conversion circuit 21.

Although FIG. 3 shows a case where the clock 2 and the timing pulse 2 are advanced by 1.5 clocks with respect to the clock 1 and the timing pulse 1, the same is true when the clock 2 and the timing pulse 2 are delayed. Considering the setup time and hold time of the latch circuit used as the means 40, it is possible to absorb the phase fluctuations of less than 2 clocks in advance and delay, respectively, and less than 4 clocks in total.

In the embodiment shown in FIG. 3, the case where the multiplex circuit has two systems has been described, but by adding the latch circuit of the clock transfer means, it becomes possible to cope with the case of three or more systems.

With the above configuration, it is possible to absorb the phase fluctuation of the clock up to near the clock division ratio.

〔The invention's effect〕

According to the present invention as described above, a clock of a multiplex circuit that absorbs phase fluctuations of the clock up to near the division ratio and outputs the same data from two multiplex circuits by performing clock transfer with a low-order group clock. A transfer circuit can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention, FIG. 2 is a block diagram illustrating an embodiment of the present invention, FIG. 3 is a diagram illustrating a time chart of the embodiment of the present invention, and FIG. FIG. 5 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating a time chart of the conventional example. In the figure, 10 is a first multiplex circuit, 10A is a multiplex circuit, 11 and 21 are P / S conversion circuits, 12 and 22 are divide-by-four circuits, 20 is a second multiplex circuit, 30,
Reference numeral 31 is INV, 40 is a clock transfer means, 41 to 43 are latch circuits, and 51 and 52 are FF circuits, respectively.

Claims (1)

[Claims] 1. A first and second multiplex circuit (1) having synchronized high-order group clocks and timing pulses, and dividing a high-order group clock input thereto to generate a low-order group clock (1).
0, 20), the inverter (30) for inverting the low-order group clock generated by the first multiplex circuit (10), and the low-frequency circuit generated by the first multiplex circuit (10). The low-order group clock generated by the first and second multiplex circuits (10, 20) is taken in after the low-order group data string to be input is fetched by the clock obtained by inverting the next-group clock by the inverter (30). A clock transfer circuit of a multiplex circuit, comprising a clock transfer means (40) for transferring.