JPH03262223A - Clock transfer circuit for multiplex circuit - Google Patents

Abstract

PURPOSE:To output a same data stably even when the phase of a clock fed to a multiplex circuit is fluctuated by providing an inverter inverting the clock and a clock transfer means. CONSTITUTION:A multiplex circuit 10 frequency-divides a clock 1 by using a timing pulse 1 to form a low-order group clock and to multiplex an input low-order group data, thereby outputting a high-order group data 1. A multiplex circuit 10 frequency-divides a clock 2 similarly and outputs a high-order group data 1, an inverter 30 inverters a low-order group clock, the result is supplied to a clock transfer means 40 and transferred to a low-order group clock generated respectively by the multiplex circuits 10, 20. Through such constitution above, a phase fluctuation close to a clock frequency division ratio is absorbed and the same data is outputted.

Description

[Detailed description of the invention] [Summary] Synchronized high-order group clock, first clock with timing pulse
and a clock transfer circuit in a second multiplex circuit, which is capable of stably outputting the same data even when the phase of the clock supplied to the first and second multiplex circuits fluctuates. An inverter that inverts the low-order group clock generated by the first multiplex circuit, and a clock obtained by inverting the low-order group clock generated by the first multiplex circuit, are used to input low-order group data. The clock transfer means transfers to the low-order group clocks generated by the first and second multiplex circuits, respectively, after taking in the column.

[Industrial application field]

The present invention relates to a clock transfer circuit in first and second multiplex circuits having synchronized high-order group clocks and timing pulses.

In order to maintain high reliability of the communication system, for example, the multiplex circuits of the transmission equipment are duplicated into working and standby circuits.
A widely used method is to output the same data from a standby multiplex circuit, thereby resolving failures or transmission line breaks in one multiplex circuit using the output data from the other multiplex circuit.

When clocks and timing pulses are supplied from a clock source to such a duplicated multiplex circuit, if the phase changes for some reason during the process, it may become impossible to output the same data.

Therefore, there is a need for a clock transfer circuit that absorbs phase fluctuations in clocks and timing pulses and stably outputs the same data.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating a time chart of the conventional example.

The conventional example shown in FIG. 4 includes a multiplex circuit 10A that multiplexes an input low-order group data string, an inverter (hereinafter referred to as INV) 31 that inverts a clock (indicated as CLK in the figure) 1, and a multiplex circuit 11. A flip-flop circuit (hereinafter referred to as an FF circuit) 51 outputs the high-order group data multiplexed by a clock l as high-order group data l, and the high-order group data multiplexed by a multiplexing circuit 11,
FF circuit 5 outputs as high-order group data 2 with clock 2
It consists of 2.

The operation of the above circuit will be explained with reference to the time chart of FIG.

■ This is a clock obtained by inverting the clock l using INV31.

■ This is high-order group data that is multiplexed and output using an inverted clock of clock 1.

■ It is clock 1 before inversion.

(2) Timing pulse 1 for refreshing a pulse generator (not shown) in the multiplex circuit 11 (4).

■■ The phases of clock 2 and timing pulse 2 are advanced.

■■ The phases of clock 2 and timing pulse 2 are delayed.

In order to output the data in the shaded part of the clock 2, it is necessary that the rising edge of the clock 2 falls within the range within the broken line, and the allowable phase difference is less than 1 clock.

[Problem to be solved by the invention]

In the conventional example shown in FIG. 4 described above, when the phase of the clock fluctuates by more than one clock, it becomes impossible to output the same data for both clocks and timing pulses.

An object of the present invention is to provide a multiplex circuit clock transfer circuit that can stably output the same data even when the phase of the clock supplied to the first and second multiplex circuits fluctuates.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

10 in the principle block diagram of the present invention shown in FIG. 1 has a clock 1 and a timing pulse ■, divides the clock l to generate a low-order group clock, and multiplexes input low-order group data. A first multiplex circuit 20 outputs high-order group data l, and 20 has a clock 2 and a timing pulse 2, divides the clock 2 to generate a low-order group clock, and multiplexes the input low-order group data. 30 is an INV that inverts the low-order group clock generated by the first multiplex circuit 10, and 40 is an INV that inverts the low-order group clock generated by the first multiplex circuit 10. Next group clock I
A clock switching means for taking in a low-order group data string inputted with a clock inverted by NV, and then switching to a low-order group clock generated by the first and second multiplex circuits 1O120, and comprising such a means. This is a means to solve this problem.

[For production]

The clock 1 of the first multiplex circuit 10 is frequency-divided to generate a low-order group clock.

This low-order group clock is inverted by INV30, and the low-order group data string is taken in with the inverted clock.

After taking in data with an inverted clock, the first and second multiplex circuits 10 and 20 generate the respective low-order group clocks, thereby absorbing phase fluctuations up to the frequency division ratio of the clock and maintaining the same level. It becomes possible to output data.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating a time chart of an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG.
The multiplex circuit 10 includes a P/S conversion circuit 11 and a frequency divider circuit 12, the second multiplex circuit 20 includes a P/S converter circuit 21 and a frequency divider circuit 22, and the clock transfer means includes three latch circuits 41. -43, and INV30.

Note that the frequency division ratio of the clock in this embodiment is set to 4.

The operation shown in FIG. 2 will be explained with reference to the time chart shown in FIG.

■ Clock l.

■ Timing pulse 1.

(2) This is a clock 1' whose frequency is divided by 4 by the 4-frequency divider circuit 12.

■ It is a low-order group timing pulse.

■ It is an inverted clocked version of the clocked version.

(2) This is a low-order group data string taken into the latch circuit 41 using the inverted clock 1'. Four low-order group data strings are input in parallel, but in the time chart and figure, the central two are deleted and two are representative.

(2) This is the output of the latch circuit 42 which latches the output of the latch circuit 41 with clock 1', and is output at approximately the center of the output of the latch circuit 41.

■ High-order group data 1 obtained by multiplexing the parallel data latched in the latch circuit 42 by the P/S conversion circuit 11
It is.

(2) 0 Clock 2 and timing pulse 2 of the second multiplex circuit 20.

This is the clock 2' whose frequency is divided by 4 by the 0.04 frequency divider circuit 22.

@ It is a low-order group timing pulse.

0 This is the output of the latch circuit 43 which latches the data string of the low-order group (2) taken into the latch circuit 41 with the inverted clock signal with the clock signal 2'.

@ High-order group data 2 is multiplexed parallel data latched by the latch circuit 43 by the P/S conversion circuit 21.

In Figure 3, clock 2 and timing pulse 2 are ahead of clock 1 and timing pulse 1 by 5 clocks, but the same is true when clock 2 and timing pulse 2 are delayed. Transfer means 4
The setup time of the latch circuit used as 0,
Considering the hold time, it is possible to absorb phase fluctuations of less than 2 clocks each for lead and delay, and less than 4 clocks in total.

In the embodiment shown in FIG. 3, a case has been described in which there are two systems of multiplex circuits, but by adding a latch circuit of the clock transfer means, it is also possible to deal with a case of three or more systems.

With the above configuration, it is possible to absorb clock phase fluctuations up to a frequency close to the clock frequency division ratio.

〔Effect of the invention〕

0 According to the present invention as described above, by performing clock transfer using a low-order group clock, it is possible to absorb clock phase fluctuations up to a frequency division ratio and improve the efficiency of a multiplex circuit that outputs the same data from two multiplex circuits. A clock transfer circuit can be provided.

30.31 is INV.

40 is a clock transfer means; 41 to 43 are latch circuits, 51.52 is an FF circuit, are shown respectively.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining a time chart of an embodiment of the present invention, and FIG. 4 is a conventional block diagram. A block diagram illustrating an example, and FIG. 5 a diagram illustrating a time chart of a conventional example are shown, respectively. In the figure, 10 is the first multiplex circuit, 10A is the multiplex circuit, 11.21 is the P/S conversion circuit, 12.22 is the 4-divider circuit, 20 is the second multiplex circuit,

Claims (1)

[Claims] A clock transfer circuit in first and second multiplex circuits (10, 20) that has synchronized high-order group clocks and timing pulses and generates low-order group clocks by dividing the input high-order group clocks, respectively. an inverter (30) for inverting the low-order group clock generated by the first multiplex circuit (10); and an inverter (30) for inverting the low-order group clock generated by the first multiplex circuit (10);
After taking in the input low-order group data string with the inverted clock in the first and second multiplex circuits (10, 30),
20) A multi-circuit clock transfer circuit comprising clock transfer means (40) for respectively transferring the low-order group clocks generated in step 20).