JPH0767046A - Wide aspect television receiver - Google Patents

Abstract

PURPOSE:To provide a wide aspect television receiver which can provide the enlarged images of right and left parts by using digital signal processing. CONSTITUTION:When a right/left part enlargement mode is selected, a read address control signal (i) to be changed with inclination in proportion to the frequency of an output clock (d) during the central and the nearby term of a picture in a horizontal scanning cycle and to be changed with much smoother inclination during the right and left peripheral part of the term is inputted to a memory circuit 60 by a memory control circuit 50. During the term of the picture central part in the horizontal scanning term, the memory control circuit 50 outputs the output clock (d) as a read clock (g) without changing it and during the respective remaining right and left side peripheral part terms, a pulse thinning the output clock (d) is outputted as the read clock (g).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wide aspect television receiver, and more particularly to a wide aspect television having a screen having an aspect ratio larger than the aspect ratio of the television receiver on which an input video signal should be originally displayed. Regarding the receiver.

[0002]

2. Description of the Related Art The aspect ratio of the screen of a current television receiver for displaying a normal color video signal such as NTSC or PAL is so-called 3: 4, in which the vertical aspect ratio is 3 and the horizontal aspect ratio is 4.
It is the structure of. However, in recent years, various high-definition television signals having higher definition than ordinary color video signals have been proposed. Among them, the high-definition system whose screen aspect ratio is set to 9:16 is the next-generation color television. It is becoming popular as a method.

Therefore, the aspect ratio of the current screen is 3:
In addition to the television receivers up to that of No. 4, so-called wide aspect television receivers having an aspect ratio of 9:16 for a screen whose width is longer than this have been mixed. Therefore, it is conceivable to display an image of a normal color video signal by this wide aspect television receiver.

When an image of a normal color video signal is displayed on a wide aspect television receiver, the normal color video signal and the high-definition color video signal have the same horizontal scanning period, so that the normal color video signal is displayed. When is displayed as it is, an image different from the original image is horizontally enlarged by the difference in the aspect ratio. This first mode is generally called the full mode.

In a second mode, a wide aspect television receiver displays an image of a normal color video signal in a correct form. Therefore, this is referred to as horizontal compression, and the horizontal direction of the image is represented by the reciprocal of the aspect ratio. There is a method of compressing and displaying. This mode is generally called a normal mode. However, in this mode, there are no signal bands on the left and right of the screen, and it cannot be said that the entire screen is being used effectively.

Further, as a method of combining the above two modes, an image having a correct shape is obtained in the central portion of the image and the horizontal portion is enlarged in the peripheral portion, but the image is displayed on the entire screen, and the distortion of the image is noticeable. There is a third mode that gives a sense of reality without turning it off.

[0007]

By the way, in order to perform the horizontal compression in the second mode, there is a method of adjusting the amplitude of the horizontal output signal of the deflection circuit of the cathode ray tube to narrow the horizontal scanning range. This method is an analog technology and has an advantage that it can be realized at low cost, but it has the disadvantages that it requires adjustment and is susceptible to aging.

Therefore, conventionally, after the video signal is once written in the memory by digital signal processing, the video signal itself is compressed by reading the digital video signal from the memory at a frequency higher than the writing frequency according to the horizontal compression ratio. A method for doing so is known (Japanese Patent Laid-Open No. 3-11891).
Issue). According to this method, adjustment is basically unnecessary as compared with the former.

However, in the third mode, conventionally, the horizontal output signal of the deflection circuit of the television receiver is realized by changing the waveform at the center and left and right of the screen. This is a method based on analog technology, which requires adjustment and has a problem that the brightness at the peripheral portion of the screen is reduced because the scanning speed differs between the center and the left and right of the screen.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a wide aspect television receiver that solves the above problems by realizing the third mode by digital signal processing.

[0011]

According to the present invention, in order to achieve the above object, the horizontal direction when the input video signal is based on the vertical direction of the vertical and horizontal ratios of the first aspect ratio of the input video signal. In a wide aspect television receiver displaying a screen with a second aspect ratio, the input clock generation circuit generates an input clock based on the horizontal synchronizing signal of the input video signal, and the input clock is input as a write clock. And a memory circuit for writing the input video signal, an output clock generation circuit and a memory control means.

The input clock is input to the output clock generation circuit, and the first clock is higher than the input clock frequency.
The first output clock having a high frequency by a large proportion of the second aspect ratio with respect to the aspect ratio, and one or more of the first output clock thinned by a predetermined one or two or more thinning patterns different from each other. And a second output clock, respectively. The memory control means receives the first and second output clocks, reads the video signal from the memory circuit at the first output clock for the signal portion displayed in the central portion of the screen and in the vicinity of the input video signal, The signal portion displayed in the peripheral portion of the screen reads the video signal from the memory circuit based on the second output clock.

According to the present invention, the video signal read from the memory circuit is input to the memory circuit and an interpolation filter for interpolating data generated from peripheral pixels between adjacent pixels of the video signal as pixels. When the first output clock is input as the read clock, the read video signal of the memory circuit is passed as it is, and when the second output clock is input as the read clock, the read of the memory circuit is performed through the interpolation filter. And a selection means for selecting a video signal.

[0014]

According to the present invention, the memory control means causes the signal portion displayed in the central portion of the screen and its vicinity in the input video signal to have the second aspect ratio with respect to the first aspect ratio rather than the write clock frequency. In the central portion of the screen and in the vicinity thereof, an image in the original form of the input video signal is displayed because it is horizontally compressed and read by the first output clock having a high frequency by a large proportion.

In the signal portion displayed in the peripheral portion of the screen, a video signal is output from the memory circuit based on a second output clock obtained by thinning out the first output clock with a predetermined one or two or more thinning patterns different from each other. Since the image is read, an image enlarged in the horizontal direction is displayed in the peripheral portion of the screen. That is, according to the present invention, the left and right enlarged images can be obtained by digital signal processing.

Further, according to the present invention, by including the interpolation filter and the selecting means, when the signal portion displayed in the peripheral portion of the screen is horizontally enlarged and read from the memory circuit, it is output through the interpolation filter. Therefore, it is possible to correct image quality deterioration due to horizontal enlargement.

[0017]

1 is a block diagram of an embodiment of the present invention. This embodiment is an example of a wide aspect television receiver having an aspect ratio of 9:16, which is the ratio of the length to the width of the screen, and is capable of displaying a high-definition signal having an aspect ratio of 9:16. Not only is it possible, but also for NTSC video signals with a screen aspect ratio of 3: 4, the full mode shown in FIG.
The normal mode shown in FIG. 4 and the left and right partial enlargement mode shown in FIG. 7C can be selected and displayed by digital signal processing.

Here, the full mode is a mode in which an NTSC video signal is displayed on the time axis as it is, and as shown in FIG.
As shown in (A), an image stretched in the horizontal direction (horizontal direction) of the screen is displayed. In this mode, the image can be displayed on the entire screen, but the shape is different from the original shape. Further, in the normal mode, the aspect ratio of the screen to be displayed is 9:16, and the screen horizontal direction is longer than that of the NTSC system video signal of 9:12 (= 3: 4).
2B in the mode in which the image is horizontally compressed by that amount and displayed.
As shown in, the image is displayed on the screen in its original shape, but there are no signal portions on the left and right of the screen.

On the other hand, the left and right partial enlargement mode is shown in FIG.
As shown in, the NTSC video signal is displayed in the original shape by horizontal compression in the center of the screen as in the normal mode, and the image is displayed on the entire screen in the peripheral portion of the screen although it is slightly different from the original shape due to horizontal expansion. Mode.

In FIG. 1, an NTSC video signal a input to an input terminal 10 is a carrier color signal obtained by balance-modulating a 3.58 MHz color subcarrier with two types of color signals, as is well known. The luminance signal is a band-shared multiplexed signal, which is input to the NTSC decoder 20, where it is separated into a luminance signal and two types of chrominance signals, demodulated, and further converted into a digital signal. To the NTSC decoder 20 in parallel.
The signals input to the memory circuit 60 from the
TSC decode signal b).

The NTSC decoder 20 separates the horizontal synchronizing signal HD from the above luminance signal and supplies it to the input clock generating circuit 30 and the memory control circuit 50, respectively. The input clock generation circuit 30 uses the input horizontal synchronization signal HD
3 is a circuit for generating an input clock having a frequency that is an integral multiple of that frequency in phase synchronization with the horizontal synchronizing signal HD, and has a phase locked loop circuit configuration as shown in FIG. 3, for example.

In FIG. 3, the input clock generation circuit 30
Is a phase comparison / previous value holding circuit 31 for comparing the phase of the horizontal synchronizing signal HD and the output signal of the frequency divider 34 and holding the previous value,
An integrating circuit 32 that smoothes the output phase error signal of the phase comparison / previous value holding circuit 31, a voltage controlled oscillator 33 that receives the output voltage of the integrating circuit 32 as a control voltage, and whose output oscillation frequency is variably controlled. It comprises a frequency divider 34 for dividing the output oscillation frequency of the voltage controlled oscillator 33 and outputting it to the phase comparison / previous value holding circuit 31. As a result, the voltage-controlled oscillator 33 oscillates and outputs a high-frequency pulse that is phase-synchronized with the input horizontal synchronizing signal HD and that has the horizontal scanning frequency multiplied by the frequency division ratio of the frequency divider 34. Is output.

The input clock c is supplied to the output clock generation circuit 40 and the memory control circuit 50, respectively, as shown in FIG. The output clock generation circuit 40 is configured, for example, as shown in FIG. 4, and generates and outputs a pulse having a frequency with which the horizontal compression ratio in the normal mode is obtained as the output clock d. As will be described later, in the normal mode, the input clock c is input to the memory circuit 60 as the write clock and the output clock d is input to the memory circuit 60. Therefore, the frequency ratio between the input clock c and the output clock d is equal to the horizontal compression ratio. Become.

Here, the aspect ratio of the screen of the NTSC signal is 9:12, and when displaying in the normal mode on the 9:16 screen of the wide aspect television receiver, the horizontal compression ratio is 3/4 (= 12). / 16). Therefore, the frequency of the output clock d is set to 4/3 times the frequency of the input clock c.

In FIG. 4, the output clock generation circuit 40
Is a frequency divider 41 that divides the input clock c by 1/3, a phase comparison / previous value holding circuit 42 that compares the output signal of the frequency divider 41 with the output signal of the frequency divider 45, and a phase comparison. An integrating circuit 43 that smoothes the output phase error signal of the previous value holding circuit 42, and a voltage controlled oscillator 4 that receives the output voltage of the integrating circuit 43 as a control voltage and variably controls the output oscillation frequency.
4 and the output oscillation frequency of this voltage controlled oscillator 44 is 1 /
It comprises a frequency divider 45 which divides the frequency by 4 and outputs it to the phase comparison / previous value holding circuit 42, and a selector 46.

Phase comparison / previous value holding circuit 42, integrating circuit 4
3, the voltage-controlled oscillator 44 and the frequency divider 45 constitute a phase locked loop, and a clock whose frequency is 4/3 times the frequency of the input clock c is phase-locked with the output signal of the frequency divider 41. It is taken out from the controlled oscillator 44 and input to the selector 46.

The selector 46 performs a selection operation according to the mode switching signal e. When the mode switching signal e indicates the normal mode, the selector 46 selects the output signal of the voltage controlled oscillator 44 and takes it out as the output clock d, and the mode switching signal e is full. When indicating the mode, the input clock c is selected and taken out as it is as the output clock d.

The output clock d is the input clock c.
And the mode switching signal e are input to the memory control circuit 50 as shown in FIG. This memory control circuit 50 is shown in FIG.
As shown in FIG. 5, a write position determination circuit 51, a read position determination circuit 52, a read only memory (ROM) 53
And a 2-input AND circuit 54, the input clock c is output as it is as a write clock f, and the write position determining circuit 51 generates a write address control signal h based on the horizontal synchronizing signal HD and the input clock c.

The read position determining circuit 52 generates and outputs a read address control signal i based on the horizontal synchronizing signal HD, the output clock d and the mode switching signal e. This read address control signal i is input to the ROM 53 as an address control signal, and R corresponding to each mode is read.
Select OM data. Data of a thinning pattern for horizontal compression and horizontal expansion is written in the ROM 53 in advance, and a signal obtained by ANDing the output data and the output clock d by the AND circuit 54 is output as the read clock g.

The selector control signal j is written in the other data bits of the ROM 53, and the selector control signal j of "1" is output at the time of horizontal expansion to output the output of the interpolation filter 70 described later to the selector 80. To select.
Similarly, an interpolation control signal k for selecting an interpolation method corresponding to the enlargement ratio at the time of horizontal enlargement is output by other data bits stored in the ROM 53.

Returning to FIG. 1 again, the memory circuit 60 writes the NTSC decode signal b on the basis of the write address control signal h and the write clock f, and the read address control signal i and the read clock g. Based on this, the stored data forming each pixel is read out.

The interpolation filter 70 is for interpolating the portion where the data rate is lowered by horizontal expansion to improve the image quality, and the interpolation method is selected by the interpolation control signal k. The selector 80 selects one of the read signal of the memory circuit 60 and the output signal of the interpolation filter 70 based on the selector control signal j and outputs it to the output terminal 90.

Next, the operation of this embodiment will be described.
The NTSC video signal a shown in FIG. 6 (A) input to the input terminal 10 is separated and demodulated by the NTSC decoder 20 to be an NTSC decoded signal b, and the memory circuit 6
While being supplied to 0, the horizontal synchronizing signal HD is extracted and reproduced as shown in FIG. 6B and supplied to the input clock generation circuit 30 and the memory control circuit 50, respectively.

The memory control circuit 50 generates a write address control signal h synchronized with the input clock c of the input clock generation circuit 30 having an integral multiple of the horizontal scanning frequency with reference to the input horizontal synchronization signal HD. The write address control signal h is an address signal that monotonically increases within the horizontal scanning period, as shown in FIG. The memory circuit 60 writes the NTSC decode signal b based on the write address control signal h and the write clock f.

The read operation of the memory circuit 60 in which the NTSC decode signal b is written in this way differs depending on each of the three modes described above. First, the operation when the full mode is selected will be described. At this time, the mode switching signal e is the output clock generation circuit 40.
4 is supplied to the selector 46 shown in FIG. 4 to select the input clock c as the output clock d, while the read position determining circuit 52 shown in FIG. 5 in the memory control circuit 50 is selected.
6D, a read address control signal i that changes with the same period and the same inclination as the write address control signal h is generated and output.

This read address control signal i is the ROM
The data having the value "1" is input to the address terminal 53 and output to the AND circuit 54. This allows
The output clock d is directly output from the AND circuit 54 to the memory circuit 60 as the read clock g. Therefore, in the full mode, the memory circuit 60 is read by the read clock g having the same frequency as the write clock f in the same order as in the write, so that the memory circuit 60 is read.
An NTSC decode signal that has not been subjected to horizontal compression or horizontal expansion is read from and output to the output terminal 90 through the selector 80. As a result, FIG.
An image enlarged horizontally is displayed as shown on the right side of (A).

Next, the operation when the normal mode is selected will be described. At this time, the mode switching signal e is supplied to the selector 46 shown in FIG. 4 in the output clock generation circuit 40 to select the output signal of the voltage controlled oscillator 44 as the output clock d. At the same time, the mode switching signal e is supplied to the read position determining circuit 52 shown in FIG. 5 in the memory control circuit 50, and as shown in FIG. 6E, the horizontal compression is performed in the horizontal scanning period. Then, the read address control signal i that changes with a slope proportional to the frequency of the output clock d from the voltage controlled oscillator 44 is generated and output only during the display period (a period excluding the left and right peripheral portions of the screen).

The read address control signal i is supplied to the memory circuit 60, and is also input to the address terminal of the ROM 53 so that only the period for horizontal compression and display of the horizontal scanning period (excluding the left and right peripheral portions of the screen). Data of "1" is output to the AND circuit 54, and data of "0" is output during other periods. As a result, the AND circuit 54 outputs the output clock d shown in FIG. 7A and the output from the ROM 53 shown in the upper side of FIG. 7B.
By taking the logical product with the data having the value of 1 ″, the output clock d is output as it is to the memory circuit 60 as the read clock g as shown in the lower part of FIG.

Therefore, in the normal mode, the memory circuit 60 outputs the stored NTSC decode signal by the read clock g having a frequency of 4/3 times the write clock f during the horizontal scanning period except for the left and right peripheral portions of the screen. The time axis in the horizontal direction is compressed 3/4 times and read. This read signal is interpolated by the selector control signal j.
Bypassed and output terminal 9 directly through selector 80
Output to 0.

As a result, in this normal mode, as shown in FIG.
As shown on the right side of (B), the image is displayed in the same shape as it is (at the same size) during the period excluding the left and right peripheral portions of the screen.
However, since the memory circuit 60 is not read during the peripheral portions on the left and right of the screen, no image is displayed.

Next, the operation when the left and right partial enlargement mode is selected will be described. At this time, the mode switching signal e is supplied to the selector 46 shown in FIG. 4 in the output clock generation circuit 40 to select the output signal of the voltage controlled oscillator 44 as the output clock d. At the same time, the mode switching signal e is supplied to the read position determining circuit 52 shown in FIG. 5 in the memory control circuit 50, which causes the address control signal i shown in FIG. 6F to be generated and output.

That is, as shown in FIG. 6 (F), the address control signal i is the same as that in the normal mode during the horizontal scanning period in the center of the screen and in the vicinity thereof.
4 changes with a slope proportional to the frequency of the output clock d, and in other periods of the left and right peripheral parts, changes with a gentler slope. The reason why the inclination of the period of the left and right peripheral portions is gentler than that in the normal mode is that the output clock d is thinned out by the ROM data and the frequency of the read clock g is lowered as described later.

The read address control signal i is supplied to the memory circuit 60, and is also input to the address terminal of the ROM 53, so that the center of the screen and the vicinity thereof in the horizontal scanning cycle have a value of "1". The data is output to the AND circuit 54, and the data of the thinning pattern for the predetermined horizontal expansion is output during the period other than the left and right peripheral portions of the screen.

Here, as shown in FIG. 8A, the input NTSC signal a which should originally be displayed on the screen with the aspect ratio of 3: 4 (= 9: 12) is converted into the aspect ratio 9: 1 of this embodiment.
When displaying in the left and right partial enlargement mode on the 6 wide screen,
In the horizontal direction of the screen shown in FIG. 8 (A), the central part 8/12 of the screen including the central part is horizontally compressed and displayed at the same size, and the remaining 2/12 on the left side and 2/12 on the right side are each divided into 3 equal parts. Assuming that the images are displayed from the center side of the screen toward the edge of the screen in the same size, 2 times magnification, and 3 times magnification, the wide screen having the aspect ratio of 9:16 according to the present embodiment is as shown in FIG. 8B. The image is displayed at the magnification.

In this case, the ROM 53 in the memory control circuit 50 outputs the data of the value "1" shown in FIG. 7 (B) to the AND circuit 54 during the screen central portion 8/12 of the horizontal scanning period. Then, the AND circuit 54 outputs the output clock d ((A) in the figure) as it is as the read clock g as shown in (C) in the figure.

Then, the ROM 53 outputs "1" data in the same manner as above for the 1 / 18th period from the center of the remaining 2/12 periods on the left and right sides of the horizontal scanning period. During the period of 1/18, the first thinning pattern as shown in FIG. 7 (D) is output, and the AND circuit 54 reads out pulses obtained by thinning out every other output clock d as shown in FIG. 7 (E). The clock g is output, and the second thinning pattern as shown in FIG. 7F is output during the period of 1/18 at the end of the screen, and the AND circuit 54 outputs the second thinning pattern as shown in FIG. A pulse obtained by thinning out two clocks out of three clocks d is output as a read clock g.

The NTSC decode signal read from the memory circuit 60 by the read clock g is input to the interpolation filter 70 and the selector 80 of FIG. 1, respectively. In the left and right partial enlargement mode, the center of the horizontal scanning period displayed at the same magnification as described above 7/9 {= (8/12) +
Interpolation filter 7 during the period of (2/36) + (2/36)}
The selector 80 is controlled so as to bypass 0, and the selector 80 is controlled so as to select the output of the interpolation filter 70 during the remaining period.

The interpolation filter 70 applies the interpolation corresponding to the enlargement ratio to the input signal by the interpolation control signal k from the ROM 53. That is, in the portion that is doubled in size, FIG.
Two output signals (time-series combined signals of the pixels A, B, and C) of the memory circuit 60 schematically shown in FIG. The process of inserting one pixel of the average value of the pixel values is performed.

Similarly, the interpolation filter 70 is a memory circuit 60 schematically shown in FIG.
Output signal (time-series combined signal of pixels A, B, and C), two pixels are determined from the values of two adjacent pixels between two adjacent pixels as schematically shown in FIG. insert. For example, between two adjacent pixels of each value of A and B, the first pixel of the value represented by (3A + B) / 4,
A second pixel having a value represented by (A + 3B) / 4 is inserted.

The output signal of the interpolation filter 70 is output to the output terminal 90 through the selector 80 at the time of the double expansion and the triple expansion. In this way, in the right and left partial enlargement mode, as shown on the right side of FIG. 2C, the signal portion displayed in the central portion of the screen and in the vicinity thereof in the input video signal is originally compressed by the image to be originally displayed. The signal portion displayed in the same shape (at the same size) and the signal portion displayed in the peripheral portion of the screen display a horizontally enlarged image, and the non-signal display portion disappears.

Here, when the horizontal compression and horizontal expansion processing is performed at the rate described with reference to FIG. 8A, images are displayed on the wide screen at the rate shown in FIG. 8B. As a result, the portion displayed in the correct shape is 58.3% (= 9.3 / 16) of the entire wide screen, and the portion enlarged to double is 16.7% (= 2.7 / 16), 3 The portion that is doubled is 25% (= 4/16).

As described above, according to the present embodiment, since the left and right partial enlargement modes can be performed by digital signal processing, adjustment can be dispensed with, and the image quality of the horizontally enlarged image can be improved by the interpolation filter 70. Can be made substantially equal to the center of the screen, and the brightness of the peripheral portion of the screen can also be made equal to the center of the screen.

The present invention is not limited to the above-described embodiment, for example, the expansion pattern is not limited to the example of FIG. 8, and a plurality of kinds of expansion patterns can be selected by selecting the address signal for the ROM 53. (Output clock thinning pattern) can be easily realized. Also, NTS that should be displayed on a screen with an aspect ratio of 3: 4
An example of displaying the C video signal on a wide screen having an aspect ratio of 9:16 has been described, but the present invention is not limited to this, and it is easy to display a signal having an aspect ratio other than this. It can be applied to.

[0054]

As described above, according to the present invention,
Since the left and right enlarged images can be obtained by digital signal processing, it is not necessary to adjust the horizontal scanning range, and it is possible to easily change the enlargement area and enlargement ratio. Since the entire screen can be effectively used, the sense of presence can be increased.

Further, according to the present invention, when the signal portion displayed in the peripheral portion of the screen is horizontally enlarged and read from the memory circuit in the left and right portion enlargement mode, the signal portion is output through the interpolation filter to output the horizontal portion. Since the image quality deterioration due to the enlargement is corrected, the brightness in the central portion of the screen and the peripheral portion of the screen can be made substantially constant, and thus the commercial value of the wide aspect television receiver can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram illustrating a display in each mode according to an embodiment of the present invention.

3 is a block diagram of an embodiment of an input clock generation circuit in FIG.

FIG. 4 is a block diagram of an embodiment of the output clock generation circuit in FIG.

5 is a block diagram of an embodiment of a memory control circuit in FIG.

FIG. 6 is a time chart for explaining the operation of the main part of the present invention.

7 is a time chart for explaining the operation of FIG.

FIG. 8 is a diagram illustrating an example of a display form in a left and right partial enlargement mode according to an embodiment of the present invention.

FIG. 9 is a diagram for explaining the operation of the interpolation filter in FIG.

[Explanation of symbols]

 10 Input Terminal 20 NTSC Decoder 30 Input Clock Generation Circuit 33, 44 Voltage Controlled Oscillator 34, 41, 45 Frequency Divider 40 Output Clock Generation Circuit 46, 80 Selector 50 Memory Control Circuit 51 Write Position Determination Circuit 52 Read Position Determination Circuit 53 Read -Only memory (ROM) 54 2-input AND circuit 60 Memory circuit 70 Interpolation filter 90 Output terminal

Claims (3)

[Claims] 1. A display of an input video signal on a screen having a second aspect ratio, in which the horizontal direction is large when the vertical direction is used as a reference among the vertical and horizontal ratios of the first aspect ratio of the input video signal. In a wide aspect television receiver, an input clock generation circuit that generates an input clock based on a horizontal synchronizing signal of the input video signal, a memory circuit that receives the input clock as a write clock and writes the input video signal, The input clock is input, and the first output clock having a frequency higher than the input clock frequency by a ratio of the second aspect ratio to the first aspect ratio is higher than the first output clock. One or two or more second thinned out by one or two or more thinning patterns different from each other
And an output clock generating circuit for respectively generating the output clocks of the first and second output clocks, and the signal portion displayed in the central portion of the screen and in the vicinity of the first video signal is input to the first and second output clocks. The video signal is read from the memory circuit at the output clock, and the signal portion displayed in the peripheral portion of the screen has a memory control unit for reading the video signal from the memory circuit based on the second output clock. Aspect television receiver. 2. An interpolation filter for inputting a video signal read from the memory circuit, and interpolating data generated from peripheral pixels as pixels between adjacent pixels of the video signal, and the memory circuit including the interpolation filter. When the first output clock is input as the read clock, the read video signal of the memory circuit is passed as it is, and when the second output clock is input as the read clock, it is passed through the interpolation filter. 2. A wide aspect television receiver according to claim 1, further comprising a selecting means for selecting a read video signal of the memory circuit. 3. The output clock generation circuit is a circuit for generating two or more second output clocks having different frequencies from each other, and the memory control means has a display position of the output video signal of the memory circuit on the left and right of the screen. The signal part closer to both ends should be read with the second output clock of lower frequency.
2. The wide aspect television receiver according to claim 1, wherein two or more second output clocks are sequentially switched.