JPH0766391A - Ohmic electrode - Google Patents

Ohmic electrode

Info

Publication number
JPH0766391A
JPH0766391A JP21575793A JP21575793A JPH0766391A JP H0766391 A JPH0766391 A JP H0766391A JP 21575793 A JP21575793 A JP 21575793A JP 21575793 A JP21575793 A JP 21575793A JP H0766391 A JPH0766391 A JP H0766391A
Authority
JP
Japan
Prior art keywords
electrode
ohmic
layer
metal
doped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP21575793A
Other languages
Japanese (ja)
Other versions
JP2630208B2 (en
Inventor
Kazuhiko Onda
和彦 恩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5215757A priority Critical patent/JP2630208B2/en
Publication of JPH0766391A publication Critical patent/JPH0766391A/en
Application granted granted Critical
Publication of JP2630208B2 publication Critical patent/JP2630208B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To prevent mutual diffusion between an electrode and a semiconductor layer, and form a stable electrode, by using high melting point metal as the electrode metal of an nonalloy ohmic electrode. CONSTITUTION:A source electrode 18 and a drain electrode 19 are formed on an N-type InGaAs cap layer 17. High melting point metal whose melting point is higher than or equal to 1200 deg.C is used for the ohmic electrodes 18, 19. A Schottky gate electrode 20 is formed in a recessed part wherein the part between the electrodes 18 and 19 is etched and eliminated until the middle part of an undoped InAlAs Schottky layer 16. As to the ohmic metals 18, 19, the interface lowermost layer metals are Mo 18a, 19a, on which Ti 18b, 19b, Pt 18c, 19c, and Au 18d, 19d are laminated in order. A device is formed by using the above multilayered structure. Thereby the heat treatment in the case of usual alloy ohmic is made unnecessary, and an ohmic electrode having excellent ohmic property can be obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は低抵抗なオーミック電極
に関するものであり、マイクロ波及びミリ波の波長領域
に於て高速動作する半導体装置への応用が可能である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low-resistance ohmic electrode, which can be applied to a semiconductor device which operates at high speed in the microwave and millimeter wave wavelength regions.

【0002】[0002]

【従来の技術】アロイ型オーミック電極としては従来、
半導体表面に金属を蒸着し、高温熱処理を行うことで金
属〜半導体界面の接触をオーミック接触化する事で作製
していた。ノンアロイオーミック電極は金属〜半導体界
面はショットキー接触であるものの、そのショットキー
障壁の高さは低い、あるいはショトキーを形づくる半導
体層の厚みが小さいためトンネル効果及び熱電子放出に
よりチャネルと電気的導通が得られている構造を示す。
この代表的な構造として例えば、ジャパニーズ・ジャー
ナル・オブ・アプライド・フィジックス(Japane
se Journal of Applied Phi
sics)1988年第27巻第9号1718頁にNi
ttonoらの論文をはじめいくつかの研究が発表され
てきている。これはGaAs基板上にInGaAsの高
濃度層を設けることでショットキー障壁高さを小さくお
さえ、良好なオーミック特性を得ている。このようにノ
ンアロイオーミックを採用することでオーミック電極の
熱処理工程が省略され、従って熱処理によるゲート電極
の劣化をもたらせる事なく電界効果トランジスタを作製
することが出来る。
2. Description of the Related Art As an alloy type ohmic electrode,
It was produced by vapor-depositing a metal on the surface of a semiconductor and performing high-temperature heat treatment to make the contact between the metal and the semiconductor interface ohmic contact. The non-alloy ohmic electrode has a Schottky contact at the metal-semiconductor interface, but its Schottky barrier height is low, or the semiconductor layer forming the Schottky is small in thickness, so that it is electrically connected to the channel due to the tunnel effect and thermionic emission. Shows the obtained structure.
As a typical structure of this, for example, Japanese Journal of Applied Physics (Japane)
se Journal of Applied Phi
ss) 1988 Vol 27 No. 9 1718 Ni
Several studies have been published, including the paper by ttono et al. By providing a high-concentration layer of InGaAs on a GaAs substrate, the height of the Schottky barrier is kept small, and good ohmic characteristics are obtained. By adopting the non-alloy ohmic as described above, the heat treatment step of the ohmic electrode is omitted, and therefore, the field effect transistor can be manufactured without causing the deterioration of the gate electrode due to the heat treatment.

【0003】ゲート電極をキャップ層よりもバンドギャ
ップが大きく電子親和力が小さい半導体により構成され
ているショットキー層上に形成する際、トンネル効率を
向上させる該半導体層のゲート電極形成位置よりも表面
側に高In組成層で構成された第2のキャップ層を設
け、オーミック電極は該半導体層表面側に形成されてい
る第1のキャップ層上に形成される例がある。このよう
な構造がInP基板上のInAlAs/InGaAs系
HEMTに応用された例が、例えばアイ・イー・イー・
イー・エレクトロン・デバイス・レターズ、第11巻、
第11号、502頁(IEEE ELECTRON D
EVICE LETTERS、VOL.11、NO.1
1、P.502)にEnokiら(T.Enoki e
t al.)に報告されている。ここでは第1のキャッ
プ層としてInGaAs層、第2のキャップ層としてI
nAlAs層を用いている。この報告では電極金属とし
てAuGe/Niがノンアロイの状態で用いられてお
り、オーミック電極のコンタクト抵抗として0.14Ω
・mmが得られている。このような構造はオーミック電
極はキャップ層にショットキー接触しているにも関わら
ずショットキー層のバリアが薄いためトンネル効率が上
がり、低ソース抵抗及び低ドレイン抵抗なオーミック電
極が作製できる。
When a gate electrode is formed on a Schottky layer made of a semiconductor having a band gap larger than that of a cap layer and an electron affinity smaller than that of the cap layer, tunnel efficiency is improved. There is an example in which a second cap layer composed of a high In composition layer is provided on the substrate, and the ohmic electrode is formed on the first cap layer formed on the surface side of the semiconductor layer. An example in which such a structure is applied to an InAlAs / InGaAs HEMT on an InP substrate is, for example, IEE
E-Electron Device Letters, Volume 11,
No. 11, p. 502 (IEEE ELECTRON D
EVICE LETTERS, VOL. 11, NO. 1
1, P.I. 502) to Enoki et al. (T. Enokie e.
t al. ) Has been reported. Here, the first cap layer is an InGaAs layer, and the second cap layer is I
The nAlAs layer is used. In this report, AuGe / Ni is used in the non-alloy state as the electrode metal, and the contact resistance of the ohmic electrode is 0.14Ω.
-Mm is obtained. In such a structure, although the ohmic electrode is in Schottky contact with the cap layer, the barrier of the Schottky layer is thin, so that tunnel efficiency is improved, and an ohmic electrode having low source resistance and low drain resistance can be manufactured.

【0004】[0004]

【発明が解決しようとする課題】一般に用いられている
AuGe/Niに代表されるようなアロイ系のオーミッ
ク電極は、熱的安定性に欠け、高温処理によって金属と
半導体の相互拡散が起こりコンタクト抵抗が劣化する等
の問題があった。Wなどの金属をノンアロイオーミック
電極として用いることで熱的な安定性は向上するもの
の、更なる信頼性向上が望まれており、また、これらの
高融点金属を電極に用いる場合、加工性の点でスパッタ
法を用いなければならない等の制約や問題も多い。
The alloy type ohmic electrode represented by AuGe / Ni, which is generally used, lacks thermal stability, and the high temperature treatment causes mutual diffusion of metal and semiconductor, resulting in contact resistance. There was a problem such as deterioration. Although thermal stability is improved by using a metal such as W as the non-alloy ohmic electrode, further improvement in reliability is desired, and when these refractory metals are used for the electrode, workability is improved. There are many restrictions and problems in that the sputtering method must be used.

【0005】[0005]

【課題を解決するための手段】熱的安定性に長け、かつ
加工性に優れた高融点金属をこのノンアロイ型オーミッ
ク電極金属として用いることで熱処理に於いても金属が
半導体と相互拡散することなく安定した接触を保つこと
で高信頼な電極形成が可能となる。
[MEANS FOR SOLVING THE PROBLEMS] By using a refractory metal having excellent thermal stability and excellent workability as the non-alloy type ohmic electrode metal, the metal does not interdiffuse with the semiconductor even in the heat treatment. Maintaining stable contact enables highly reliable electrode formation.

【0006】本発明は、半導体基板上に設けられた金属
が活性層と電気的接触をとっているオーミック電極に於
いて、前記電極金属が融点が1200℃を越える高融点
金属を最下層とした少なくとも1層以上の積層からなる
ことを特徴とする。また該高融点金属がMo,Cr,P
t,Pd,Ni,Re,Os,Ta,Nb,Ir,R
u,Rhのうちのいずれかの元素であることを特徴とす
る。
According to the present invention, in the ohmic electrode in which the metal provided on the semiconductor substrate is in electrical contact with the active layer, the lowermost layer is a high melting point metal having a melting point of more than 1200 ° C. It is characterized in that it is composed of at least one or more layers. The refractory metal is Mo, Cr, P
t, Pd, Ni, Re, Os, Ta, Nb, Ir, R
It is characterized in that it is one of the elements u and Rh.

【0007】[0007]

【作用】高融点金属をノンアロイオーミック電極の電極
金属として用いることで半導体層との間で相互拡散が起
こることなく、安定した電極形成が可能となる。一般に
高融点金属は半導体材料と反応しくいのでアロイオーミ
ックしては不適であるが、ノンアロイ系オーミックの電
極材料として用いることで熱的に安定した電極を得るこ
とが可能となる。またMoをはじめとする各材料は電子
銃蒸着法で比較的容易に形成することが可能である。
By using the refractory metal as the electrode metal of the non-alloy ohmic electrode, stable electrode formation can be achieved without mutual diffusion with the semiconductor layer. Generally, refractory metals do not react well with semiconductor materials and are not suitable for alloy ohmic use, but when used as a non-alloy type ohmic electrode material, a thermally stable electrode can be obtained. In addition, each material such as Mo can be formed relatively easily by the electron gun vapor deposition method.

【0008】[0008]

【実施例】(実施例1)本発明の実施例を図面を参照し
ながら詳細に説明する。
EXAMPLE 1 An example of the present invention will be described in detail with reference to the drawings.

【0009】図1に本発明のオーミック電極を電界効果
トランジスタに適用した構造の一例を表わす要部切断面
図を示す。
FIG. 1 is a cross-sectional view of a main part showing an example of a structure in which the ohmic electrode of the present invention is applied to a field effect transistor.

【0010】半絶縁性InP基板11上にノンドープI
0 . 5 2 Al0 . 4 8 As層12を800nmの厚さ
で、ノンドープNi0 . 5 3 Ga0 . 4 7 Asチャネル
層13を40nmの厚さで、ノンドープIn0 . 5 2
0 . 4 8 As層14を3nmの厚さで、2×101 8
cm- 3 の濃度にn型にSiドープされたIn0 . 52
Al0 . 4 8 As電子供給層15を30nmの厚さで、
ノンドープIn0 . 52 Al0 . 4 8 Asショットキー
層16を20nmの厚さで、2×101 9 cm- 3 の濃
度にn型にSiドープされたIn0 . 5 3 Ga0 . 4 7
Asキャップ層17を30nmの厚さで、それぞれ順次
結晶成長した。
Non-doped I on the semi-insulating InP substrate 11
n 0. In 5 2 Al 0. 4 8 As layer 12 to a thickness of 800 nm, a non-doped Ni 0. 5 3 Ga 0. 4 7 The As channel layer 13 with a thickness of 40 nm, undoped In 0. 5 2 A
l 0. In 4 8 As layers 14 of 3nm thickness, 2 × 10 1 8
cm -. In 0 which is Si-doped n-type to a concentration of 3 52
In Al 0. 4 8 As the thickness of 30nm electron supply layer 15,
.. Non-doped In 0 52 Al 0 4 8 with As Shot key layer 16 of 20nm thickness, 2 × 10 1 9 cm - .. In 0 which is Si-doped n-type to a third concentration 5 3 Ga 0 4 7
The As cap layer 17 was sequentially grown with a thickness of 30 nm.

【0011】n型InGaAsキャップ層17の上にソ
ース電極18及びドレイン電極19を形成する。このオ
ーミック電極18,19間にノンドープInAlAsシ
ョットキー層16の途中までエッチング除去したリセス
領域内部にショットキーゲート電極20を形成する。
A source electrode 18 and a drain electrode 19 are formed on the n-type InGaAs cap layer 17. The Schottky gate electrode 20 is formed between the ohmic electrodes 18 and 19 in the recess region which is removed by etching up to the middle of the non-doped InAlAs Schottky layer 16.

【0012】オーミック金属18、19として界面最下
層金属をMo(モリブデン)としたMo(10nm)
(18a,19a)/Ti(50nm)(18b,19
b)/Pt(50nm)(18c,19c)/Au(1
00nm)(18d,19d)の積層構造でデバイスを
作製したところ、オーミック電極は通常のアロイオーミ
ックのように熱処理する事なく良好なオーミック性を有
しており、コンタクト抵抗として0.075Ω・mmが
得られた。
Mo (10 nm) in which the interface lowermost layer metal is Mo (molybdenum) as the ohmic metals 18 and 19
(18a, 19a) / Ti (50 nm) (18b, 19
b) / Pt (50 nm) (18c, 19c) / Au (1
(00 nm) (18d, 19d), a device was manufactured, and the ohmic electrode had good ohmic characteristics without heat treatment like normal alloy ohmic, and the contact resistance was 0.075Ω · mm. Was obtained.

【0013】また耐熱試験を行い、その結果(白丸の
点)を図2に示すが、350℃、10分間のアニールに
於いてもMo/Ti/Pt/Au構造はほとんど劣化は
みられず、コンタクト抵抗0.078Ω・mmが得られ
ている。Moを用いないでTi(50nm)/Pt(5
0nm)/Au(100nm)の積層構造を用いた場合
の耐熱試験の結果(黒丸の点)も併せて示しているが3
50℃の熱処理によりコンタクト抵抗が大きく劣化し、
0.2Ω・mm以上の値が得られている。以上の結果は
Ti/Pt/Auオーミックに於ける熱処理による劣化
は金属と半導体の相互拡散が要因であり、高融点金属で
あるMoを界面に挟み込むことでTiと半導体の相互拡
散が抑制されることを示している。
A heat resistance test was conducted, and the results (open circles) are shown in FIG. 2. Almost no deterioration was observed in the Mo / Ti / Pt / Au structure even after annealing at 350 ° C. for 10 minutes. A contact resistance of 0.078 Ω · mm is obtained. Ti (50nm) / Pt (5
The results of the heat resistance test (dots with black circles) when a laminated structure of 0 nm) / Au (100 nm) is used are also shown.
Contact resistance is greatly deteriorated by heat treatment at 50 ° C,
A value of 0.2 Ω · mm or more is obtained. The above results indicate that the deterioration due to the heat treatment in Ti / Pt / Au ohmic is due to the mutual diffusion of the metal and the semiconductor, and the interdiffusion of Ti and the semiconductor is suppressed by sandwiching Mo, which is a refractory metal, at the interface. It is shown that.

【0014】キャップに用いられているInGaAs層
17のIn組成は本実施例に於いては0.53に設定し
ているが、本発明はこのIn組成比をこの値に限定する
ものではなく、歪層としてミスフィット転移が発生しな
い範囲であればIn組成比を更に大きくすることが可能
である。また、キャップInGaAs層中のIn組成比
は一様でなくても良く、In組成の大きな部分は層中に
少なくとも1部分存在すればキャップInGaAs層の
伝導帯はIn組成が一様に53%に設定されている場合
に比べ小さくなるので、オーミック抵抗低減の効果は確
認できる。本実施例では高融点金属としてMoを用いた
ものを示したが、このMoはCr,Pt,Pd,Ni,
Re,Os,Ta,Nb,Ir,Ruなどの他の高融点
金属と置き換えても同様の発明の効果が得られる。
The In composition of the InGaAs layer 17 used for the cap is set to 0.53 in this embodiment, but the present invention does not limit this In composition ratio to this value. The In composition ratio can be further increased as long as the strained layer does not cause misfit transition. Further, the In composition ratio in the cap InGaAs layer does not have to be uniform, and if at least one portion having a large In composition exists in the layer, the conduction band of the cap InGaAs layer has a uniform In composition of 53%. Since it is smaller than when set, the effect of reducing ohmic resistance can be confirmed. In this embodiment, Mo is used as the refractory metal, but this Mo contains Cr, Pt, Pd, Ni,
The same effect of the invention can be obtained even if it is replaced with another refractory metal such as Re, Os, Ta, Nb, Ir, Ru.

【0015】(実施例2)図3に本発明のオーミック電
極を適用した半導体装置の構造の別の例を表わす要部切
断面図を示す。
(Embodiment 2) FIG. 3 is a cross-sectional view of a main part showing another example of the structure of a semiconductor device to which the ohmic electrode of the present invention is applied.

【0016】半絶縁性InP基板31上にノンドープI
0 . 5 2 Al0 . 4 8 As層32を800nmの厚さ
で、ノンドープIn0 . 5 3 Ga0 . 4 7 Asチャネル
層33を40nmの厚さで、ノンドープIn0 . 5 2
0 . 4 8 As層34を3nmの厚さで、2×101 8
cm- 3 の濃度にn型にSiドープされたIn0 . 5 2
Al0 . 4 8 As電子供給層35を30nmの厚さで、
ノンドープIn0 . 5 2Al0 . 4 8 Asショットキー
層36を20nmの厚さで、5×101 8 cm-3 の濃
度にn型にSiドープされたIn0 . 5 2 Al0 . 4 8
Asキャップ層37を30nmの厚さで、5×101 8
cm- 3 の濃度にn型SiドープされたIn0 . 5 3
0 . 4 7 Asキャップ層38を10nmの厚さで、そ
れぞれ順次結晶成長した。
Non-doped I on the semi-insulating InP substrate 31
n 0. In 5 2 Al 0. 4 8 As layer 32 a thickness of 800 nm, a non-doped In 0. 5 3 Ga 0. 4 7 The As channel layer 33 with a thickness of 40 nm, undoped In 0. 5 2 A
l 0. In 4 8 As layers 34 of 3nm thickness, 2 × 10 1 8
cm -. In 0 which is Si-doped n-type to a concentration of 3 5 2
In Al 0. 4 8 As the thickness of the electron supply layer 35 30 nm,
Doped In 0. 5 2 Al 0. 4 8 As Shot key layer 36 with a thickness of 20nm, 5 × 10 1 8 cm In 0 which is Si-doped n-type to a concentration of -3. 5 2 Al 0. 4 8
The As cap layer 37 with a thickness of 30 nm is 5 × 10 18
cm −3 Concentration n-type Si-doped In 0.53 G
a 0. In 4 7 As cap layer 38 of 10nm thickness were sequentially grown respectively.

【0017】n型InGaAsキャップ層上にソース電
極39及びドレイン電極40を形成する。このオーミッ
ク電極39,40間にノンドープInAlAsショット
キー層36の途中までエッチング除去されたリセス領域
内部にショットキーゲート電極41を形成する。
A source electrode 39 and a drain electrode 40 are formed on the n-type InGaAs cap layer. A Schottky gate electrode 41 is formed between the ohmic electrodes 39 and 40, inside the recess region which is etched and removed halfway through the non-doped InAlAs Schottky layer 36.

【0018】オーミック金属39,40として界面最下
層金属をMo(モリブデン)としたMo(10nm)
(39a,40a)/Ti(50nm)(39b,40
b)/Pt(50nm)(39c,40c)/Au(1
00nm)(39d,40d)の積層構造でデバイスを
作製したところ、オーミック電極は通常のアロイオーミ
ックのように熱処理する事なく良好なオーミック性を有
しており、コンタクト抵抗として0.45Ω・mmが得
られた。
Mo (10 nm) in which the interface lowermost layer metal is Mo (molybdenum) as the ohmic metals 39 and 40
(39a, 40a) / Ti (50 nm) (39b, 40
b) / Pt (50 nm) (39c, 40c) / Au (1
(00 nm) (39d, 40d), a device was manufactured, and the ohmic electrode had good ohmic characteristics without heat treatment like normal alloy ohmic, and the contact resistance was 0.45Ω · mm. Was obtained.

【0019】また耐熱試験を行い、その結果(白丸の
点)図4に示すが、350℃、10分間のアニールに於
いてもMo/Ti/Pt/Au構造はほとんど劣化はみ
られず、コンタクト抵抗0.048Ω・mmが得られて
いる。Moを用いないでTi(50nm)/Pt(50
nm)/Au(100nm)の積層構造を用いた場合の
耐熱試験の結果(黒丸の点)も併せて示しているが35
0℃の熱処理によりコンタクト抵抗が大きく劣化し、
0.1Ω・mm以上の値が得られている。以上の結果は
Ti/Pt/Auオーミックに於ける熱処理による劣化
は金属と半導体の相互拡散が要因であり、高融点金属で
あるMoを界面に挟み込むことでTiと半導体の相互拡
散が抑制されることを示している。
A heat resistance test was conducted, and the result (open circles) is shown in FIG. 4. The Mo / Ti / Pt / Au structure showed almost no deterioration even after annealing at 350 ° C. for 10 minutes. A resistance of 0.048 Ω · mm is obtained. Ti (50nm) / Pt (50
nm) / Au (100 nm) laminated structure is also used, the result of the heat resistance test (dots in black) is also shown.
Contact resistance is greatly deteriorated by heat treatment at 0 ° C,
A value of 0.1 Ω · mm or more is obtained. The above results indicate that the deterioration due to the heat treatment in Ti / Pt / Au ohmic is due to the mutual diffusion of the metal and the semiconductor, and the interdiffusion of Ti and the semiconductor is suppressed by sandwiching Mo, which is a refractory metal, at the interface. It is shown that.

【0020】キャップに用いられているInGaAs層
38のIn組成は本実施例に於いては0.53に設定し
ているが、本発明はこのIn組成比をこの値に限定する
ものではなく、歪層としてミスフィット転移が発生しな
い範囲であれば該In組成比を更に大きくすることが可
能である。また、キャップInGaAs層中のIn組成
比は一様でなくても良く、In組成の大きな部分は層中
に少なくとも1部分存在すればキャップInGaAs層
の伝導帯はIn組成が一様に53%に設定されいる場合
に比べ小さくなるので、オーミック抵抗低減の効果は確
認できる。本実施例では高融点金属としてMoを用いた
ものを示したが、このMoはCr,Pt,Pd,Ni,
Re,Os,Ta,Nb,Ir,Ruなどの他の高融点
金属と置き換えても同様の効果が得られる。
The In composition of the InGaAs layer 38 used for the cap is set to 0.53 in this embodiment, but the present invention does not limit this In composition ratio to this value. The In composition ratio can be further increased as long as the strained layer does not cause misfit transition. Further, the In composition ratio in the cap InGaAs layer does not have to be uniform, and if at least one portion having a large In composition exists in the layer, the conduction band of the cap InGaAs layer has a uniform In composition of 53%. Since it is smaller than when it is set, the effect of reducing ohmic resistance can be confirmed. In this embodiment, Mo is used as the refractory metal, but this Mo contains Cr, Pt, Pd, Ni,
The same effect can be obtained by substituting other refractory metals such as Re, Os, Ta, Nb, Ir and Ru.

【0021】[0021]

【発明の効果】本発明により耐熱性をはじめとする信頼
性に優れたオーミック電極が得られる。実験によりコン
タクト抵抗の劣化は少なくとも350℃までは変化しな
いことが確認できている。この信頼性は半導体とオーミ
ック金属の界面にMoをはじめとする高融点金属を用い
ることに起因し、かつノンアロイに適した半導体積層構
造と併用することで低抵抗な高信頼オーミック電極を得
ることが可能となる。
According to the present invention, an ohmic electrode having excellent reliability such as heat resistance can be obtained. It has been confirmed by experiments that the deterioration of contact resistance does not change up to at least 350 ° C. This reliability is due to the use of a refractory metal such as Mo at the interface between the semiconductor and the ohmic metal, and it is possible to obtain a highly reliable ohmic electrode with low resistance when used in combination with a semiconductor laminated structure suitable for non-alloy. It will be possible.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明を適用した一実施例の半導体装置の構造
を示す図である。
FIG. 1 is a diagram showing a structure of a semiconductor device of an embodiment to which the present invention is applied.

【図2】本発明の効果を説明するための図である。FIG. 2 is a diagram for explaining the effect of the present invention.

【図3】本発明を適用した別の実施例の半導体装置の構
造を示す図である。
FIG. 3 is a diagram showing a structure of a semiconductor device of another embodiment to which the present invention is applied.

【図4】本発明の効果を説明するための図である。FIG. 4 is a diagram for explaining the effect of the present invention.

【符号の説明】[Explanation of symbols]

11 InP基板 12 ノンドープIn0 . 5 2 Al0 . 4 7 As層 13 ノンドープIn0 . 5 3 Ga0 . 4 7 As層 14 ノンドープIn0 . 5 2 Al0 . 4 7 As層 15 SiドープIn0 . 5 2 Al0 . 4 7 As層 16 ノンドープIn0 . 5 2 Al0 . 4 7 As層 17 SiドープIn0 . 5 3 Ga0 . 4 7 As層 18 ソース電極 18a ソース電極(モリブデン) 18b ソース電極(チタン) 18c ソース電極(白金) 18d ソース電極(金) 19 ドレイン電極 19a ドレイン電極(モリブデン) 19b ドレイン電極(チタン) 19c ドレイン電極(白金) 19d ドレイン電極(金) 20 ゲート電極 31 InP基板 32 ノンドープIn0 . 5 2 Al0 . 4 7 As層 33 ノンドープIn0 . 5 3 Ga0 . 4 7 As層 34 ノンドープIn0 . 5 2 Al0 . 4 7 As層 35 SiドープIn0 . 5 2 Al0 . 4 7 As層 36 ノンドープIn0 . 5 2 Al0 . 4 7 As層 37 SiドープIn0 . 5 3 Al0 . 4 7 As層 38 SIドープIn0 . 5 3 Ga0 . 4 7 As層 39 ソース電極 39a ソース電極(モリブデン) 39b ソース電極(チタン) 39c ソース電極(白金) 39d ソース電極(金) 40 ソース電極 40a ドレイン電極(モリブデン) 40b ドレイン電極(チタン) 40c ドレイン電極(白金) 40d ドレイン電極(金) 41 ゲート電極11 InP substrate 12 doped In 0. 5 2 Al 0. 4 7 As layer 13 doped In 0. 5 3 Ga 0. 4 7 As layer 14 doped In 0. 5 2 Al 0. 4 7 As layer 15 Si doped In 0 . 5 2 Al 0. 4 7 As layer 16 doped In 0. 5 2 Al 0. 4 7 As layer 17 Si doped In 0. 5 3 Ga 0. 4 7 As layer 18 source electrode 18a source electrode (molybdenum) 18b source Electrode (titanium) 18c Source electrode (platinum) 18d Source electrode (gold) 19 Drain electrode 19a Drain electrode (molybdenum) 19b Drain electrode (titanium) 19c Drain electrode (platinum) 19d Drain electrode (gold) 20 Gate electrode 31 InP substrate 32 doped In 0. 5 2 Al 0. 4 7 As layer 33 doped In 0. 5 3 Ga 0. 4 7 As layer 34 doped In 0. 5 2 Al 0. 4 7 As layer 35 Si doped In 0. 5 2 Al 0. 4 7 As layer 36 doped In 0. 5 2 Al 0. 4 7 As layer 37 Si doped In 0. 5 3 Al 0. 4 7 As layers 38 SI-doped In 0. 5 3 Ga 0. 4 7 As layer 39 source electrode 39a source electrode (molybdenum) 39 b a source electrode (titanium) 39c source electrode (platinum) 39d source electrode (gold) 40 source electrode 40a drain electrode (molybdenum) 40b drain electrode (Titanium) 40c Drain electrode (platinum) 40d Drain electrode (gold) 41 Gate electrode

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/43 ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI technical display location H01L 29/43

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上に設けられた金属が活性層
と電気的接触をとっているオ−ミック電極に於いて、該
オーミック電極金属が融点が1200℃以上の高融点金
属を最下層とした少なくとも1層以上の積層構造からな
ることを特徴とするオーミック電極。
1. In an ohmic electrode in which a metal provided on a semiconductor substrate is in electrical contact with an active layer, the ohmic electrode metal is a refractory metal having a melting point of 1200 ° C. or higher as a lowermost layer. An ohmic electrode having a laminated structure of at least one layer.
【請求項2】 高融点金属が、Mo,Cr,Pt,P
d,Ni,Re,Os,Ta,Nb,Ir,Ru,Rh
の中のいずれか1つまたは複数の金属であることを特徴
とする請求項1記載のオーミック電極。
2. The refractory metal is Mo, Cr, Pt, P.
d, Ni, Re, Os, Ta, Nb, Ir, Ru, Rh
The ohmic electrode according to claim 1, wherein the ohmic electrode is any one or a plurality of the metals.
JP5215757A 1993-08-31 1993-08-31 Ohmic electrode Expired - Fee Related JP2630208B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5215757A JP2630208B2 (en) 1993-08-31 1993-08-31 Ohmic electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5215757A JP2630208B2 (en) 1993-08-31 1993-08-31 Ohmic electrode

Publications (2)

Publication Number Publication Date
JPH0766391A true JPH0766391A (en) 1995-03-10
JP2630208B2 JP2630208B2 (en) 1997-07-16

Family

ID=16677729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5215757A Expired - Fee Related JP2630208B2 (en) 1993-08-31 1993-08-31 Ohmic electrode

Country Status (1)

Country Link
JP (1) JP2630208B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5693964A (en) * 1995-07-31 1997-12-02 Matsushita Electronics Corporation Field-effect transistor and fabrication method
WO1998025310A1 (en) * 1996-12-06 1998-06-11 Raytheon Ti Systems, Inc. GATE ELECTRODE FOR GaAs FET

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5698877A (en) * 1980-01-08 1981-08-08 Mitsubishi Electric Corp Gaas field effect transistor
JPS5877259A (en) * 1981-11-04 1983-05-10 Hitachi Ltd Semiconductor device
JPS61187364A (en) * 1985-02-15 1986-08-21 Hitachi Ltd Ohmic electrode
JPS61256766A (en) * 1985-05-10 1986-11-14 Hitachi Ltd Electrode for compound semiconductor
JPS631065A (en) * 1986-06-20 1988-01-06 Matsushita Electronics Corp Manufacture of schottky barrier diode
JPH01145856A (en) * 1987-12-02 1989-06-07 Hitachi Ltd Electrode for compound semiconductor

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5698877A (en) * 1980-01-08 1981-08-08 Mitsubishi Electric Corp Gaas field effect transistor
JPS5877259A (en) * 1981-11-04 1983-05-10 Hitachi Ltd Semiconductor device
JPS61187364A (en) * 1985-02-15 1986-08-21 Hitachi Ltd Ohmic electrode
JPS61256766A (en) * 1985-05-10 1986-11-14 Hitachi Ltd Electrode for compound semiconductor
JPS631065A (en) * 1986-06-20 1988-01-06 Matsushita Electronics Corp Manufacture of schottky barrier diode
JPH01145856A (en) * 1987-12-02 1989-06-07 Hitachi Ltd Electrode for compound semiconductor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5693964A (en) * 1995-07-31 1997-12-02 Matsushita Electronics Corporation Field-effect transistor and fabrication method
WO1998025310A1 (en) * 1996-12-06 1998-06-11 Raytheon Ti Systems, Inc. GATE ELECTRODE FOR GaAs FET

Also Published As

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