JPH0766328A - Heat sink for semiconductor device - Google Patents
Heat sink for semiconductor deviceInfo
- Publication number
- JPH0766328A JPH0766328A JP22781293A JP22781293A JPH0766328A JP H0766328 A JPH0766328 A JP H0766328A JP 22781293 A JP22781293 A JP 22781293A JP 22781293 A JP22781293 A JP 22781293A JP H0766328 A JPH0766328 A JP H0766328A
- Authority
- JP
- Japan
- Prior art keywords
- heat sink
- resin
- semiconductor
- semiconductor device
- dissipation plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＩＣやＬＳＩ等の半導
体を搭載する放熱板の改良に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a heat sink on which a semiconductor such as an IC or LSI is mounted.
【０００２】[0002]
【従来の技術】従来、図５に示すように、半導体装置
は、放熱板１の周縁部をリード２に接着剤３で接着し、
半導体Ｓを載せて接着剤４で接着し、ボンディングワイ
ヤＷでリード２と半導体Ｓを接続して、樹脂５で封止し
ている。放熱板１は、通常Ｃｕ系金属素材から成り、Ａ
ｇやＮｉメッキを施したものもある。また、半導体装置
によっては、図６に示すように、放熱板１の底面６ａを
樹脂５から露出させて封止するものもある。2. Description of the Related Art Conventionally, as shown in FIG. 5, in a semiconductor device, a peripheral edge of a heat sink 1 is attached to a lead 2 with an adhesive 3,
The semiconductor S is placed and bonded with the adhesive 4, the lead 2 and the semiconductor S are connected by the bonding wire W, and the resin 5 is sealed. The heat sink 1 is usually made of a Cu-based metal material,
Some are plated with g or Ni. Further, depending on the semiconductor device, as shown in FIG. 6, the bottom surface 6a of the heat sink 1 is exposed from the resin 5 and sealed.
【０００３】[0003]
【発明が解決しようとする課題】上記従来の放熱板１
は、封止樹脂５との接着力が弱く、密着しないので、耐
湿性が低下したり、熱サイクルで樹脂にクラックが生じ
るという問題がある。特に、半導体装置における樹脂パ
ッケージが益々薄型化される傾向にあるため、放熱板と
樹脂との密着性の確保が重要性を増している。そこで、
本発明は、封止樹脂とよく密着して、耐湿性が高く、樹
脂クラックが生じない半導体装置用放熱板を提供するこ
とを課題としている。DISCLOSURE OF THE INVENTION The above conventional heat sink 1
Has a weak adhesive force with the sealing resin 5 and does not adhere to it, so that there is a problem that the moisture resistance is lowered or cracks are generated in the resin during a thermal cycle. Particularly, since the resin package in the semiconductor device tends to be made thinner, it is becoming more important to secure the adhesion between the heat sink and the resin. Therefore,
An object of the present invention is to provide a heat dissipation plate for a semiconductor device, which is well adhered to a sealing resin, has high moisture resistance, and does not cause resin cracks.
【０００４】[0004]
【課題を解決するための手段】上記課題を解決するた
め、本発明においては、半導体Ｓを搭載し、周縁部がリ
ード１２に接着され、半導体Ｓ及びリード１２と共に樹
脂１５にて封止される半導体装置用放熱板１１におい
て、封止樹脂１５との接合部となる表面の全部又は一部
にＣｕＯ膜１７を形成した。また、ヒートシンクにアー
スをとる場合に、導電性を確保し、またＣｕＯ膜を形成
しないように、半導体Ｓの搭載部に、Ａｇメッキ１６を
施した。さらに、放熱板１１の底面にＮｉメッキ１８を
施し、この部分を露出させるようにした。In order to solve the above-mentioned problems, in the present invention, a semiconductor S is mounted, the peripheral portion is adhered to the lead 12, and the semiconductor S and the lead 12 are sealed with a resin 15. In the heat dissipation plate 11 for a semiconductor device, the CuO film 17 was formed on all or part of the surface to be a joint with the sealing resin 15. Further, when the heat sink is grounded, Ag mounting 16 is applied to the mounting portion of the semiconductor S so as to ensure conductivity and not form the CuO film. Further, Ni plating 18 was applied to the bottom surface of the heat dissipation plate 11 to expose this portion.
【０００５】[0005]
【作用】本発明の放熱板１１は、封止樹脂１５との接合
面となる表面にＣｕＯ膜１７を形成したので、樹脂１５
との食い付きがよく、密着するので、耐湿性が高く、熱
サイクルによっても樹脂のクラックが生じない。Ａｇメ
ッキ１６を施した場合、ヒートシンクにアースをとるな
ど必要なときにはＣｕＯ膜の形成を妨げて半導体Ｓの搭
載部の導電性が確保される。底面にＮｉメッキ１８を施
すと、底面を露出させて樹脂封止する際の樹脂バリを除
去し易くなる。In the heat sink 11 of the present invention, the CuO film 17 is formed on the surface to be joined to the sealing resin 15.
Since it has a good bite with and adheres to it, it has high moisture resistance and does not crack the resin even during thermal cycling. When the Ag plating 16 is applied, the formation of the CuO film is hindered when necessary such as grounding the heat sink to ensure the conductivity of the mounting portion of the semiconductor S. The Ni plating 18 on the bottom surface makes it easier to remove the resin burr when the bottom surface is exposed and the resin is sealed.
【０００６】[0006]
【実施例】本発明の実施例を図面について説明する。図
１は半導体装置の縦断面図、図２は放熱板の一部拡大断
面図、図３は他の実施例の半導体装置の縦断面図、図４
は放熱板の一部拡大断面図である。図１において、１１
は半導体Ｓを載せる放熱板である。半導体Ｓは接着剤１
３で放熱板１１に接着される。また、放熱板１１の周縁
部は接着剤１４でリード１２に接着される。接着剤１３
は、従来同様、放熱板１１とリード１２とを絶縁する。
接着剤１４は導電性を有する。リード１２はボンディン
グワイヤＷで半導体Ｓと接続される。半導体Ｓ、放熱板
１１、リード１２の内側端部は樹脂１５で封止される。Embodiments of the present invention will be described with reference to the drawings. 1 is a vertical cross-sectional view of a semiconductor device, FIG. 2 is a partially enlarged cross-sectional view of a heat dissipation plate, FIG. 3 is a vertical cross-sectional view of a semiconductor device of another embodiment, and FIG.
FIG. 4 is a partially enlarged cross-sectional view of a heat sink. In FIG. 1, 11
Is a heat dissipation plate on which the semiconductor S is placed. Semiconductor S is adhesive 1
It is adhered to the heat sink 11 at 3. Further, the peripheral portion of the heat dissipation plate 11 is adhered to the leads 12 with an adhesive 14. Adhesive 13
Insulates the heat sink 11 and the lead 12 as in the conventional case.
The adhesive 14 has conductivity. The lead 12 is connected to the semiconductor S by a bonding wire W. Inner end portions of the semiconductor S, the heat sink 11, and the leads 12 are sealed with resin 15.
【０００７】放熱板１１は、図２に示すように、矩形板
状のＣｕ系金属から成る。放熱板１１の上面１１ａに
は、Ａｇメッキ１６が施されている。また、放熱板１１
の側面１１ｂ及び底面１１ｃには、ＣｕＯ膜１７が形成
されている。Ａｇメッキ１６は、ヒートシンクにアース
をとる場合に、導電性を確保してＣｕＯ膜の形成を阻止
する。As shown in FIG. 2, the heat dissipation plate 11 is made of a rectangular plate-shaped Cu-based metal. The upper surface 11 a of the heat dissipation plate 11 is plated with Ag. In addition, the heat sink 11
A CuO film 17 is formed on the side surface 11b and the bottom surface 11c. When the heat sink is grounded, the Ag plating 16 ensures conductivity and prevents formation of the CuO film.
【０００８】この半導体装置の放熱板１１は、封止樹脂
１５との接触面にＣｕＯ膜１７が形成されているので、
樹脂１５に対する食い付きがよく、密着するので、耐湿
性が高く、熱サイクルによっても樹脂のクラックが生じ
ない。なお、放熱板１１の上面１１ａにＡｇメッキ１６
を必要としない場合には、ＣｕＯ膜１７を形成すること
とし、同様に樹脂１５に対する上面１１ａの密着性を高
めることができる。Since the heat dissipation plate 11 of this semiconductor device has the CuO film 17 formed on the contact surface with the sealing resin 15,
Since the resin 15 has a good biting property and adheres well, it has high moisture resistance and does not crack the resin even by a thermal cycle. In addition, the Ag plating 16 is provided on the upper surface 11a of the heat dissipation plate 11.
When it is not necessary to form the CuO film 17, the adhesion of the upper surface 11a to the resin 15 can be similarly enhanced.
【０００９】他の実施例における放熱板１１は、図３に
示すように、底面１１ｃが樹脂１５から露出した状態で
封止されている。そして、図４に示すように、放熱板１
１の上面１１ａにはＡｇメッキ１６が施されており、側
面１１ｂにはＣｕＯ膜１７が形成されている。この放熱
板１１の底面１１ｃには、Ｎｉメッキ１８が施されてい
る。Ｎｉメッキ１８は、底面１１ｃからはみ出た樹脂バ
リを除去し易くする。As shown in FIG. 3, the heat sink 11 in another embodiment is sealed with the bottom surface 11c exposed from the resin 15. Then, as shown in FIG. 4, the heat sink 1
The upper surface 11a of No. 1 is plated with Ag 16 and the side surface 11b is provided with a CuO film 17. A Ni plating 18 is applied to the bottom surface 11c of the heat dissipation plate 11. The Ni plating 18 facilitates removal of the resin burr protruding from the bottom surface 11c.
【００１０】[0010]
【発明の効果】以上のように、本発明は、半導体Ｓを搭
載し、周縁部がリード１２に接着され、半導体Ｓ及びリ
ード１２と共に樹脂１５にて封止される半導体装置用放
熱板１１において、封止樹脂１５との接合部となる表面
の全部又は一部にＣｕＯ１７膜を形成し、あるいは、放
熱板の半導体Ｓの搭載部に導電性を確保すると共にＣｕ
Ｏ膜が形成されないようにＡｇメッキ１６を施し、さら
に放熱板１１の底面にＮｉメッキ１８を施し、この部分
を露出させるようにしたため、放熱板と樹脂が密着し、
耐湿性が高く、樹脂のクラックを防止することができる
という効果を有する。特に、半導体装置における樹脂パ
ッケージが益々薄型化される傾向にあり、放熱板と樹脂
との密着性の確保が重要性を増している現状において、
本発明の意義は大きい。As described above, according to the present invention, in the heat dissipation plate 11 for a semiconductor device, the semiconductor S is mounted, the peripheral portion is adhered to the lead 12, and the semiconductor S and the lead 12 are sealed with the resin 15 together. , A CuO17 film is formed on all or part of the surface to be joined to the sealing resin 15, or conductivity is ensured in the mounting portion of the semiconductor S of the heat dissipation plate and Cu
Since Ag plating 16 is applied so that the O film is not formed and Ni plating 18 is applied on the bottom surface of the heat dissipation plate 11 to expose this portion, the heat dissipation plate and the resin are in close contact,
It has high moisture resistance and has an effect that cracks of the resin can be prevented. In particular, in the current situation where the resin package in a semiconductor device tends to be made thinner and thinner, and securing the adhesiveness between the heat sink and the resin is becoming more important.
The significance of the present invention is great.
【図１】半導体装置の縦断面図である。FIG. 1 is a vertical sectional view of a semiconductor device.
【図２】放熱板の一部拡大断面図である。FIG. 2 is a partially enlarged cross-sectional view of a heat dissipation plate.
【図３】他の実施例の半導体装置の縦断面図である。FIG. 3 is a vertical cross-sectional view of a semiconductor device of another embodiment.
【図４】放熱板の一部拡大断面図である。FIG. 4 is a partially enlarged cross-sectional view of a heat dissipation plate.
【図５】従来の半導体装置の縦断面図である。FIG. 5 is a vertical cross-sectional view of a conventional semiconductor device.
【図６】従来の他の半導体装置の縦断面図である。FIG. 6 is a vertical cross-sectional view of another conventional semiconductor device.
１１ 放熱板 １２ リード １５ 樹脂 １６ Ａｇメッキ １７ Ｃｕ膜 １８ Ｎｉメッキ Ｓ 半導体 11 Heat sink 12 Lead 15 Resin 16 Ag plating 17 Cu film 18 Ni plating S Semiconductor
Claims (3)
され、半導体及びリードと共に樹脂封止される半導体装
置用放熱板において、表面の封止樹脂との接合面の全部
又は一部にＣｕＯ膜が形成されていることを特徴とする
半導体装置用放熱板。1. A heat dissipation plate for a semiconductor device, in which a semiconductor is mounted, a peripheral portion of which is adhered to a lead, and which is resin-sealed together with the semiconductor and the lead. A heat sink for a semiconductor device, wherein a film is formed.
に、ヒートシンクにアースをとる場合に導電性を確保す
ると共にＣｕＯ膜を形成しないようにＡｇメッキが施さ
れていることを特徴とする半導体装置用放熱板。2. The semiconductor mounting portion of the heat dissipation plate according to claim 1, wherein the semiconductor mounting portion is Ag-plated so as to ensure conductivity when a grounding is applied to the heat sink and not to form a CuO film. Heat sink for semiconductor devices.
ッキが施され、底面が前記封止樹脂から露出されること
を特徴とする半導体装置用放熱板。3. A heat dissipation plate for a semiconductor device, wherein the bottom surface of the heat dissipation plate according to claim 1 is plated with Ni, and the bottom surface is exposed from the sealing resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5227812A JP2562789B2 (en) | 1993-08-23 | 1993-08-23 | Heat sink for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5227812A JP2562789B2 (en) | 1993-08-23 | 1993-08-23 | Heat sink for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0766328A true JPH0766328A (en) | 1995-03-10 |
| JP2562789B2 JP2562789B2 (en) | 1996-12-11 |
Family
ID=16866770
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5227812A Expired - Fee Related JP2562789B2 (en) | 1993-08-23 | 1993-08-23 | Heat sink for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2562789B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998042022A1 (en) * | 1997-03-18 | 1998-09-24 | Seiko Epson Corporation | Semiconductor device and method of manufacturing same |
| KR100306230B1 (en) * | 1998-12-30 | 2001-12-17 | 마이클 디. 오브라이언 | Semiconductor package structure |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03236267A (en) * | 1990-02-14 | 1991-10-22 | Ibiden Co Ltd | Slug for forming semiconductor device |
-
1993
- 1993-08-23 JP JP5227812A patent/JP2562789B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03236267A (en) * | 1990-02-14 | 1991-10-22 | Ibiden Co Ltd | Slug for forming semiconductor device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998042022A1 (en) * | 1997-03-18 | 1998-09-24 | Seiko Epson Corporation | Semiconductor device and method of manufacturing same |
| US6166446A (en) * | 1997-03-18 | 2000-12-26 | Seiko Epson Corporation | Semiconductor device and fabrication process thereof |
| KR100306230B1 (en) * | 1998-12-30 | 2001-12-17 | 마이클 디. 오브라이언 | Semiconductor package structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2562789B2 (en) | 1996-12-11 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |