JPH0760860B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0760860B2 JPH0760860B2 JP61152934A JP15293486A JPH0760860B2 JP H0760860 B2 JPH0760860 B2 JP H0760860B2 JP 61152934 A JP61152934 A JP 61152934A JP 15293486 A JP15293486 A JP 15293486A JP H0760860 B2 JPH0760860 B2 JP H0760860B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- diffusion layer
- semiconductor device
- level
- ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 18
- 238000009792 diffusion process Methods 0.000 claims description 33
- 230000007257 malfunction Effects 0.000 description 13
- 230000005260 alpha ray Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔概要〕 本発明はMOSFET等の半導体装置において、 電極材やパツケージ材等から放射されるα線が半導体装
置に侵入することによって発生する電荷の捕獲量が多
く、誤動作を生じる問題点を解決するため、 １つのトランジスタを構成する拡散層部分を複数個に分
割し拡散層１個宛の上記電荷の捕獲量を少なくすること
により、 α線が侵入しても誤動作を未然に防止するようにしたも
のである。DETAILED DESCRIPTION OF THE INVENTION [Outline] In a semiconductor device such as a MOSFET, the present invention has a large amount of charge trapped when α rays emitted from an electrode material, a packaging material, etc. enter the semiconductor device, and malfunctions occur. In order to solve the above-mentioned problem, the diffusion layer portion constituting one transistor is divided into a plurality of portions to reduce the trapping amount of the electric charge addressed to one diffusion layer, so that a malfunction may occur even if α rays enter. This is to prevent it in advance.
本発明は半導体装置、特に、MOSFET等の半導体装置に関
する。MOSFETを例えばＤ−RAM（ダイナミツクRAM）のセ
ンスアンプとして用いた場合、前記電荷の捕獲量が多い
と誤動作を生じる。そこで、電荷の捕獲量が少なく、常
に正常動作を行ない得る半導体装置が必要とされる。The present invention relates to a semiconductor device, and more particularly to a semiconductor device such as MOSFET. When the MOSFET is used as a sense amplifier of, for example, a D-RAM (dynamic RAM), a malfunction occurs when the amount of trapped charge is large. Therefore, there is a need for a semiconductor device that has a small amount of trapped charges and can always perform a normal operation.
〔従来の技術〕 第４図（Ａ），（Ｂ）は夫々従来の半導体装置の一例の
平面図及びそのＢ−Ｂ線に沿った断面図を示す。同図
中、１はゲート電極、２は拡散層（ドレイン電極及びソ
ース電極を構成する）、３は酸化膜、４は基板、５は空
乏層である。[Prior Art] FIGS. 4A and 4B respectively show a plan view of an example of a conventional semiconductor device and a cross-sectional view taken along line BB thereof. In the figure, 1 is a gate electrode, 2 is a diffusion layer (which constitutes a drain electrode and a source electrode), 3 is an oxide film, 4 is a substrate, and 5 is a depletion layer.
ここで、基板４及び拡散層２が夫々異なる電位であると
空乏層５が形成されここにα線が侵入すると正孔及び電
子を生じる。ところで、一般に、半導体装置を構成する
電極材，配線材，絶覆材，被膜材，パッケージ材，封止
材等からはα線が放射されるが、第４図（Ｂ）に示すよ
うにこのα線６が半導体チップに侵入すると空乏層５内
で発生した正孔は電界に沿って基板に放出される一方、
空乏層５内で発生した電子は拡散層２へ引かれる。この
電荷の拡散層２への捕獲により拡散層２の電位は降下
し、この場合α線６が空乏層５を通過する距離l1が長い
程捕獲電荷量が多くなって拡散層２の電位降下が大きく
なる。Here, when the substrate 4 and the diffusion layer 2 have different potentials, a depletion layer 5 is formed, and when α rays enter there, holes and electrons are generated. By the way, in general, α rays are radiated from the electrode material, wiring material, covering material, coating material, package material, encapsulating material, etc., which constitute the semiconductor device, but as shown in FIG. When the α-ray 6 enters the semiconductor chip, the holes generated in the depletion layer 5 are emitted to the substrate along with the electric field,
The electrons generated in the depletion layer 5 are attracted to the diffusion layer 2. The potential of the diffusion layer 2 drops due to the trapping of the charges in the diffusion layer 2. In this case, the longer the distance l 1 through which the α-ray 6 passes through the depletion layer 5, the larger the amount of trapped charges and the lowering of the potential of the diffusion layer 2. Grows larger.
第５図（Ａ），（Ｂ）は第４図に示す従来の半導体装置
をＤ−RAMのセンスアンプに適用した場合の回路図及び
その平面図を示す。同図中、71,72,73はセンスアンプ
で、例えばセンスアンプ71はＮチャンネルトランジスタ
8a,8b及びＰチャンネルトランジスタ8c,8dにて構成され
ている。91,92,93はセルアレイで、トランジスタ10及び
コンデンサ11にて構成されている。ここで、通常状態に
ある場合の従来の回路例（第５図）の動作を説明する。
第３図に示す如く、ワード線WLからの制御信号によりセ
ルアレイ91のトランジスタ10が時刻t1でオンとなりコン
デンサ11に蓄えられていた情報がビット線BLに現われ
る。第３図は、コンデンサ11に高レベルの電荷が蓄えら
れていた例であり、ビット線BLのレベルが上がってい
る。次に、制御線PSA,NSAからの制御信号によってセン
サアンプ71が時刻t2でセンス動作を開始し、ビット線BL
及び のレベルは増幅されて夫々Ｈレベル及びＬレベルの情報
が出力される。FIGS. 5 (A) and 5 (B) are a circuit diagram and a plan view thereof when the conventional semiconductor device shown in FIG. 4 is applied to a sense amplifier of D-RAM. In the figure, 7 1 , 7 2 , and 7 3 are sense amplifiers, for example, the sense amplifier 7 1 is an N-channel transistor.
8a, 8b and P-channel transistors 8c, 8d. 9 1 , 9 2 , and 9 3 are cell arrays, each of which includes a transistor 10 and a capacitor 11. Here, the operation of the conventional circuit example (FIG. 5) in the normal state will be described.
As shown in Figure 3, information that transistor 10 of the cell array 9 1 by a control signal from the word line WL is stored in the capacitor 11 turns on at time t 1 appears on the bit line BL. FIG. 3 shows an example in which a high level of electric charge is stored in the capacitor 11, and the level of the bit line BL has risen. Next, the sensor amplifier 7 1 starts the sensing operation at time t 2 by the control signal from the control lines PSA and NSA, and the bit line BL
as well as Is amplified and the information of H level and L level is output respectively.
次にα線が侵入して誤動作を生じる場合の第５図の動作
を説明する。α線が例えばドレイン電極の拡散層２に時
刻t1からt3の間に侵入すると前述のように電子が捕獲さ
れ拡散層２の電位降下がおこる。そして、第６図に示す
如く、制御線PSA,NSAからの制御信号を供給する以前に
時刻t3からビット線BL及び の出力レベルは正常時とは逆のレベルとなり、本来のレ
ベルとは逆のレベルの情報が出力される問題点があっ
た。これは、α線によって発生した電子の捕獲量が少な
い場合は特に問題ないが、その電子の量が多い場合は、
上記の如き誤動作を生じる。Next, the operation of FIG. 5 when the .alpha.-ray enters to cause a malfunction will be described. When α rays enter the diffusion layer 2 of the drain electrode, for example, between times t 1 and t 3 , the electrons are captured and the potential of the diffusion layer 2 drops as described above. Then, as shown in FIG. 6, the control lines PSA, the bit lines BL and from time t 3 before supplying the control signal from the NSA The output level of is opposite to the normal level, and there is a problem that information of the level opposite to the original level is output. This is not a problem when the amount of captured electrons generated by α rays is small, but when the amount of electrons is large,
The above malfunction occurs.
本発明になる半導体装置は、第１図に示す如く、α線６
の粒子が半導体チップに侵入した際に発生する電荷によ
って誤動作に至る回路を構成する一のトランジスタの拡
散層部分を複数個（131,132）に分割して設けてなる。The semiconductor device according to the present invention, as shown in FIG.
Is formed by dividing a diffusion layer portion of one transistor constituting a circuit that causes malfunction due to electric charges generated when the particles enter the semiconductor chip into a plurality (13 1 , 13 2 ).
一つのトランジスタを構成する拡散層部分を複数個に分
割したので拡散層131,132夫々１個宛の面積は従来のも
のに比して小さく、α線６が空乏層162を通過する距離l
2は従来のものに比して短かく、電荷捕獲量が従来のも
のに比して少ないため誤動作に至らない。Since the diffusion layer portion constituting one transistor is divided into a plurality of portions, the area for each of the diffusion layers 13 1 and 13 2 is smaller than that of the conventional one, and the α ray 6 passes through the depletion layer 16 2 . Distance l
2 is shorter than the conventional one, and the amount of charge trapped is smaller than the conventional one, so that no malfunction occurs.
第１図（Ａ），（Ｂ）は夫々本発明の半導体装置の一実
施例の平面図及びそのＢ−Ｂ線に沿った断面図を示す。
同図中、12はゲート電極、131,132は拡散層（夫々がド
レイン電極及びソース電極を構成する）で、第４図に示
す本来の１個の拡散層２を例えば２個に分割したもの
で、本発明の要部をなす。14は酸化膜、15は基板、161,
162は空乏層である。1 (A) and 1 (B) are respectively a plan view and a cross-sectional view taken along the line BB of an embodiment of the semiconductor device of the present invention.
In the figure, 12 is a gate electrode, and 13 1 and 13 2 are diffusion layers (each of which constitutes a drain electrode and a source electrode), and one original diffusion layer 2 shown in FIG. 4 is divided into, for example, two. This is the main part of the present invention. 14 is an oxide film, 15 is a substrate, 16 1 ,
16 2 is a depletion layer.
このように、１つのトランジスタを構成する拡散層部分
を複数に分割したので、拡散層131,132夫々１個宛の面
積は第４図示の従来装置の拡散層２の面積に比して小さ
く、これにより、α線６が空乏層162を通過する距離l2
は従来装置の距離l2に比して短かい。従って、電荷捕獲
量が従来装置に比して少なく、拡散層の電位降下が小さ
いため誤動作に至らない。As described above, since the diffusion layer portion forming one transistor is divided into a plurality of portions, the area for each one of the diffusion layers 13 1 and 13 2 is larger than the area of the diffusion layer 2 of the conventional device shown in FIG. small, thereby, the distance α line 6 passes through the depletion layer 16 2 l 2
Is shorter than the distance l 2 of the conventional device. Therefore, the amount of charge trapped is smaller than that in the conventional device, and the potential drop in the diffusion layer is small, so that no malfunction occurs.
第２図（Ａ），（Ｂ）は第１図に示す本発明になる半導
体装置をＤ−RAMのセンスアンプに適用した場合の回路
図及びその平面図を示し、同図中、第５図と同一構成部
分には同一番号を付す。同図中、171,172,173はセンス
アンプで、例えばセンスアンプ171はトランジスタ部18a
（拡散層131）,18b（拡散層132）からなるＮチャンネル
トランジスタ18、トランジスタ部19a（拡散層131）,19b
（拡散層132）からなるＮチャンネルトランジスタ19、
トランジスタ部20a,20bからなるＰチャンネルトランジ
スタ20、トランジスタ部21a,21bからなるＰチャンネル
トランジスタ21にて構成されている。2 (A) and 2 (B) are a circuit diagram and a plan view of the semiconductor device according to the present invention shown in FIG. 1 when applied to a sense amplifier of a D-RAM, and FIG. The same numbers are given to the same components as. In the figure, 17 1 , 17 2 and 17 3 are sense amplifiers, for example, the sense amplifier 17 1 is a transistor section 18a.
N-channel transistor 18 composed of (diffusion layers 13 1 ) and 18b (diffusion layers 13 2 ), and transistor portions 19a (diffusion layers 13 1 ) and 19b
An N-channel transistor 19 composed of (diffusion layer 13 2 ),
The P-channel transistor 20 is composed of the transistor portions 20a and 20b, and the P-channel transistor 21 is composed of the transistor portions 21a and 21b.
ここで、従来装置と略同様に、第３図に示す如く、ワー
ド線WLからの制御信号によりセルアレイ91のトランジス
タが時刻t1でオンとなり、次に、制御線PSA,NSAからの
制御信号によってセンスアンプ171が時刻t2でセンス動
作を開始し、ビット線BL及び のレベルは増幅されて夫々Ｈレベル及びＬレベルの情報
が出力される。ここで、前述のようにα線が侵入しても
拡散層の電位降下が従来装置に比して小さいので、従来
装置のような本来のレベルとは逆のレベルの情報が出力
されるような誤動作を生じることはない。Here, as in the conventional device, as shown in FIG. 3, the control signal from the word line WL turns on the transistor of the cell array 9 1 at time t 1 , and then the control signals from the control lines PSA and NSA. By this, the sense amplifier 17 1 starts the sensing operation at time t 2 , and the bit line BL and Is amplified and the information of H level and L level is output respectively. Here, as described above, the potential drop in the diffusion layer is smaller than that of the conventional device even when the α-ray enters, so that the information of the level opposite to the original level as in the conventional device is output. No malfunction will occur.
この場合、一般に、α線は数10時間毎に１個放射される
と考えられるので、本実施例のように拡散層を例えば２
個（131,132）設けてもその１個宛の電荷捕獲量が少な
ければ、α線の放射間隔に比して極めて短時間に動作す
るＤ−RAMに適用した場合に上記の如き誤動作を防止し
得る。In this case, in general, one α ray is considered to be emitted every several tens of hours, and therefore, as in the present embodiment, a diffusion layer such as 2 is used.
Even if a plurality of (13 1 , 13 2 ) are provided, if the amount of charge trapped to that one is small, the above-mentioned malfunction occurs when applied to a D-RAM that operates in an extremely short time compared to the radiation interval of α rays. Can be prevented.
なお、第１図（Ａ），（Ｂ）に示す実施例の如く、ソー
ス電極Ｓ及びドレイン電極Ｄの両方を拡散層131,132と
して独立に設けてもよいが、特に、α線６の注入によっ
て発生する電荷によって回路の誤動作を引き起こす力の
拡散層（ドレイン電極）みを拡散層131,132として独立
に設け、他方の拡散層（ソース電極）を独立せずに設け
てもよい。Note that both the source electrode S and the drain electrode D may be independently provided as the diffusion layers 13 1 and 13 2 as in the embodiment shown in FIGS. Even if only the diffusion layers (drain electrodes) of the force that causes the malfunction of the circuit due to the charge generated by the injection of the charges are separately provided as the diffusion layers 13 1 and 13 2 and the other diffusion layer (source electrode) is not provided independently. Good.
本発明によれば、一のトランジスタを構成する拡散層部
分を複数個に分割して設けたため、α線が空乏層を通過
する距離は従来のものに比して短かくなり、これによ
り、α線が半導体チップに侵入した際の電荷捕獲量は従
来のものに比して少なくなって拡散層の電位降下が小さ
くなり、もって、例えばＤ−RAMのセンスアンプ等に適
用した場合、従来のような誤動作を生じることはなく、
動作信頼性を向上し得る等の特長を有する。According to the present invention, since the diffusion layer portion that constitutes one transistor is provided by being divided into a plurality of portions, the distance that the α-ray passes through the depletion layer becomes shorter than that of the conventional one. The amount of charge trapped when a line invades a semiconductor chip is smaller than that of the conventional one, and the potential drop in the diffusion layer is small. Therefore, when applied to a sense amplifier of D-RAM, for example, it is as conventional. Without causing any malfunction,
It has features such as improved operational reliability.
第１図は本発明装置の一実施例の平面図及び断面図、 第２図は本発明装置をＤ−RAMのセンスアンプに適用し
た場合の回路図及び平面図、 第３図はＤ−RAMの正常状態時の動作特性図、 第４図は従来装置の一例の平面図及び断面図、 第５図は従来装置をＤ−RAMのセンスアンプに適用した
場合の回路図及び平面図、 第６図はＤ−RAMの誤動作時の動作特性図である。 図中において、 ６はα線、 91,92,93はセルアレイ、 12はゲート電極、 131,132は拡散層、 14は酸化膜、 15は基板、 161,162は空乏層、 171,172,173はセンスアンプ、 18,19,20,21はトランジスタ、 18a,18b,19a,19b,20a,20b,21a,21bはトランジスタ部、 Ｄはドレイン電極、 Ｓはソース電極である。FIG. 1 is a plan view and a sectional view of an embodiment of the present invention device, FIG. 2 is a circuit diagram and a plan view when the present invention device is applied to a sense amplifier of a D-RAM, and FIG. 3 is a D-RAM. FIG. 4 is a plan view and a sectional view of an example of a conventional device, FIG. 5 is a circuit diagram and a plan view when the conventional device is applied to a D-RAM sense amplifier, and FIG. The figure is an operation characteristic diagram when the D-RAM malfunctions. In the figure, 6 is an α ray, 9 1 , 9 2 and 9 3 are cell arrays, 12 is a gate electrode, 13 1 and 13 2 are diffusion layers, 14 is an oxide film, 15 is a substrate, and 16 1 and 16 2 are depleted. Layers, 17 1 , 17 2 , 17 3 are sense amplifiers, 18,19,20,21 are transistors, 18a, 18b, 19a, 19b, 20a, 20b, 21a, 21b are transistor parts, D is a drain electrode, S is S It is a source electrode.
Claims (1)
のトランジスタ（19）のドレインとが接続され、第１の
トランジスタ（18）のドレインと第２のトランジスタ
（19）のゲートとが接続され、第１のトランジスタ（1
8）のソースと第２のトランジスタ（19）のソースとが
接続されてなる一対のトランジスタ（18、19）を有する
半導体記憶装置のセンスアンプ回路（17）を含む半導体
装置において、 前記第１及び第２のトランジスタ（18、19）のそれぞれ
の拡散層部分を複数個（131、132）に分割して設けてな
ることを特徴とする半導体装置。1. A gate of the first transistor (18) and a second gate of the first transistor (18).
Of the first transistor (19) is connected to the drain of the first transistor (19), and the drain of the first transistor (18) is connected to the gate of the second transistor (19).
A semiconductor device including a sense amplifier circuit (17) of a semiconductor memory device having a pair of transistors (18, 19) in which a source of 8) and a source of a second transistor (19) are connected to each other. A semiconductor device characterized in that each diffusion layer portion of the second transistor (18, 19) is divided into a plurality of portions (13 1 , 13 2 ).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61152934A JPH0760860B2 (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61152934A JPH0760860B2 (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS639143A JPS639143A (en) | 1988-01-14 |
| JPH0760860B2 true JPH0760860B2 (en) | 1995-06-28 |
Family
ID=15551338
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61152934A Expired - Lifetime JPH0760860B2 (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0760860B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007073709A (en) * | 2005-09-06 | 2007-03-22 | Nec Electronics Corp | Semiconductor device |
| JP2008085235A (en) * | 2006-09-29 | 2008-04-10 | Toshiba Corp | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS556133Y2 (en) * | 1971-09-15 | 1980-02-12 |
-
1986
- 1986-06-30 JP JP61152934A patent/JPH0760860B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS639143A (en) | 1988-01-14 |
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