JPH01293670A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To realize a highly integrated device by effectively utilizing a blank part between metal wiring layers by arranging a control gate pair and a floating gate pair along two crossed directions at the upper part of a substrate where impurity diffusion regions for a source and a drain have been formed. CONSTITUTION:Control gates 2 are formed in the X direction at the upper part of a substrate 10; control gates 12 are formed in the Y direction at the upper part of the gates 2; floating gates 11 are formed at the lower part of the gates 2 via an insulator layer 7. The floating gates 11 are formed at the lower part of the gates 12 via the layer 7. For a write operation and a readout operation of memory transistors arranged in the X and Y directions, a high voltage is applied to the gates 12.1 in N-type impurity diffusion regions 3, 1 on the side of a drain of floating gates 1 and a low voltage is applied to the regions 3 on the side of other drains and to the gates 12.2; then, the write operation is executed; when the low voltage is applied to the regions 3 and the gates 12.2 in this manner, the readout operation is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to the structure of a nonvolatile semiconductor memory device for achieving high integration of memory cells.

[Prior Art] FIG. 4A is a partial plan view showing a conventional N-channel floating gate type nonvolatile semiconductor memory device, and FIG. 4B is a sectional view taken along the line IVB-IVB in FIG. 4A.

In the figure, control gates made of a conductive layer such as polycrystalline silicon are arranged above a P-type silicon substrate 10 at a predetermined distance from each other so as to extend in the direction indicated by the arrow X through an insulating layer 7. 2 is formed. Below this control gate 2, via an insulator layer 7,
Similarly, a floating gate 1 made of a conductive layer is formed. In the P-type silicon substrate 10 below the floating gate 1, an N-type impurity diffusion region 3 on the drain side and an N-type impurity diffusion region 4 on the source side are formed at intervals. The N-type impurity diffusion region 3 has a digging portion 3a under the floating gate 1, and the N-type impurity diffusion region 4 similarly has a digging portion 4a. The N-type impurity diffusion region 3 on the drain side is a contact hole 6
It is connected to a metal wiring layer 5 made of aluminum or the like via the metal wiring layer 5 . This metal wiring layer 5 is the control gate 2
They are formed at a predetermined distance from each other so as to extend in the direction indicated by the arrow Y and perpendicular to the arrow Y.

Next, the operation of this floating gate type nonvolatile semiconductor memory device will be explained. Here, charging the floating gate 1 with electrons will be referred to as "writing", and discharging electrons from the floating gate 1 will be referred to as "erasing".

First, in "writing", a high voltage is applied to one N-type impurity diffusion region 3 and one control gate 2 on the drain side, and the other N-type impurity diffusion regions 3 and control gates 2 are set to "Low" level. This is done by leaving things as they are. As a result, electrons with high energy generated in the channel region of one memory transistor selected in a matrix form cross the conduction band energy gap of the insulator layer 7 under the floating gate 1 and enter the floating gate 1. reach. In this way, "writing" is performed by charging the floating gate 1 with a negative charge. On the other hand, "erasing" means ultraviolet rays,
Alternatively, the electrons in the floating gate 1 may be emitted by irradiation with light having a wavelength close to that of ultraviolet light. Therefore, the threshold voltage of the memory transistor differs depending on the presence or absence of charge in the floating gate 1. Therefore, "reading" takes advantage of the fact that the amount of current flowing between the drain and source changes depending on the difference in threshold voltage, and this amount of current is amplified by a sense amplifier (not shown) connected to the metal arrangement layer 5. This is done by detecting the data and identifying the "write" and "erase" states.

By the way, in a conventional nonvolatile semiconductor memory device, as shown in FIG. 4A, one N-type impurity diffusion region 3 on the drain side
It is formed so as to constitute two memory transistors for each. This is because the N-type impurity diffusion region 4 on the source side, which is normally set at the substrate potential (ground potential), is shared and the distance between each memory transistor in the direction shown by arrow Y is reduced. Furthermore, the spacing between the metal wiring layers 5 in the direction indicated by the arrow X is wider than the spacing in the Y direction, and there are many regions where only the insulator layer 7 is formed. This is because it is difficult to pattern the metal wiring layer 5 stacked on the top layer. For example, in a nonvolatile semiconductor memory device with a capacity of 1 megabit, the technically possible minimum spacing is 1.0 μm between impurity diffusion regions and 1.0 μm between gates.
．． The distance between 5 μm metal wiring layers is approximately 2.0 μm. As is clear from this, the higher the layers are stacked on the semiconductor substrate, the wider the interval needs to be patterned. This is because the higher the layers are stacked, the larger the difference in level between the stacked layers becomes. For example, the metal wiring layer 5 is formed thicker, about 10,000 A, compared to about 2,000 to 3,000 A, which is the film thickness of the gate. There is a need to.

[Problems to be Solved by the Invention] Conventional nonvolatile semiconductor memory devices, particularly floating gate type nonvolatile semiconductor memory devices, are configured as described above, so it is necessary to reduce the distance between the metal wiring layers formed in the uppermost layer. It needed to be made as wide as possible. Therefore, no pattern is formed as an active region in the region between the metal wiring layers, resulting in a blank region, which has been an obstacle to achieving higher integration of nonvolatile semiconductor memory devices.

Further, in conventional nonvolatile semiconductor memory devices, as the memory capacity increases, the chip size increases, resulting in a decrease in yield and other problems, such as an increase in manufacturing costs.

Therefore, this invention was made to solve the above problems, and it is possible to effectively utilize the blank area between metal wiring layers, and to easily achieve high integration. The purpose of the present invention is to provide a semiconductor memory device that can perform the following steps.

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a semiconductor substrate having a main surface and having a predetermined impurity concentration of a certain conductivity type, a first conductor layer, and a second conductor layer. conductor layer, a first floating conductor layer, a second floating conductor layer, and one and other semiconductor regions having conductivity types opposite to that of the semiconductor substrate. The first conductor layer is formed so as to extend along the first direction above the main surface of the semiconductor substrate, and is insulated. The second conductor layer is formed above the main surface of the semiconductor substrate to extend along a second direction intersecting the first direction, and is insulated. Further, the first floating conductor layer is formed between the semiconductor substrate and the first conductor layer and is insulated. The second floating conductor layer is connected to the semiconductor substrate and the second floating conductor layer.
It is formed between the conductor layer and the conductor layer and is insulated. Further, one and the other semiconductor regions having conductivity types opposite to that of the semiconductor substrate are formed on the main surface of the semiconductor substrate spaced apart below the first floating conductor layer and the second floating conductor layer. has been done.

[Function] The semiconductor memory device according to the present invention includes a first conductor layer and a first floating conductor layer extending along a first direction;
It has a second conductor layer and a second floating conductor layer extending along a second direction intersecting the first direction. Further, below the first floating conductor layer and the second floating conductor layer, semiconductor regions having a conductivity type opposite to that of the semiconductor substrate, which are to become active regions, are formed at intervals.

Therefore, since the memory element can be formed along two directions that intersect the first direction and the second direction,
The range in which the area on the semiconductor substrate can be used as an active area increases. Therefore, a new area is provided in which a memory element is formed, making it possible to significantly increase the degree of integration of semiconductor memory devices.

[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. 1st
Figure A is a partial plan view showing an N-channel floating gate type nonvolatile semiconductor memory device according to the present invention;
Figure B is a cross-sectional view taken along line IB-IB in Figure 1A, and Figure 1C.
The figure is a sectional view taken along the line IC-IC in FIG. 1A.

In the figure, above the P-type silicon substrate 10, there is an arrow
Control gates 2 made of a conductive layer such as polycrystalline silicon are formed at a predetermined distance from each other so as to extend along the direction shown in FIG. Further, above the control gate 2, a control gate 12 is arranged at a predetermined interval with an insulating layer 7 interposed therebetween so as to extend in a direction perpendicular to the direction in which the control gate 2 extends, that is, in a direction indicated by an arrow Y. It is formed by separating the

Below the control gate 2, a floating gate 1 made of a conductive layer such as polycrystalline silicon is similarly formed along the direction indicated by arrow X with an insulating layer 7 interposed therebetween. A floating gate 11 is similarly formed below the control gate 12 along the direction indicated by the arrow Y with the insulator layer 7 interposed therebetween. Further, in the P-type silicon substrate 10 below the floating gate 1, an N-type impurity diffusion region 3 on the drain side is provided at a distance.
and a source side N-type impurity diffusion region 4 are formed. Similarly, below the floating gate 11, N-type impurity diffusion regions 3 and 4 are formed at intervals in the P-type silicon substrate 10.

In this case, the N-type impurity diffusion region 3 on the drain side has a digging portion 3 a under the floating gate 1 and a digging portion 3 b under the floating gate 11 . Further, the N-type impurity diffusion region 4 on the source side has a digging portion 4a under the floating gate 1 and a digging portion 4b under the floating gate 11. Furthermore, metal wiring layers 5 made of aluminum or the like are formed at a predetermined distance from each other so as to extend in the direction shown by arrow Y so as to be connected to the N-type impurity diffusion region 3 on the drain side via a contact hole 6. has been done.

Next, the operation of the nonvolatile semiconductor memory device according to the present invention will be explained. First, writing and reading of the memory transistors arranged in the direction indicated by the arrow
By applying the "Low" level voltage, the part 3b of the n-type impurity diffusion region on the drain side and the part 4b of the n-type impurity diffusion region on the source side are completely disconnected, so as mentioned above, This can be done in the same manner as before.

Writing and reading of memory transistors arranged along the direction indicated by arrow Y are performed by control gate 2.
This can be done similarly to a conventional memory transistor arranged along the direction indicated by arrow X by applying a voltage of 'Low', t, to all parts of the memory transistor.

That is, a high voltage is applied to one drain-side N-type impurity diffusion region 3 and one control gate 12, and a Low' level voltage is applied to the other drain-side N-type impurity diffusion region 3 and control gate 12. As a result, "writing" is performed to one memory transistor selected in a matrix.

Further, similarly to the above, "reading" is performed by selectively applying a low voltage to the N-type impurity diffusion region 3 and the control gate 12 on the drain side. Furthermore, "erasing" can be performed without any change from the conventional method.

In addition, in the above embodiment, the floating gate 1.11
is rectangular in plan view, but if it is possible to reduce the area of the contact hole 6 for connecting the N-type impurity diffusion region 3 on the drain side and the metal wiring layer 5, the second It may be formed as shown in the figure. That is, referring to FIG. 2, floating gates 1,
A floating gate may be formed having a shape in which a corner portion, which is a region where the distance between each adjacent one of the two regions is the smallest, is cut out to make an angle of 45° with the direction indicated by X or Y. Even if the floating gate is formed in this way, the same effects as those of the above-mentioned embodiments can be obtained, and higher integration can be achieved.

FIG. 3A is a partial plan view showing another embodiment of the nonvolatile semiconductor memory device of the present invention, and FIG. 3B is the mB-m of FIG. 3A.
It is a sectional view taken along the B line. Referring to these figures, a part of the insulator layer 7 formed between the floating gates 1 and 11 and the N-type impurity diffusion region 3 on the drain side is thinned so that the film thickness is several tens of amps. It is formed. In this way, the thickness of the insulator layer formed between the biting part 3a (or 3b) of the N-type impurity diffusion region on the drain side and the floating gate 1 (or 11) formed above it is determined. By making it thinner, the electrical operation performed therebetween may cause a tunneling effect to inject and emit electrons. As described above, the semiconductor memory device according to the present invention is based on the EPROM (Erasable Program
abke Read 0nly Memory)
In addition, as shown in FIGS. 3A and 3B, EEFROM (Electrically Erased Memory)
able and programmable R
(ead ONLY Memory).

Further, in the above embodiment, the control gate 12 was shown to be formed above the control gate 2, but it goes without saying that it may be formed below the control gate 2. Further, although the above-described embodiment shows an example using a P-type silicon substrate, a semiconductor memory device of the opposite conductivity type may be constructed using an N-type silicon substrate.

[Effects of the Invention] As described above, according to the present invention, the first conductor layer and the first floating conductor layer extend above the semiconductor substrate along the first direction, and the first conductor layer and the first floating conductor layer extend above the semiconductor substrate along the first direction. Since the semiconductor memory device is configured to have a second conductor layer and a second floating conductor layer extending along a second direction, semiconductor memory elements are formed along two intersecting directions. can be done.

Therefore, the area of a region to be an active region on the semiconductor substrate can be increased, and higher integration (approximately 10 to 50%) can be achieved compared to the conventional technology. Therefore, it is possible to configure a semiconductor memory device having a larger memory capacity with the same chip size, and there is an effect that manufacturing costs can be reduced.

[Brief explanation of the drawing]

FIG. 1A is a partial plan view showing a nonvolatile semiconductor memory device according to an embodiment of the present invention, and FIG. 1B is an IB-
A cross-sectional view along line IB, Figure 1C is TC-I in Figure 1A.
It is a sectional view taken along the C line. FIG. 2 is a partial plan view showing a nonvolatile semiconductor memory device according to another embodiment of the invention. FIG. 3A is a partial plan view showing an EEFROM which is a nonvolatile semiconductor memory device according to yet another embodiment of the present invention, and FIG.
It is a sectional view taken along the line I[[B-mB of Figure A. 4th A
The figure is a partial plan view showing a conventional nonvolatile semiconductor memory device.
FIG. 4B is a sectional view taken along the line IVB--IVB of FIG. 4A. In the figure, 1.11 is a floating gate, 2.1
2 is a control gate, 3.4 is an N-type impurity diffusion region, and 10 is a P-type silicon substrate. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] A semiconductor substrate having a main surface and having a predetermined impurity concentration of a certain conductivity type; an insulated second conductor layer formed above the main surface of the semiconductor substrate and extending along a second direction intersecting the first direction; , a first floating conductor layer formed between the semiconductor substrate and the first conductor layer and insulated; and a first floating conductor layer formed between the semiconductor substrate and the second conductor layer and insulated. the second
a floating conductor layer formed on the main surface of the semiconductor substrate at a distance below the first floating conductor layer and the second floating conductor layer; A semiconductor memory device comprising one semiconductor region and the other semiconductor region having a conductive type.