JPS639143A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS639143A JPS639143A JP61152934A JP15293486A JPS639143A JP S639143 A JPS639143 A JP S639143A JP 61152934 A JP61152934 A JP 61152934A JP 15293486 A JP15293486 A JP 15293486A JP S639143 A JPS639143 A JP S639143A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- rays
- transistor
- alpha
- parts
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 37
- 230000007257 malfunction Effects 0.000 claims description 13
- 230000005260 alpha ray Effects 0.000 claims description 6
- 239000002245 particle Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- OFHCOWSQAMBJIW-AVJTYSNKSA-N alfacalcidol Chemical compound C1(/[C@@H]2CC[C@@H]([C@]2(CCC1)C)[C@H](C)CCCC(C)C)=C\C=C1\C[C@@H](O)C[C@H](O)C1=C OFHCOWSQAMBJIW-AVJTYSNKSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Abstract
Description
【発明の詳細な説明】
(概要〕
本発明はMOSFET等の半導体装置において、電極材
やパッケージ材等から放射されるα線が半導体装置に侵
入することによって発生する電荷の捕獲量が多く、誤動
作を生じる問題点を解決するため、
1つのトランジスタを構成する拡散層部分を複数個に分
割して拡散層1個宛の上記電荷の捕獲量を少なくするこ
とにより、
α線が侵入しても誤動作を未然に防止するようにしたも
のである。Detailed Description of the Invention (Summary) The present invention provides a method for preventing malfunctions in semiconductor devices such as MOSFETs due to a large amount of captured charge generated when α rays emitted from electrode materials, package materials, etc. enter the semiconductor device. In order to solve the problem that occurs, the diffusion layer that makes up one transistor is divided into multiple parts to reduce the amount of charge captured by each diffusion layer, thereby preventing malfunction even if α rays enter. It is designed to prevent this from happening.
本発明は半導体装置、特に、MOSFET等の半導体装
置に関する。MOSFETを例えばD−RAM (ダイ
ナミックRAM)のセンスアンプとして用いた場合、前
記電荷の捕1ffiが多いと誤動作を生じる。そこで、
電荷の捕獲量が少なく、常に正常動作を行ない得る半導
体装置が必要とされる。The present invention relates to semiconductor devices, and particularly to semiconductor devices such as MOSFETs. When a MOSFET is used, for example, as a sense amplifier for a D-RAM (dynamic RAM), malfunctions occur if the amount of charge trapped 1ffi is large. Therefore,
There is a need for a semiconductor device that captures a small amount of charge and can always operate normally.
第4図(A)、(B)は夫々従来の半導体装置の一例の
平面図及びそのB−B線に沿った新面図を示す。同図中
、1はゲート電極、2は拡散層(ドレイン電極及びソー
ス電極を構成する)、3は酸化膜、4は基板、5は空乏
層であるっここで、基板4及び拡散層2が夫々光なる゛
電位であると空乏層5が形成されここにα線が侵入する
と正孔及び電子を生じる。ところで、一般に、半導体装
置を構成する電極材、!!i!線材、絶゛覆材。FIGS. 4(A) and 4(B) respectively show a plan view of an example of a conventional semiconductor device and a new view taken along the line BB. In the figure, 1 is a gate electrode, 2 is a diffusion layer (constituting a drain electrode and a source electrode), 3 is an oxide film, 4 is a substrate, and 5 is a depletion layer. When the potential is the same as that of light, a depletion layer 5 is formed, and when α rays enter there, holes and electrons are generated. By the way, in general, electrode materials that constitute semiconductor devices! ! i! Wire rod, continuous covering material.
被膜材、パッケージ材、封止材等からはα線が放射され
るが、第4図(8)に示すようにこのα線6が半導体チ
ップに侵入すると空乏層5内で発生した正孔は電界に沿
って基板に放出される一方、空乏層5内で発生した電子
は拡散層2へ引かれる。α rays are emitted from coating materials, packaging materials, sealing materials, etc., but as shown in FIG. 4 (8), when these α rays 6 enter the semiconductor chip, the holes generated in the depletion layer 5 are Electrons generated in the depletion layer 5 are drawn to the diffusion layer 2 while being emitted to the substrate along the electric field.
この電荷の拡散層2への捕獲により拡散層2の電位は降
下し、この場合α線6が空乏層5を通過する距離21が
長い程捕獲電荷吊が多くなって拡散層2の電位降下が大
きくなる。The potential of the diffusion layer 2 decreases due to the capture of this charge in the diffusion layer 2. In this case, the longer the distance 21 that the α ray 6 passes through the depletion layer 5, the more the trapped charge hangs, and the potential drop of the diffusion layer 2 decreases. growing.
第5図(A)、(B)は第4図に示す従来の半導体装置
をD−RAMのセンスアンプに適用した場合の回路図及
びその平面図を示す。同図中、7+ 、72.73はセ
ンスアンプで、例えばセンスアンプ71はNチャンネル
トランジスタ3a。5(A) and 5(B) show a circuit diagram and a plan view thereof when the conventional semiconductor device shown in FIG. 4 is applied to a sense amplifier of a D-RAM. In the figure, 7+, 72, and 73 are sense amplifiers; for example, the sense amplifier 71 is an N-channel transistor 3a.
8b及びPチャンネルトランジスタ8c、8dにて構成
されている。9+ 、92.93はセルアレイで、トラ
ンジスタ1o及びコンデンサ11にて構成されている。8b and P channel transistors 8c and 8d. 9+, 92.93 are cell arrays, which are composed of a transistor 1o and a capacitor 11.
ここで、通常状態にある場合の従来の回路例(第5図)
の動作を説明する。第3図に示す如く、ワードaWLか
らの制御信号によりセルアレイ91のトランジスタ10
が時刻t1でオンとなりコンデンサ11に蓄えられてい
た情報がビット線8Lに現われる。第3図は、コンデ°
ンサ11に高レベルの電荷が蓄えられていた例であり、
ビット線BLのレベルが上がっている。次に、制御線P
SA、NSAからの制御信号によってセンスアンプ7I
が時刻t2でセンス動作を開始し、ビット線BL及びビ
ット線8Lのレベルは増幅されて夫々Hレベル及びLレ
ベルの情報が出力される。Here, an example of a conventional circuit in a normal state (Fig. 5)
Explain the operation. As shown in FIG. 3, the transistor 10 of the cell array 91 is activated by the control signal from the word aWL.
is turned on at time t1, and the information stored in the capacitor 11 appears on the bit line 8L. Figure 3 shows the conde
This is an example where a high level of charge was stored in the sensor 11.
The level of the bit line BL is rising. Next, the control line P
The sense amplifier 7I is controlled by control signals from SA and NSA.
starts sensing operation at time t2, and the levels of bit line BL and bit line 8L are amplified to output H level and L level information, respectively.
次にα線が侵入して誤動作を生じる場合の第5図の動作
を説明する。α線が例えばドレイン電極の拡散M2に時
刻t1からt3の間に侵入すると前述のように電子が捕
獲され拡散層2の電位降下がおこる。そして、第6図に
示す如く、制御線PSA、NSAからのIli御信号を
供給する以前に時刻t3からビット線8L及びビット線
−■ゴーの出力レベルは正常時とは逆のレベルとなり、
本来のレベルとは逆のレベルの情報が出力される問題点
があった。これは、α線によって発生した電子の捕獲間
が少ない場合は特に問題ないが、その電子の母が多い場
合は、上記の如き誤動作を生じる。Next, the operation shown in FIG. 5 when α rays enter and cause malfunction will be explained. When α rays enter, for example, the diffusion M2 of the drain electrode between times t1 and t3, electrons are captured and the potential of the diffusion layer 2 is lowered as described above. Then, as shown in FIG. 6, before the Ili control signal is supplied from the control lines PSA and NSA, from time t3 the output levels of the bit line 8L and bit line -Go become the opposite level from the normal state.
There was a problem in that information was output at a level opposite to the original level. This is not a particular problem if the number of electrons generated by the alpha rays is captured is small, but if the number of electrons is large, the above-mentioned malfunction occurs.
本発明になる半導体装置は、第1図に示す如く、α線6
の粒子が半導体チップに侵入した際に発生する電荷によ
って誤動作に至る回路を構成する一のトランジスタの拡
散層部分を複数個(131。As shown in FIG. 1, the semiconductor device according to the present invention has α-ray 6
A plurality of diffusion layer portions (131) of one transistor that constitute a circuit cause malfunction due to charges generated when particles enter a semiconductor chip.
132)に分割して設けてなる。132).
一つのトランジスタを構成する拡散層部分を複数個に分
割したので拡散層131.132夫々1個宛の面積は従
来のものに比して小さく、α線6が空乏層162を通過
する距離22は従来のものに比して短かく、電荷捕1f
fiが従来のものに比して少ないため誤動作に至らない
。Since the diffusion layer part constituting one transistor is divided into a plurality of parts, the area for each of the diffusion layers 131 and 132 is smaller than that of the conventional one, and the distance 22 that the α ray 6 passes through the depletion layer 162 is It is shorter than the conventional one and has a charge trapping capacity of 1f.
Since fi is smaller than that of the conventional type, malfunction does not occur.
第1図(A)、(B)は夫々本発明の半導体装置の一実
施例の平面図及びそのB−B線に沿った断面図を示す。FIGS. 1(A) and 1(B) respectively show a plan view and a sectional view taken along the line B--B of an embodiment of the semiconductor device of the present invention.
同図中、12はゲート電極、131゜132は拡散層(
夫々がドレインlff1及びソース電極を構成する)で
、第4図に示す本来の1個の拡散層2を例えば2個に分
割したもので、本発明の要部をなす。14は酸化膜、1
5は基板、161゜162は空乏層である。In the figure, 12 is a gate electrode, 131° and 132 are diffusion layers (
Each of them constitutes a drain lff1 and a source electrode), which are obtained by dividing the original one diffusion layer 2 shown in FIG. 4 into two, for example, and form the main part of the present invention. 14 is an oxide film, 1
5 is a substrate, and 161° and 162 are depletion layers.
このように、1つのトランジスタを構成する拡rl1層
部分を′a敗に分割したので、拡散層131゜132夫
々1個宛の面積は第4図示の従来装置の拡r11ffi
2の面積に比して小さく、これにより、α線6が空乏層
162を通過する距離!!、2は従来装置の距離2+
に比して短かい。従って、電荷捕獲凹が従来装置に比し
て少なく、拡散層の電位降下が小さいため誤動作に至ら
ない。In this way, since the expanded rl1 layer portion constituting one transistor is divided into 'a' parts, the area for each of the diffusion layers 131 and 132 is the same as that of the conventional device shown in FIG.
This is the distance that α rays 6 pass through the depletion layer 162! ! , 2 is the distance of the conventional device 2+
It is shorter than . Therefore, there are fewer charge trapping recesses than in conventional devices, and the potential drop in the diffusion layer is small, so malfunctions do not occur.
第2図(A)、(B)は第1図に示す本発明になる半導
体装置をD−LRAMのセンスアンプに適用した場合の
回路図及びその平面図を示し、同図中、第5図と同一構
成部分には同一番号を付す。2(A) and 2(B) show a circuit diagram and a plan view thereof when the semiconductor device according to the present invention shown in FIG. 1 is applied to a D-LRAM sense amplifier; The same components are given the same numbers.
同図中、171’、172.173はセンスアンプで、
例えばセンスアンプ171はトランジスタ部18a(拡
散層131 )、18b<拡散層132)からなるNチ
ャンネルトランジスタ18、トランジスタ部19a(拡
散層131 )、19b(拡散ff113z)からなる
Nチャンネルトランジスタ19、トランジスタ部20a
、20bからなるPチャンネルトランジスタ20、トラ
ンジスタ部21a、21bからなるPチャンネルトラン
ジスタ21にて構成されている。In the same figure, 171', 172, and 173 are sense amplifiers,
For example, the sense amplifier 171 includes an N-channel transistor 18 consisting of transistor sections 18a (diffusion layer 131) and 18b<diffusion layer 132), an N-channel transistor 19 consisting of transistor sections 19a (diffusion layer 131) and 19b (diffusion ff113z), and a transistor section. 20a
, 20b, and a P-channel transistor 21 including transistor parts 21a and 21b.
ここで、従来装置と略同様に、第3図に示す如く、ワー
ド線WLからの制御信号によりセルアレイ91のトラン
ジスタが時刻t1゛でオンとなり、次に、制御線PSA
、NSAからの制御信号によってセンスアンプ17+が
時刻t2でセンス動作を開始し、ビット線BL及びビッ
ト線BLのレベルは増幅されて夫々Hレベル及びLレベ
ルの情報が出力される。ここで、前述のようにα線が侵
入しても拡散層の電位降下が従来装置に比して小さいの
で、従来装置のような本来のレベルとは逆のレベルの情
報が出力されるような誤動作を生じることはない。Here, as shown in FIG. 3, substantially similar to the conventional device, the transistors of the cell array 91 are turned on at time t1' by a control signal from the word line WL, and then
, the sense amplifier 17+ starts sensing operation at time t2 in response to a control signal from the NSA, and the levels of the bit lines BL and BL are amplified to output H level and L level information, respectively. Here, as mentioned above, even if alpha rays enter, the potential drop in the diffusion layer is smaller than in conventional devices, so information at a level opposite to the original level is output as in conventional devices. No malfunction will occur.
この場合、一般に、α線は数10時間毎に1個放射され
ると考えられるので、本実施例のように拡散層を例えば
2個(131 、132 )設けてもその1個宛の電荷
捕獲量が少なければ、α線の放射間隔に比して極めて短
時間に動作するD−RAMに適用した場合に上記の如き
7A動作を防止し得る。In this case, it is generally considered that one alpha ray is emitted every several tens of hours, so even if two diffusion layers (131, 132) are provided as in this example, the charge trapping for one of them is If the amount is small, the above-described 7A operation can be prevented when applied to a D-RAM that operates in a very short time compared to the emission interval of α rays.
なお、第1図(A>、(B)に示す実施例の如く、ソー
ス電極S及びドレイン電極りの両方を拡散層131.1
32として独立に設けてもよいが、特に、α線6の注入
によって発生する電荷によって回路の誤動作を引き起こ
す方の拡散層(トレイン電極)のみを拡散層131.1
32として独立に設け、他方の拡散層(ソース電極)を
独立せずに設けてもよい。Note that, as in the embodiment shown in FIGS. 1A and 1B, both the source electrode S and the drain electrode are covered with a diffusion layer
However, in particular, only the diffusion layer (train electrode) that causes malfunction of the circuit due to the charge generated by the injection of α rays 6 is provided as the diffusion layer 131.1.
32 may be provided independently, and the other diffusion layer (source electrode) may be provided not independently.
本発明によれば、一のトランジスタを構成する拡散層部
分を複数個に分割して設けたため、α線が空乏層を通過
する距離は従来のものに比して短かくなり、これにより
、α線が半導体チップに侵入した際の電荷捕1ffiは
従来のものに比して少なくなって拡散層の電位降下が小
さくなり、もって、例えばD−RAMのセンスアンプ等
に適用した場合、従来のような誤動作を生じることはな
く、動作信頼性を向上し得る等の特長を有する。According to the present invention, since the diffusion layer portion constituting one transistor is divided into a plurality of parts, the distance that α rays pass through the depletion layer is shorter than that of the conventional method, and thus α When a line enters a semiconductor chip, charge trapping 1ffi is smaller than in the conventional case, and the potential drop in the diffusion layer is small. It has the advantage of not causing serious malfunctions and improving operational reliability.
第1図は本発明装置の一実施例の平面図及び断面図、
第2図は本発明装置をD−RAMのセンスアンプに適用
した場合の回路図及び平面図、第3図はD−RAMの正
常状態時の動作特性図、第4図は従来装置の一例の平面
図及び断面図、第5図は従来装置をD−RAMのセンス
アンプに適用した場合の回路図及び平面図、
第6図はD−RAMの誤動作時の動作特性図である。
図中において、
6はα線、
9+ 、92.93はセルアレイ、
12はゲート電極、
131.132は拡散層、
14は酸化膜、
15は基板、
161.162は空乏層、
17+ 、172.173はセンスアンプ、18.19
,20.21はトランジスタ、18a、18b、19a
、19b、20a。
20b、21a、21bはトランジスタ部、Dはドレイ
ン電極、
Sはソース電也である。
第1図
(A)
第2図
第4図
第5図(A)FIG. 1 is a plan view and a sectional view of an embodiment of the device of the present invention, FIG. 2 is a circuit diagram and a plan view of the device of the present invention applied to a D-RAM sense amplifier, and FIG. 3 is a D-RAM sense amplifier. Fig. 4 is a plan view and a cross-sectional view of an example of a conventional device; Fig. 5 is a circuit diagram and plan view when the conventional device is applied to a D-RAM sense amplifier; The figure is an operational characteristic diagram when the D-RAM malfunctions. In the figure, 6 is the alpha ray, 9+, 92.93 is the cell array, 12 is the gate electrode, 131.132 is the diffusion layer, 14 is the oxide film, 15 is the substrate, 161.162 is the depletion layer, 17+, 172.173 is sense amplifier, 18.19
, 20.21 are transistors, 18a, 18b, 19a
, 19b, 20a. 20b, 21a, and 21b are transistor parts, D is a drain electrode, and S is a source electrode. Figure 1 (A) Figure 2 Figure 4 Figure 5 (A)
Claims (1)
電荷によって誤動作に至る様な半導体装置において、該
半導体装置を構成する一のトランジスタの拡散層部分を
複数個(13_1、13_2)に分割して設けてなるこ
とを特徴とする半導体装置。In a semiconductor device where the electric charge generated when α-ray (6) particles are injected into a semiconductor chip may cause malfunction, the diffusion layer portion of one transistor constituting the semiconductor device is divided into multiple pieces (13_1, 13_2). What is claimed is: 1. A semiconductor device comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61152934A JPH0760860B2 (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61152934A JPH0760860B2 (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS639143A true JPS639143A (en) | 1988-01-14 |
JPH0760860B2 JPH0760860B2 (en) | 1995-06-28 |
Family
ID=15551338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61152934A Expired - Lifetime JPH0760860B2 (en) | 1986-06-30 | 1986-06-30 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0760860B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007073709A (en) * | 2005-09-06 | 2007-03-22 | Nec Electronics Corp | Semiconductor device |
JP2008085235A (en) * | 2006-09-29 | 2008-04-10 | Toshiba Corp | Semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4841160U (en) * | 1971-09-15 | 1973-05-25 |
-
1986
- 1986-06-30 JP JP61152934A patent/JPH0760860B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4841160U (en) * | 1971-09-15 | 1973-05-25 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007073709A (en) * | 2005-09-06 | 2007-03-22 | Nec Electronics Corp | Semiconductor device |
JP2008085235A (en) * | 2006-09-29 | 2008-04-10 | Toshiba Corp | Semiconductor device |
Also Published As
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