JPH0758798B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0758798B2 JPH0758798B2 JP59118673A JP11867384A JPH0758798B2 JP H0758798 B2 JPH0758798 B2 JP H0758798B2 JP 59118673 A JP59118673 A JP 59118673A JP 11867384 A JP11867384 A JP 11867384A JP H0758798 B2 JPH0758798 B2 JP H0758798B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor device
- type
- semiconductor
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 60
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 11
- 229910017875 a-SiN Inorganic materials 0.000 claims description 3
- 229910020328 SiSn Inorganic materials 0.000 claims description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 description 5
- 229910021424 microcrystalline silicon Inorganic materials 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910021478 group 5 element Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PIN type
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/547—Monocrystalline silicon PV cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
- Y02E10/548—Amorphous silicon PV cells
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関する。さらに詳しくは、高効率
な光起電力を生ぜしめる半導体装置に関する。The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device that produces highly efficient photovoltaic power.
従来、高効率な光起電力を生ぜしめる半導体装置を製造
するために、窓側に光学的エネルギーギヤツプ（Eg.op
t）の大きな材料を用いたり、ａ−Siのホモ接合を有す
る半導体装置において、ｉ層にホウ素を入れて補償する
方法が知られている（米国特許第4217148号明細書）。Conventionally, in order to manufacture a semiconductor device that produces highly efficient photovoltaic power, an optical energy gear (Eg.op
There is known a method of compensating by using boron in the i layer in a semiconductor device having a large t) or having a homojunction of a-Si (US Pat. No. 4,217,148).
本発明者らは、ITO/n型ａ−Si:H/i型ａ−Si:H/p型ａ−S
iC:H/SUSなどからなるヘテロ接合を有する半導体装置の
ｉ層にホウ素を入れて、高効率な光起電力を生ずる半導
体装置を製造しようとしたが、単にｉ層にホウ素を入れ
て補償し、真性にするだけでは効果のないことが判明し
た。The present inventors have found that ITO / n type a-Si: H / i type a-Si: H / p type aS
I tried to manufacture a semiconductor device that produces a highly efficient photovoltaic by adding boron to the i layer of a semiconductor device having a heterojunction such as iC: H / SUS, but just add boron to the i layer to compensate. , It turned out that just making it genuine has no effect.
本発明は、上記のごときヘテロ接合を有する半導体装置
においては、高効率な光起電力を生ずる半導体装置をう
ることが、ｉ層にホウ素を入れて補償するだけではでき
ないという問題点を解決するとともに、ホモ接合を有す
る半導体装置においてもさらに高効率な光起電力を生ぜ
しめる半導体装置をうるためになされたものである。The present invention solves the problem that, in the semiconductor device having a heterojunction as described above, it is not possible to obtain a semiconductor device that produces highly efficient photovoltaic power by simply compensating by adding boron to the i layer. The present invention has been made in order to obtain a semiconductor device which can generate a highly efficient photovoltaic even in a semiconductor device having a homojunction.
本発明は、pin接合半導体装置において、光の入射側の
半導体層の禁止帯幅がｉ層の禁止帯幅よりも0.1〜0.5eV
大きく、かつｐ層−ｉ層（以下、p/iという）の価電子
帯のエネルギー差とｉ層−ｎ層間（以下、i/nという）
の伝導体のエネルギー差が実質的に等しいことを特徴と
する半導体装置に関し、このようにすることにより、前
記問題点を解決したものである。According to the present invention, in the pin junction semiconductor device, the band gap of the semiconductor layer on the light incident side is 0.1 to 0.5 eV more than the band gap of the i layer.
The energy difference of the valence band between the p layer and the i layer (hereinafter referred to as p / i) is large and the i layer to the n layer (hereinafter referred to as i / n).
With regard to a semiconductor device characterized in that the conductors have substantially the same energy difference, the above problem is solved by doing so.
本発明におけるpin接合半導体装置は、少なくともｐ層
またはｎ層がSiを含む非晶質または結晶相を含む非晶質
半導体で、ｉ層がSiを含む非晶質半導体層からなるpin
ホモ接合半導体装置またはpinヘテロ接合半導体装置で
ある。In the pin junction semiconductor device of the present invention, at least the p layer or the n layer is an amorphous semiconductor containing Si or an amorphous semiconductor containing a crystalline phase, and the i layer is an amorphous semiconductor layer containing Si.
A homojunction semiconductor device or a pin heterojunction semiconductor device.
なお、その光の入射側の半導体層はｐ層であつてもよ
く、ｎ層であつてもよい。また該半導体装置の半導体層
は、pin半導体層が１層のものでもよいが、多層、たと
えば２〜６層程度に積層されたものであつてもよい。The semiconductor layer on the light incident side may be a p-layer or an n-layer. The semiconductor layer of the semiconductor device may have a single pin semiconductor layer, but may have a multi-layered structure, for example, two to six layers.
本発明の半導体装置を形成するｐ層またはｎ層として
は、ａ−SiC系、ａ−SiN系、ａ−SiCN系、ａ−SiO系、
ａ−SiON系などからなる層、あるいはこれらの成分から
なる微結晶化した層やμｃ−Si系の層などがあげられ、
Ｈおよび（または）Ｆなどを含有していてもよい。The p layer or the n layer forming the semiconductor device of the present invention includes a-SiC type, a-SiN type, a-SiCN type, a-SiO type,
Examples of the layer include an a-SiON-based layer, a microcrystallized layer including these components, and a μc-Si-based layer.
It may contain H and / or F and the like.
本発明の半導体装置を形成するｉ層としては、Siを含む
ドープされていない非晶質半導体で、Ｈおよび（また
は）Ｆなどを含有するものであり、フエルミレベルを調
節するために必要により、Ｂ、Alなどの周期表第III族
の元素、あるいはＰ、Asなどの周期表第Ｖ族の元素を少
量（0.01〜100ppm程度）含んでいてもよい。このような
ｉ層の具体例としては、ａ−Si系、ａ−SiGe系、ａ−Si
N系またはａ−SiSn系などからなる層があげられる。The i layer forming the semiconductor device of the present invention is an undoped amorphous semiconductor containing Si and contains H and / or F, and if necessary in order to adjust the Fermi level, B , Al, etc., or a group V element in the periodic table such as P or As may be included in a small amount (about 0.01 to 100 ppm). Specific examples of such an i layer include a-Si type, a-SiGe type, and a-Si type.
Examples of the layer include N-based or a-SiSn-based layers.
本発明の半導体装置を形成するpinの各層の間には、つ
ぎの関係が存在することが必要である。すなわち、光入
射側のｐ層またｎ層のエネルギーギヤツプであるEg.pま
たはEg.nが、ｉ層のエネルギーギヤツプであるEg.iより
0.1〜0.5eV大きく、かつp/i間の価電子帯のエネルギー
差（ΔEp/i）がi/n間の伝導体のエネルギー差（ΔEi/
n）と実質的に等しい（差が0.1eV以下である）ことが必
要である。なおｐ層、ｉ層、ｎ層、Eg.p、Ｅｇ・ｉ、Ｅ
ｇ・ｎ、ΔＥ、ΔＥp/i、ΔＥi/nの関係を第１図に示
す。各層におけるΔＥは電気伝導度の温度依存性から測
定される活性化エネルギーで、伝導帯（Ec）または価電
子帯（Ev）とフェルミレベル（Ef）とのエネルギー差の
うち、小さい方を示す。第１図中のEfはフエルミレベ
ル、Ecは伝導帯エネルギーレベル、Evは価電子帯エネル
ギーレベルのことである。The following relationships must exist between the layers of the pins forming the semiconductor device of the present invention. That is, Eg.p or Eg.n, which is the energy gap of the p-layer or the n-layer on the light incident side, is larger than that of Eg.i, which is the energy gap of the i-layer.
0.1 to 0.5 eV larger, and the energy difference of the valence band between p / i (ΔEp / i) is the energy difference of the conductor between i / n (ΔEi /
n) should be substantially equal (the difference should be less than 0.1eV). Note that p layer, i layer, n layer, Eg.p, Eg · i , E
The relationship between gn , ΔE, ΔE p / i , and ΔE i / n is shown in FIG. ΔE in each layer is the activation energy measured from the temperature dependence of electrical conductivity and is the smaller of the energy difference between the conduction band (E c ) or valence band (E v ) and the Fermi level (E f ). Indicates. In Fig. 1, E f is the Fermi level, Ec is the conduction band energy level, and Ev is the valence band energy level.
前記光入射側のEg.pまたEg.nがEg.iよりも0.1〜0.5eV大
きいばあいには、短絡電流と開放電圧（Voc）が大きく
なり、曲線因子（FF）も改善される結果高効率がえられ
る。なお、前記の差が0.5eVをこえるとエネルギースパ
イクが発生しやすくなるので、0.5eV以下であることが
好ましいが、0.1eV以上大きくないばあいには、短絡電
流や開放電圧が改善されないので効果が小さくなる。When Eg.p or Eg.n on the light incident side is larger than Eg.i by 0.1 to 0.5 eV, the short-circuit current and open circuit voltage (Voc) are large, and the fill factor (FF) is also improved. High efficiency can be obtained. Since energy spikes tend to occur when the difference exceeds 0.5 eV, it is preferably 0.5 eV or less, but unless 0.1 eV or more is large, the short-circuit current and open-circuit voltage are not improved, so it is effective. Becomes smaller.
またΔEp/iがΔEi/nより大きいか、または小さく、実質
的に等しくないばあいには、電流値が少なくなる。When ΔEp / i is larger or smaller than ΔEi / n and is not substantially equal, the current value is small.
本発明の半導体装置は、形成されたｐ層、ｉ層、ｎ層の
EgおよびΔEp/i、ΔEi/nが、前記条件を満足するように
製造されるかぎり、通常の方法により製造することがで
き、ｐ、ｉ、ｎ各層の厚さなどに限定はない。The semiconductor device of the present invention includes the formed p layer, i layer, and n layer.
As long as Eg and ΔEp / i and ΔEi / n are manufactured so as to satisfy the above-mentioned conditions, they can be manufactured by a usual method, and the thicknesses of p, i, and n layers are not limited.
つぎに本発明の半導体装置を実施例にもとづき説明す
る。Next, the semiconductor device of the present invention will be described based on examples.
実施例１ 厚さ2000ÅのSnO2透明電極を設けた厚さ1.1mmのガラス
基板上に、ｐ層は基板温度150℃でSiH4＋CH4＋B2H6（0.
01モル％）からなる混合ガス、ｉ層は基板温度200℃でS
iH4＋PH3（0.000001モル％）からなる混合ガスをこの順
に用いて、３室分離グロー放電法により、ａ−SiC:Hか
らなるｐ層を130Å、ａ−Si:Hからなるｉ層を7000Å堆
積させた。ついでｎ層を基板温度200℃で、SiH4＋PH3＋
H2からなる混合ガスを用いRFパワーを10倍にしたほかは
ｉ層と同様にしてμｃ−Siからなるｎ層を堆積させ、半
導体装置を作製した。Example 1 A p-layer was formed on a glass substrate having a thickness of 2000 mm and provided with a SnO 2 transparent electrode having a thickness of 1.1 mm and having a p-layer of SiH 4 + CH 4 + B 2 H 6 (0.
01 mol%) mixed gas, i layer is S at substrate temperature 200 ℃
Using a mixed gas consisting of iH 4 + PH 3 (0.000001 mol%) in this order, a p-layer of a-SiC: H was 130 Å and an i-layer of a-Si: H was 7,000 Å by a three-chamber separation glow discharge method. Deposited. Next, the n-layer is heated to a substrate temperature of 200 ° C. and SiH 4 + PH 3 +
A semiconductor device was manufactured by depositing an n-layer made of μc-Si in the same manner as the i-layer except that the RF power was increased 10 times by using a mixed gas made of H 2 .
えられた半導体装置は、ｐ型ａ−SiC:H（Eg.p＝2.05e
V、ΔＥ＝0.5eV）/i型ａ−Si:H（Eg.i＝1.8eV、ΔＥ＝
0.68eV）/n型μｃ−Si（ΔＥ＝0.05eV）のものでΔEp/i
＝0.62eV、ΔEi/n＝0.63eVと実質的に等しいものであつ
た。The obtained semiconductor device is a p-type a-SiC: H (Eg.p = 2.05e
V, ΔE = 0.5 eV) / i-type a-Si: H (Eg.i = 1.8 eV, ΔE =
0.68eV) / n type μc-Si (ΔE = 0.05eV) and ΔEp / i
= 0.62 eV and ΔEi / n = 0.63 eV, which are substantially the same.
えられた半導体装置にAl電極を2000Å形成して太陽電池
を作製し、AM−１、100mW/cm2のソーラシユミレーター
での太陽電池特性を測定したところ、Jsc＝18mA/cm2、V
oc＝0.93V、FF＝75％、η＝12.6％であつた。A solar cell was prepared by forming an Al electrode on the obtained semiconductor device at 2000 Å, and the solar cell characteristics were measured with a solar simulator of AM-1, 100 mW / cm 2 , Jsc = 18 mA / cm 2 , V
It was oc = 0.93V, FF = 75%, and η = 12.6%.
比較例１ 実施例１において、ｉ層の形成時に用いたPH3を使用し
なかった他は実施例１と同様にして、半導体装置を作製
した。Comparative Example 1 A semiconductor device was manufactured in the same manner as in Example 1 except that PH 3 used in forming the i layer was not used.
えられた半導体装置は、ｐ型ａ−SiC:H（Eg・ｐ＝2.05e
V、ΔＥ＝0.5eV）/i型ａ−Si:H（Eg・ｉ＝1.81eV、ΔＥ
＝0.85eV）/n型μｃ−Si（ΔＥ＝0.05eV）のもので、Δ
Ｅp/i＝0.46eV、ΔＥi/n＝0.80eVと実質的に異なるもの
であった。The obtained semiconductor device is a p-type a-SiC: H (Eg · p = 2.05e
V, ΔE = 0.5eV) / i-type a-Si: H (Eg · i = 1.81eV, ΔE
= 0.85 eV) / n type μc-Si (ΔE = 0.05 eV)
E p / i = 0.46 eV and ΔE i / n = 0.80 eV, which were substantially different.
えられた半導体装置に、実施例１と同様にしてAl電極を
形成して太陽電池を作製し、太陽電池特性を測定したと
ころ、Jsc＝16mA/cm2、Voc＝0.92V、FF＝71％、η＝10.
5％であった。An Al electrode was formed on the obtained semiconductor device in the same manner as in Example 1 to manufacture a solar cell, and the solar cell characteristics were measured. Jsc = 16mA / cm 2 , Voc = 0.92V, FF = 71% , Η = 10.
It was 5%.
比較例２ 実施例１において、ｐ層の形成に用いたSiH4＋CH4＋B2H
6（0.01モル％）からなる混合ガスにおけるCH4のガス量
を67％増にした他は実施例１と同様にして、半導体装置
を作製した。Comparative Example 2 SiH 4 + CH 4 + B 2 H used for forming the p-layer in Example 1
A semiconductor device was manufactured in the same manner as in Example 1 except that the amount of CH 4 gas in the mixed gas of 6 (0.01 mol%) was increased by 67%.
えられた半導体装置は、ｐ型ａ−SiC:H（Eg・ｐ＝2.14e
V、ΔＥ＝0.6eV）/i型ａ−Si:H（Eg・ｉ＝1.8eV、ΔＥ
＝0.68eV）/n型μｃ−Si（ΔＥ＝0.05eV）のもので、Δ
Ｅp/i＝0.52eV、ΔＥi/n＝0.63eVと実質的に異なるもの
であった。The obtained semiconductor device is a p-type a-SiC: H (Egp = 2.14e
V, ΔE = 0.6eV) / i-type a-Si: H (Eg · i = 1.8eV, ΔE
= 0.68 eV) / n type μc-Si (ΔE = 0.05 eV)
E p / i = 0.52 eV and ΔE i / n = 0.63 eV, which are substantially different.
えられた半導体装置に、実施例１と同様にしてAl電極を
形成して太陽電池を作製し、太陽電池特性を測定したと
ころ、Jsc＝15mA/cm2、Voc＝0.93V、FF＝61％、η＝8.5
％であった。An Al electrode was formed on the obtained semiconductor device in the same manner as in Example 1 to prepare a solar cell, and the solar cell characteristics were measured. Jsc = 15mA / cm 2 , Voc = 0.93V, FF = 61% , Η = 8.5
%Met.
実施例２ SUS基板上に、基板温度250℃でｐ型ａ−SiC:H（Eg.p＝
1.80V、ΔＥ＝0.5eV）500Å、B2H6を2ppmドープしたｉ
型ａ−Si:H（Eg.i＝1.8eV、ΔＥ＝0.8eV）5000Å、ｎ型
ａ−SiC:H（Eg.n＝1.95eV ΔＥ＝0.3eV）150Åを堆積
させ、ITOを850Åの厚さになるように蒸着させた。この
ばあいのΔEp/i＝ΔEi/n＝0.5eVであつた。Example 2 A p-type a-SiC: H (Eg.p =
1.80V, ΔE = 0.5eV) 500Å, i doped with B 2 H 6 at 2ppm
Type a-Si: H (Eg.i = 1.8eV, ΔE = 0.8eV) 5000Å, n-type a-SiC: H (Eg.n = 1.95eV ΔE = 0.3eV) 150Å are deposited, and ITO is 850Å thick It was vapor-deposited so that it became the size. In this case, ΔEp / i = ΔEi / n = 0.5 eV.
えられた太陽電池の特性をAM−１、100mW/cm2のソーラ
シユシレーターで測定したところ、Jsc＝16.3mA/cm2、V
oc＝0.85V、FF＝68％、η＝9.4％であつた。The characteristics of the obtained solar cell were measured with a solar simulator of AM-1, 100mW / cm 2 , Jsc = 16.3mA / cm 2 , V
It was oc = 0.85V, FF = 68%, and η = 9.4%.
上記のように、pin整合半導体装置において、光の入射
側の半導体層のEgがｉ層のEgよりも0.1〜0.5eV大きく、
かつΔEp/iとΔEi/nとを実質的に等しくすることによ
り、ヘテロ接合あるいはホモ接合の区別なく、高効率な
光起電力を生ぜしめる半導体装置をうることができる。As described above, in the pin matching semiconductor device, the Eg of the semiconductor layer on the light incident side is larger by 0.1 to 0.5 eV than the Eg of the i layer,
In addition, by making ΔEp / i and ΔEi / n substantially equal, it is possible to obtain a semiconductor device that can generate highly efficient photovoltaic power without distinguishing between heterojunction and homojunction.
第１図は、光の入射する側がｐ層である半導体装置のｐ
層、ｉ層、ｎ層とEg.p、Eg.i、Eg.nとの関係およびΔEp
/i、ΔEi/nに関する説明図である。FIG. 1 shows a p-type semiconductor device in which the light-incident side is a p-layer.
Relationship between Eg.p, Eg.i, and Eg.n and p, i, and n layers and ΔEp
It is explanatory drawing regarding / i and (DELTA) Ei / n.
Claims (5)
の半導体層の禁止帯幅がｉ層の禁止帯幅よりも0.1〜0.5
eV大きく、かつｐ層−ｉ層間の価電子帯のエネルギー差
とｉ層−ｎ層間の伝導帯のエネルギー差が実質的に等し
いことを特徴とする半導体装置。1. In a pin-junction semiconductor device, the band gap of the semiconductor layer on the light incident side is 0.1 to 0.5 than the band gap of the i layer.
A semiconductor device having a large eV and an energy difference in a valence band between the p layer and the i layer and an energy difference in a conduction band between the i layer and the n layer are substantially equal to each other.
層またはｎ層がSiを含む非晶質また結晶相を含む非晶質
半導体で、ｉ層がSiを含む非晶質半導体からなるpinホ
モまたはpinへテロ接合半導体装置である特許請求の範
囲第１項記載の半導体装置。2. The pin junction semiconductor device is at least p.
A pin homo or pin heterojunction semiconductor device in which the layer or the n layer is an amorphous semiconductor containing Si or an amorphous semiconductor containing a crystalline phase, and the i layer is an amorphous semiconductor containing Si. The semiconductor device according to item 1.
層である特許請求の範囲第１項記載の半導体装置。3. The semiconductor layer on the light incident side is a p-layer or an n-layer.
The semiconductor device according to claim 1, which is a layer.
系、ａ−SiCN系、ａ−SiO系、ａ−SiON系またはμｃ−S
i系からなる層であり、ｉ層がａ−Si系、ａ−SiGe系、
ａ−SiN系またはａ−SiSn系からなる層である特許請求
の範囲第１項、第２項または第３項記載の半導体装置。4. The p-layer or the n-layer is an a-SiC type, a-SiN
System, a-SiCN system, a-SiO system, a-SiON system or μc-S
i-type layer, i-layer is a-Si type, a-SiGe type,
The semiconductor device according to claim 1, which is a layer made of an a-SiN system or an a-SiSn system.
〜６層積層した半導体層を有する半導体装置である特許
請求の範囲第１項、第２項、第３項または第４項記載の
半導体装置。5. The pin-junction semiconductor device has a pin semiconductor layer of 2 layers.
The semiconductor device according to claim 1, 2, 3, or 4, which is a semiconductor device having six to six stacked semiconductor layers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59118673A JPH0758798B2 (en) | 1984-06-08 | 1984-06-08 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59118673A JPH0758798B2 (en) | 1984-06-08 | 1984-06-08 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60262470A JPS60262470A (en) | 1985-12-25 |
| JPH0758798B2 true JPH0758798B2 (en) | 1995-06-21 |
Family
ID=14742376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59118673A Expired - Lifetime JPH0758798B2 (en) | 1984-06-08 | 1984-06-08 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0758798B2 (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5513938A (en) * | 1978-07-17 | 1980-01-31 | Shunpei Yamazaki | Photoelectronic conversion semiconductor device and its manufacturing method |
| JPS5760875A (en) * | 1980-09-25 | 1982-04-13 | Sharp Corp | Photoelectric conversion element |
| JPS57181176A (en) * | 1981-04-30 | 1982-11-08 | Kanegafuchi Chem Ind Co Ltd | High voltage amorphous semiconductor/amorphous silicon hetero junction photosensor |
| JPS5823489A (en) * | 1981-08-05 | 1983-02-12 | Semiconductor Energy Lab Co Ltd | Manufacture of semiconductor device |
| JPS58171870A (en) * | 1982-04-02 | 1983-10-08 | Sanyo Electric Co Ltd | Photovoltaic device |
-
1984
- 1984-06-08 JP JP59118673A patent/JPH0758798B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60262470A (en) | 1985-12-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4496788A (en) | Photovoltaic device | |
| US6121541A (en) | Monolithic multi-junction solar cells with amorphous silicon and CIS and their alloys | |
| Fischer et al. | The" micromorph" solar cell: Extending a-Si: H technology towards thin film crystalline silicon | |
| US6077722A (en) | Producing thin film photovoltaic modules with high integrity interconnects and dual layer contacts | |
| US7879644B2 (en) | Hybrid window layer for photovoltaic cells | |
| US5066340A (en) | Photovoltaic device | |
| KR910001742B1 (en) | Photo electromotive force device | |
| EP0494088B1 (en) | Photovoltaic device | |
| JPH05243596A (en) | Manufacture of laminated type solar cell | |
| KR20080054807A (en) | Solar cell | |
| US8704326B2 (en) | Thin-film photoelectric conversion device and method for production thereof | |
| Beneking et al. | Recent developments in amorphous silicon‐based solar cells | |
| JPH0644638B2 (en) | Stacked photovoltaic device with different unit cells | |
| Meier et al. | Efficiency enhancement of amorphous silicon pin solar cells by LP-CVD ZnO | |
| US4857115A (en) | Photovoltaic device | |
| JPH0125235B2 (en) | ||
| JPS609178A (en) | Photovoltaic device | |
| Krühler | Amorphous thin-film solar cells | |
| JPH0122991B2 (en) | ||
| JP2946214B2 (en) | Thin film solar cell | |
| JPH0758798B2 (en) | Semiconductor device | |
| JPS6225275B2 (en) | ||
| Arya et al. | Progress in amorphous silicon based multijunction modules | |
| Dhere | Present status of the development of thin-film solar cells | |
| JPS62165374A (en) | Amorphous photovoltaic element |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |