JPS5823489A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5823489A
JPS5823489A JP56122707A JP12270781A JPS5823489A JP S5823489 A JPS5823489 A JP S5823489A JP 56122707 A JP56122707 A JP 56122707A JP 12270781 A JP12270781 A JP 12270781A JP S5823489 A JPS5823489 A JP S5823489A
Authority
JP
Japan
Prior art keywords
film
semiconductor
electrode
resist
nickel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56122707A
Other languages
Japanese (ja)
Inventor
Shunpei Yamazaki
舜平 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP56122707A priority Critical patent/JPS5823489A/en
Publication of JPS5823489A publication Critical patent/JPS5823489A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0224Electrodes
    • H01L31/022408Electrodes for devices characterised by at least one potential jump barrier or surface barrier

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemically Coating (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Photovoltaic Devices (AREA)

Abstract

PURPOSE:To obtain a cheap electrode having high reliability by forming a film, the principal ingredient thereof is nickel, through an electroless plating method and using the film as the electrode. CONSTITUTION:The figure shows a NCS1 with a transparent conductive film 3 and P20, I19 and N18 structure on a light transmitting substrate 7. A resist film 31 is formed selectively onto a base body through a screen printing method. The resist film is dried (at 100-200 deg.C generally), and the surface is activated and washed by water. These all surfaces containing the surface 35 of a semiconductor and the surface 36 of the transparent conductive film are activated. The surface is immersed in an electroless nickel plating liquid (Schumer) at 60-90 deg.C, and the metallic film 32, the principal ingredient thereof is nickel, is shaped onto these surfaces through the electroless plating method. The surfaces are lightly washed by water and hot water, the Schumer liquid is removed and the surfaces are heated and dried for thirty min at 100-200 deg.C. The whole is immersed in a resist removing agent, the resist film 31 is removed, and a metallic film 34 or another metallic film 33 on a semiconductor film are formed. The whole is sintered at the temperature of 100-350 deg.C.

Description

【発明の詳細な説明】 本発明は水素、フッ素、塩素の如きハロゲン元素または
りチューム、ナトリューム、カリュームの如きアルカリ
金属元素が再結合中心中和用に添加台布した非単結晶半
導体(アモルファ膜または薄膜状に形成された半導体の
総称、本明細書においてはNO8と略記する)またはこ
の半導体の電極として設けられた透明導電膜に密接して
ニッケルを主成分とする電極を設けることを目的とする
Detailed Description of the Invention The present invention provides a non-single crystal semiconductor (amorphous film or A general term for semiconductors formed in the form of a thin film, abbreviated as NO8 in this specification), or the purpose of providing an electrode containing nickel as a main component in close contact with a transparent conductive film provided as an electrode of this semiconductor. .

本発明はNC8を構成するPまたはN型の導電型を有す
る半導体に密接してオーム接触を有せしめたニッケル電
極またはその電極よシ延在したリードを設けることを目
的とする。
The object of the present invention is to provide a nickel electrode or a lead extending from the electrode in close ohmic contact with the semiconductor having conductivity type of P or N type constituting the NC8.

無電界メッキ法によシニッケルを主成分とする被膜を形
成しこれを電極とすることによシ、従来真空蒸着法等で
アルミニュームを主成分とした電極が形成さ糺ていたの
にかわシ安価でか(酸化インジューム、酸化スズ、酸化
ア!チ)ンまたはそれらの混合体代表的には工To、窒
化チタンの如き窒化物金属よシなる透光性の導電性被膜
を本発明では総称し、単にTCPという)上に印刷用レ
ジストを印刷コートしまたはフォトレジストをフォトエ
ツチングして選択的に形成し、このレジ及トの膜の形成
されていない領域にのみ選択的に金属膜特にニッケ゛ル
膜を形成し電極とすることを目的とする0 本発明はかかる選択的形成に関し、リフトオフ法を適用
した0すなわち金属膜を選択エツチング液グと、その液
がNC8またはTCP’を融食溶去してしまう。このこ
とを防ぐためかかるエツチング液を用いないことを他の
特徴としている。さらに本発明はスクリーン印刷を行な
う大面積の基板上に対し無電界メッキ法を適用するとリ
フトオフ可能であシ、工学的に安価で大量に電極、リー
ド形成が可能であることを示したことを他の特徴として
いる。
By forming a film mainly composed of aluminum using an electroless plating method and using this as an electrode, it is cheaper and cheaper than the conventional electrodes mainly composed of aluminum, which were formed using vacuum evaporation methods. In the present invention, a light-transmitting conductive film made of a metal oxide (indium oxide, tin oxide, atin oxide) or a mixture thereof, typically a nitride metal such as titanium nitride, is collectively referred to in the present invention. Then, a printing resist (simply referred to as TCP) is coated with a printing resist or a photoresist is selectively formed by photoetching, and a metal film, especially a nickel film, is selectively formed only on the regions where no film is formed on this resist or resist. The present invention relates to such selective formation, in which a lift-off method is applied to selectively etching a metal film, and the liquid erodes and erodes NC8 or TCP'. Resulting in. In order to prevent this, another feature is that such an etching solution is not used. Furthermore, the present invention shows that lift-off is possible when electroless plating is applied to a large-area substrate for screen printing, and that it is possible to form electrodes and leads in large quantities at low engineering cost. It is a feature of

従来NC8とTOFとが同一基板に設けられた代表的な
半導体装置として光電変換装置特にlアモルファス太陽
電池が知られている。さらにこのN0EJを応用した絶
縁ゲイト型電界効果半導体装置(例えば不発門人の出願
になる 半導体装置およびその作製方法 53−124
021昭和53年10月7日出願)が知られている。
Conventionally, a photoelectric conversion device, particularly an amorphous solar cell, is known as a typical semiconductor device in which an NC8 and a TOF are provided on the same substrate. Furthermore, an insulated gate field effect semiconductor device applying this N0EJ (for example, a semiconductor device and its manufacturing method, which is filed by an undiscovered disciple, 53-124)
021 (filed on October 7, 1978) is known.

しかしながらこれらの半導体装置においては上側の電極
特にプラズマOVD法、減圧CVD法によ多形成された
NO8上の電極形成にはアルミニュームの真空蒸着法に
よる被膜作製が行なわれていたρしかし真空蒸着法は蒸
着装置が2000万円〜40oO万円ときわめて高価で
あシまた原料の被膜化として用いられる材料の使用効率
も1%以下であシ、他の99%以上はむだになってしま
った。さらにアルミニュームの蒸発を大量生産において
は電子ビームで行なうため電子ビームにより被形成面の
半導体面損傷がおきてしまった。
However, in these semiconductor devices, an aluminum film was formed by vacuum evaporation to form an electrode on the upper electrode, especially on the NO8 formed by plasma OVD or low-pressure CVD. However, the vapor deposition equipment was extremely expensive, costing between 20 million yen and 40 million yen, and the efficiency of use of the materials used to form a film on the raw materials was less than 1%, and the other 99% or more was wasted. Furthermore, since aluminum is evaporated using an electron beam in mass production, the semiconductor surface on which it is formed is damaged by the electron beam.

そのため低価格の大容量太陽電池を作ろうとにもなって
しまった0このことは1o OFl/Wすなわち100
m’にて10チの効率を有する太陽電池をたものであシ
、被膜製造装置は数万円〜数十万円と安価でアシ、かつ
重要なことはこの被膜の作製に対し半導体に何らの機械
ストレス、電子ビーム衝撃によるスパッタ効果、ダメー
ジ効果がない。さらに熱処理温度が再結合中心中和元素
が外部に放出されはじめる3 50’C!以下の温度(
5) 代表的には100〜250@Oでよい等きわめて多くの
特徴を有している。
For this reason, I started trying to make low-cost, large-capacity solar cells. This means that 1o OFl/W, or 100
It is possible to obtain a solar cell with an efficiency of 10 cm at m', and the coating manufacturing equipment is inexpensive at tens of thousands to hundreds of thousands of yen, and importantly, there is no need for semiconductors to produce this coating. No mechanical stress, no sputtering effects, and no damage effects caused by electron beam impact. Furthermore, the heat treatment temperature is 350'C, at which point the recombination center neutralizing element begins to be released to the outside! The temperature below (
5) It has many characteristics such as typically 100 to 250@O.

加えて従来はTCFの化学エッチがいわゆるITOにお
陽ては酸ならば何でも簡単にエツチングされてしまう。
In addition, in conventional chemical etching of TCF, any acid can be easily etched onto so-called ITO.

こρため上の金属面のみを選択的に酸により化学エッチ
できず、電極形成には単に蒸着マスクを用いる以外に可
能でなかった。しかしこの蒸着マスクではマスークと基
板とのすきが発生しやすかった。そしてひいてはパター
ンにボケができやすく、工学的に最適の方法とはいえな
かった。
Therefore, it was not possible to selectively chemically etch only the upper metal surface with acid, and the only way to form electrodes was to simply use a vapor deposition mask. However, with this vapor deposition mask, gaps between the mask and the substrate were likely to occur. Furthermore, the pattern was likely to become blurry, so it was not an optimal method from an engineering perspective.

本発明は金属のエツチングに酸で金属そのものをエツチ
ングするのではなく、その下側にあらかじめ形成された
レジストを有機溶剤例えばトリクレン等によシ溶去する
ことによシ、その上側の金属をリフトオフするいわゆる
リフトオ界メッキ法で形成するという全く画期的なもの
である。
In the present invention, instead of etching the metal itself with acid, the metal on the upper side is lifted off by dissolving the resist previously formed on the lower side with an organic solvent such as trichlene. This is a completely innovative method in which it is formed using the so-called lift-off field plating method.

以下本発明を図面に従って説明する。The present invention will be explained below with reference to the drawings.

第を図のフローチャートは本発明方法を示す無電界メツ
3.・リフトオフ法の主たる工程を示している。
The flowchart in Figure 3 shows the method of the present invention. - Shows the main steps of the lift-off method.

第1図は本発明の半導体装置である光電変換装置および
その作製方法を示すたて断面図である0 第1図(A)において透光性基板(7)上の透明導電膜
(3)、pl、Iα転Nα枠型構造を有するNC8巾(
1,7〜2.3eV)を有するセミアモルファス半導体
層によIpP型およびN型半導体層(イ)、α樽をそれ
ぞれ50〜20OA、 ’150−30OAの膜厚にプ
ラズマ気相法によ多形成した。さらに真性または実質的
に真性の導電型を有する半導体α呻はアモルファスまた
はセミアモルファス構造を有する半導体により0.4〜
0.8μの膜厚にプラズマ気相法によ多形成されている
。この半導体膜の形成方法に関しては、不発門人の出願
による特許願(半導体装置作製方法 53−45288
’i’ 853.1210  出願)また特許願(半導
体装置 53−(7) 083467853、フ、8出願 対応米国特許 He
terOJunction  Sem1conduct
or  Device  伯I(4、254,4291
911,3,3公告)に記されている。
FIG. 1 is a vertical cross-sectional view showing a photoelectric conversion device, which is a semiconductor device of the present invention, and a method for manufacturing the same. In FIG. 1(A), a transparent conductive film (3) on a light-transmitting substrate (7), pl, NC8 width with Iα inversion Nα frame structure (
The IpP type and N type semiconductor layers (a) and α barrels were formed using a plasma vapor phase method to film thicknesses of 50 to 20 OA and 150 to 30 OA, respectively. Formed. Furthermore, the semiconductor α of having an intrinsic or substantially intrinsic conductivity type is 0.4 to
The film is formed to a thickness of 0.8μ by plasma vapor phase method. Regarding the method for forming this semiconductor film, there is a patent application filed by an unexplored student (Semiconductor device manufacturing method 53-45288).
'i' 853.1210 application) and patent application (Semiconductor device 53-(7) 083467853, F, 8 application Corresponding US patent He
terO Junction Sem1conduct
or Device Haku I (4, 254, 4291
911, 3, 3 public notice).

この第1図(A)の工程は光電変換装置であるがNO8
またはNO8とTOFとを少くとも一部に有している基
体(基板とNC8またはTCFとを有する総称)が第2
図(1)の工程に示されている。これは光電変換半導体
装置、絶縁ゲイト型電界効果トランジスタまたは集積化
構造体さらにフォトセンサ、フォトセンサアレー、イメ
ージセンサ等であってもよい。本発明はこれらいずれの
半導体装置に対しても有効である。
This process in Figure 1 (A) is for a photoelectric conversion device, but NO8
Or, the base body (general term including the substrate and NC8 or TCF) having at least a part of NO8 and TOF is the second
The process is shown in Figure (1). This may be a photoelectric conversion semiconductor device, an insulated gate field effect transistor, an integrated structure, a photosensor, a photosensor array, an image sensor, or the like. The present invention is effective for any of these semiconductor devices.

さらに第1図CB)においてこれら基体上に選択的にレ
ジスト膜(31)をスクリーン印刷法にて形成した。こ
れはスクリーンマスクを通して選択的にレジスト膜を5
〜30μの厚さに印刷形成させた。
Furthermore, in FIG. 1CB), a resist film (31) was selectively formed on these substrates by screen printing. This selectively spreads the resist film through a screen mask.
It was printed to a thickness of ~30μ.

もちろん公知のフォトエツチング法すなわち全面にレジ
ストを塗付し紫外光、電子ビームによりフォトマスクを
通じてレジストを硬化せしめ硬化しない部分を除去して
第1図(B)を得てもよい0 (8) この工程は第2図(2)に示している。さらにこのレジ
スト膜をれii、(一般には100〜zooc)シ(3
6)を含みこれらすべての表面を活性化した。
Of course, it is also possible to obtain the image shown in FIG. 1(B) by using the known photoetching method, that is, by coating the entire surface with a resist, curing the resist using ultraviolet light or an electron beam through a photomask, and removing the unhardened portions. The process is shown in Figure 2 (2). Furthermore, this resist film is heated (generally 100~zooc) (3
6) and activated all these surfaces.

すなわちセージタイザー(例えばSnO’1□1g/l
i.e. sagetizer (e.g. SnO'1□1g/l
.

HCl3m1/1残り水)中に室温にて5〜20分浸し
た。さらに市販のレッドシューマー液に室温にて5〜2
0分浸し、これら基体の表面を活性化した。第2図(5
)、さらにこの表面に無電解ニッケル絞金液(シューマ
ー)に液温60〜90°0例えば70DCにて5秒〜5
分間浸し、これらの表面はニッケルを主成分とする金属
膜を形成せしめ、このニッケル中には1価、■価または
遷移金属、珪素またはゲルマニュームを0.1〜5チ添
加してP型またはN型半導体へのオーム接触を助長して
もよい。かくして表面に500〜5000Aの膜厚の金
属膜(32)を無電解メッキ法にて形成せしめた。
3 ml of HCl (remaining water) for 5 to 20 minutes at room temperature. Furthermore, 5 to 2
The surfaces of these substrates were activated by immersion for 0 minutes. Figure 2 (5
), and further coat this surface with an electroless nickel drawing liquid (Schumer) at a temperature of 60 to 90 degrees, for example 70 DC, for 5 seconds to 5 minutes.
After soaking for a minute, a metal film containing nickel as a main component is formed on the surface of the nickel. It may also facilitate ohmic contact to the type semiconductor. In this way, a metal film (32) having a thickness of 500 to 5000 A was formed on the surface by electroless plating.

この後水洗、湯洗をかるく行ない、シューマー液を除去
した後、100〜200°C例えば120°Cに(9) て30分加熱乾燥をしてメッキ膜の半導体表面。
Thereafter, the Schumer's solution was removed by gentle washing with water and hot water, and the semiconductor surface of the plated film was dried by heating at 100 to 200°C, for example 120°C (9), for 30 minutes.

透明導電膜表面とのt%性を向上させた。この温度はレ
ジスト膜(31)が硬化しない程度に低いことが重要で
ある。
The t% property with the surface of the transparent conductive film was improved. It is important that this temperature is low enough that the resist film (31) does not harden.

この後これら全体をレジスト除去剤例えばトリクレン液
中に浸し、かるく起4凌を加えてレジスト膜(31)を
オニした。その結果レジスト膜上の金属膜はハクリし、
結果として第1図(C)の断面図に示される如く、TC
F上に金属膜(34)また半導体膜上に他の金属膜(3
3)を形成させることができた。第2図では工程(8)
に対応する。
Thereafter, the entire structure was immersed in a resist remover, such as a trichloride solution, and a diluted salt was added thereto to oxidize the resist film (31). As a result, the metal film on the resist film peels off,
As a result, as shown in the cross-sectional view of FIG. 1(C), the TC
A metal film (34) is placed on F and another metal film (34) is placed on the semiconductor film.
3) could be formed. In Figure 2, process (8)
corresponds to

さらにこれら全体を100−350’O代表的には15
0〜200’Oの温度にて15〜30分間シンターを行
ない必要に応じて230〜什0#05〜10秒間ハング
槽に浸しニッケル膜上にハンダ付を行なってもよい0 第1図において半導体層はPまたはN型の導電型を有し
、その電気伝導度が10シ4以上代表さらにオーム接触
をさせやすく好都合である。
Further, the whole of these is 100-350'O, typically 15
Sintering is performed for 15 to 30 minutes at a temperature of 0 to 200'O, and if necessary, soldering may be performed on the nickel film by immersing it in a hang bath for 5 to 10 seconds. The layer has a conductivity type of P or N type, and its electrical conductivity is typically 10 to 4 or more, which is advantageous because it facilitates ohmic contact.

00) その接触抵抗は10〜0.1.n/mmでアシ、実際上
全く支障がなかった。
00) Its contact resistance is 10-0.1. n/mm, there was practically no problem at all.

第1図においては従来よシも上側電極がアルミニューム
に比較して耐熱性を、有するニッケルを主成分として用
いたことによシ、半導体装置としての信頼性が100〜
1$5’O高温放置した際、15〜16倍も向上した。
In Fig. 1, the reliability of the semiconductor device is 100 to 100% because the upper electrode uses nickel, which has higher heat resistance than aluminum, as the main component.
When left at a high temperature of 1$5'O, it improved by 15 to 16 times.

また電極−の形成に強酸例えばフッ酸、硝酸、硫酸等を
用いず、トリクレン等の有機溶剤を用いたリフトオフ法
であるため、NO8,TC!Fがエツチングされるとと
もなく、加えてこの金属膜上にさら奴ハンダ等を選択的
に形成させ、膜としての抵抗を下げることが可能であシ
、部品として他のミーグ)IC等と接続しやすい等の特
徴を有する。
Furthermore, since the lift-off method does not use strong acids such as hydrofluoric acid, nitric acid, sulfuric acid, etc. to form the electrodes, but uses organic solvents such as trichlene, NO8, TC! As F is etched, it is also possible to selectively form bare solder etc. on this metal film to lower the resistance of the film, and to connect it with other MEG (IC) etc. as a component. It has characteristics such as easy to use.

加えてこの工程は一度に大面積の基体(10cm”〜5
0cm)を多量に制御することが可能であシ、真空蒸着
法を用いないため減価償却費が安価であるという特徴を
有する。
In addition, this process can handle large areas of substrates (10 cm to 5 cm) at one time.
It is possible to control a large amount of 0 cm), and since a vacuum deposition method is not used, depreciation costs are low.

さらに重要なことはNO8,TOFがきわめてやわらか
く、損傷を受けやすい材料であることは被膜の作製に電
子ビーム、スパッタ法、高温(再結合中心中和剤である
水素、ハロゲン元素、アルカリ金属元素が半導体である
珪素、ゲルマニュームと結合を切る温度すなわち350
’C以上の温度)処理を必要としない等、あらゆる面で
好ましいものである。
What is more important is that NO8 and TOF are extremely soft and easily damaged materials. The temperature at which the bond between silicon and germanium, which is a semiconductor, is broken is 350°C.
It is preferable in all respects, such as not requiring treatment (temperatures higher than 'C).

第1図(0)においてA M 1(1oomw/am)
 (30)の光照射において8.0〜12. o%/c
mを5cm’の光電変換装置で作ることができた。
In Figure 1 (0), A M 1 (1 oomw/am)
(30) 8.0-12. o%/c
m could be created using a 5 cm' photoelectric conversion device.

第2図は本発明方法を工程別に示したものである。図面
において無電界メッキされる金属はニッケルを主成分と
した金属にニッケルのみを含む)を示した。しかし本発
明方法はニッケルに限らずチタン、モリブデン等他の・
金属であっても同様である。
FIG. 2 shows the method of the present invention step by step. In the drawings, the metal to be electrolessly plated is a metal whose main component is nickel (including only nickel). However, the method of the present invention is applicable not only to nickel but also to other metals such as titanium and molybdenum.
The same applies to metals.

第3図は本発明を用いた他の実施例を示す。FIG. 3 shows another embodiment using the present invention.

第3図(4)は第1図(0)の光電変換装置を複数個集
積化して設けたものである。
FIG. 3(4) shows a device in which a plurality of photoelectric conversion devices of FIG. 1(0) are integrated.

すなわち照射洸(30)は透光性基板(〒)上に選択的
に設けられ、半導体(1)の一方の電極として設けられ
ている透明導電膜(3) 、 (d) 、 <<6をへ
て半導体(1)を照射し光電変換を行なう。この電子・
ホール対は一方の透明導電膜と他方の無電解メッキ法で
作られた金属例えばニツケ−ルを主成分六する裏面電極
(2) 、 (、i)、 <8にドリフトする。このニ
ッケル電極(2)は半導体(1)の裏面電極であシ、半
導体(i)の表面電極(勢と(5)にて連続しておシ、
また電極(山は(5)にて(喝と連続した3個の光電変
換装置を直列接続して外部接続端子(4)、(6)にて
3倍の電圧を得ようとしたものである。もちろんこれは
並列接続させてもよい0 第3図(B)は2個の絶縁ゲイト型電界効果半導体装置
を基板上に設けたものである。
In other words, the irradiation layer (30) is selectively provided on the transparent substrate (〒), and the transparent conductive film (3), (d), <<6 provided as one electrode of the semiconductor (1). Then, the semiconductor (1) is irradiated and photoelectric conversion is performed. This electronic
The hole pair drifts to a back electrode (2), (,i), whose main component is a transparent conductive film on one side and a metal such as nickel made by electroless plating on the other side. This nickel electrode (2) is the back electrode of the semiconductor (1), and the front electrode (5) of the semiconductor (i).
In addition, an attempt was made to obtain three times the voltage at the external connection terminals (4) and (6) by connecting three consecutive photoelectric conversion devices in series with the electrode (the crest is at (5)). Of course, these may be connected in parallel. FIG. 3(B) shows two insulated gate type field effect semiconductor devices provided on a substrate.

すなわち基板(マ)上に真性または実質的に真性の半導
体(8)を0.1〜1μの厚さに形成した。これは非晶
質であってもまたセミアモルファス構造(SASという
)を有する珪素半導体であってもよい。
That is, an intrinsic or substantially intrinsic semiconductor (8) was formed on the substrate (ma) to a thickness of 0.1 to 1 .mu.m. This may be amorphous or may be a silicon semiconductor having a semi-amorphous structure (referred to as SAS).

高い用:t 報$l I・1を有すまたは微結晶性を有
するセミアモルファス半導体が好ましい。かくすると単
結晶半導体膜きわめて近い電気伝導度]、XIO〜1×
10(二am))を有する。
For high applications: Semi-amorphous semiconductors having a t value of I·1 or having microcrystallinity are preferred. Thus, the electrical conductivity is very close to that of a single crystal semiconductor film], XIO ~ 1×
10 (2 am)).

さらにこの後この上面にPまたはN型のNCBの半導体
層をプラズマ気相法およびフォトエツチング法によシ選
択的に形成し、ソース(9) 、 (9)トレイン(1
0)、 (10’)とした。その後フィールド絶縁物(
39)をプラズマ気相法によシ酸化珪素を0.3〜3μ
の厚さに形成した。この後プラズマ+f/j化法によシ
ゲイト絶縁膜を前記した半導体層(9)(10)および
(8)、ま゛た(40ゐおよび(8)を酸化することに
よシ300〜100OAの厚さに形成した。この後プラ
ズマ水素のアニール法を行なった。
Furthermore, after this, a P or N type NCB semiconductor layer is selectively formed on this upper surface by plasma vapor phase method and photoetching method to form source (9), (9) train (1)
0), (10'). Then the field insulator (
39) to 0.3 to 3 μm of silicon oxide by plasma vapor phase method.
It was formed to a thickness of . Thereafter, by oxidizing the semiconductor layers (9), (10) and (8), and (40) and (8) on which the Sigate insulating film was formed using the plasma+f/j conversion method, a film of 300 to 100 OA was formed. After that, a plasma hydrogen annealing method was performed.

さらにこれらの上面に選択的に第1図、第2図と同様の
方法にてゲイト電極α転αう、ソースまたはドレインの
電極例えばαI、(J)を形成した。
Further, on the upper surfaces of these electrodes, a gate electrode α-transfer and source or drain electrodes such as αI and (J) were formed selectively in the same manner as in FIGS. 1 and 2.

この半導体装置はそのすべてにおいて350’0以下の
温度で処理を行なっており、単に集積化された絶縁ゲイ
ト型電界効果半導体装置のみでなく、イメージセンサ、
フォトトランジスタプレイとして用いることが可能であ
る。
All of this semiconductor device is processed at a temperature of 350'0 or below, and is not only an integrated insulated gate field effect semiconductor device, but also an image sensor,
It can be used as a phototransistor play.

第3図(0)は基板α・がステンレスよシなシ、P型半
導体層(ホ)、真性半導体層aL N型半導体層a→よ
シなるNO8αηおよびその上面に反射防止膜と電極と
をかねた透明導電膜(ハ)が設けられている。このTO
?上にくし型、魚骨型にニッケルの電極(イ)、外部引
出し電極Qヤが設けられ、さらKその電圧の抵抗を少な
くするためハンダに)が50〜300μの厚さにもられ
ている。
Figure 3 (0) shows a substrate α made of stainless steel, a P-type semiconductor layer (e), an intrinsic semiconductor layer aL, an N-type semiconductor layer a → a different NO8αη, and an anti-reflection film and an electrode on its upper surface. A transparent conductive film (c) is provided. This TO
? A comb-shaped, fishbone-shaped nickel electrode (A) and an external lead electrode (Q) are provided on the top, and a solder (K) is applied to a thickness of 50 to 300 μm to reduce the resistance of the voltage. .

照射光(30)によ]AMl下にて10〜14%を得る
ことができ、さらに耐久性の信頼性向上にきわめてすぐ
れたものであった。特にN型半導体層(IIをS i 
C!、、 (0< X(1)とし微結晶化してSAS構
造の1.8〜2.2eVのエネルギバンドを有せしめ工
型半導体層0Iは照射面よシ内部に向ってSASよpA
s (非晶質)に構造を連続的に菱えることによシ内部
電圧を0.3vも得ることができた。
It was possible to obtain 10 to 14% under AMl using irradiation light (30), and the reliability of durability was extremely improved. In particular, the N-type semiconductor layer (II is Si
C! ,, (0<
By continuously forming a structure in S (amorphous), we were able to obtain an internal voltage of as much as 0.3V.

またP型半導体層(ホ)もSin、 (0<X<1)と
してかたいP型半導体層とすることによシ、半導体作製
工程においてP4接合を完全にしその境界面に高抵抗バ
リヤ層をなくしたことが多の特徴であシ、最大13〜1
’4%/curl)得ることかで′きた。
In addition, by making the P-type semiconductor layer (E) a hard P-type semiconductor layer with Sin, (0<X<1), the P4 junction can be completed in the semiconductor manufacturing process, and a high-resistance barrier layer can be formed at the interface. The characteristic of many things that have been lost is 13 to 1 maximum.
I was able to get 4%/curl).

しかしこの図面でさらに重要なことは、ニッケル電極の
耐熱性の向上によ、9AM1であシュ00^凸 0C雰囲気下の連続照射においても信頼性の劣化が認め
られずきわめてすぐれたものであった。
However, what is even more important in this drawing is that due to the improved heat resistance of the nickel electrode, no deterioration in reliability was observed even in continuous irradiation in a 9AM1 ash 00^ convex 0C atmosphere, making it extremely excellent. .

導体装置に有効であシ、それらの効果はこれらの説明に
おいて大なることが判明したものと信する。
It is believed that these effects have been found to be great in these explanations.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明方法を示す半導体装置の作製工程を示す
たて断面図である。 第2図は本発明を示すフローチャートである。 第3図は本発明の他の半導体装置の実施例を示す。 察1図 #2図
FIG. 1 is a vertical sectional view showing the manufacturing process of a semiconductor device using the method of the present invention. FIG. 2 is a flowchart illustrating the present invention. FIG. 3 shows an embodiment of another semiconductor device of the present invention. Figure 1 #2 Figure

Claims (1)

【特許請求の範囲】 1、水素、ハロゲン元素またはアルカリ金属元素を含有
する非単結晶半導体または該半導体の電極として設けら
れた透明導電膜上に無電界メッキ法によシ選択的に金属
被膜をオーム接触を有する電極として350°C以下の
温度にて形成することを特徴とする半導体装置作製方法
。 2、特許請求の範囲第1項において、非単結晶半導体ま
たは透明導電膜上にレジストを選択的に被膜形成し、た
後活性化、無電解メッキ液に浸しニッケルを主成分とす
る金属被膜を形成した後リフトオフ法により前記レジス
トおよびその上面の前記金属被膜を助去することにより
前記半導体または透明導電膜上に選択的に金属被膜の電
極・IJ−ドを形成することを特徴とする半導体装置作
製方法。 3、特許請求の範囲第1項または第2項において、室温
〜100″′Cの温度で無電解メッキ工程、50〜20
0’Oでのメッキ被膜の乾燥工程または50〜350’
Oでの半導体膜とのオーム接触の形成工程がなされるこ
とを特徴とする半導体装置作製方法。
[Claims] 1. A metal coating is selectively formed by electroless plating on a non-single crystal semiconductor containing hydrogen, a halogen element, or an alkali metal element, or a transparent conductive film provided as an electrode of the semiconductor. A method for manufacturing a semiconductor device, characterized in that an electrode having ohmic contact is formed at a temperature of 350°C or less. 2. In claim 1, a resist is selectively formed on a non-single crystal semiconductor or a transparent conductive film, and then activated and immersed in an electroless plating solution to form a metal film mainly composed of nickel. A semiconductor device characterized in that an electrode/IJ-de of a metal film is selectively formed on the semiconductor or transparent conductive film by removing the resist and the metal film on the upper surface thereof by a lift-off method after formation. Fabrication method. 3. In claim 1 or 2, the electroless plating step is performed at a temperature of room temperature to 100''C, 50 to 20
Drying process of plating film at 0'O or 50-350'
1. A method for manufacturing a semiconductor device, comprising a step of forming an ohmic contact with a semiconductor film using O.
JP56122707A 1981-08-05 1981-08-05 Manufacture of semiconductor device Pending JPS5823489A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56122707A JPS5823489A (en) 1981-08-05 1981-08-05 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56122707A JPS5823489A (en) 1981-08-05 1981-08-05 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5823489A true JPS5823489A (en) 1983-02-12

Family

ID=14842612

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56122707A Pending JPS5823489A (en) 1981-08-05 1981-08-05 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5823489A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59150485A (en) * 1983-02-16 1984-08-28 Semiconductor Energy Lab Co Ltd Photoelectric conversion semiconductor device
JPS6030180A (en) * 1983-07-28 1985-02-15 Matsushita Electric Ind Co Ltd Amorphous thin film photovoltaic element
JPS6066426A (en) * 1983-08-19 1985-04-16 エナージー・コンバーション・デバイセス・インコーポレーテッド Improving method for bonding conductive metal material in preselected pattern on transparent conductive layer of semiconductor element
JPS60262470A (en) * 1984-06-08 1985-12-25 Kanegafuchi Chem Ind Co Ltd Semiconductor device
JPS62281376A (en) * 1986-05-29 1987-12-07 Kyocera Corp Photovoltaic device
US7452749B2 (en) * 2005-03-02 2008-11-18 Nec Electronics Corporation Method for manufacturing flip-chip type semiconductor device featuring nickel electrode pads, and plating apparatus used in such method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59150485A (en) * 1983-02-16 1984-08-28 Semiconductor Energy Lab Co Ltd Photoelectric conversion semiconductor device
JPS6030180A (en) * 1983-07-28 1985-02-15 Matsushita Electric Ind Co Ltd Amorphous thin film photovoltaic element
JPS6066426A (en) * 1983-08-19 1985-04-16 エナージー・コンバーション・デバイセス・インコーポレーテッド Improving method for bonding conductive metal material in preselected pattern on transparent conductive layer of semiconductor element
JPH0515071B2 (en) * 1983-08-19 1993-02-26 Enaajii Konbaajon Debaisesu Inc
JPS60262470A (en) * 1984-06-08 1985-12-25 Kanegafuchi Chem Ind Co Ltd Semiconductor device
JPS62281376A (en) * 1986-05-29 1987-12-07 Kyocera Corp Photovoltaic device
US7452749B2 (en) * 2005-03-02 2008-11-18 Nec Electronics Corporation Method for manufacturing flip-chip type semiconductor device featuring nickel electrode pads, and plating apparatus used in such method

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