JPH01243555A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH01243555A
JPH01243555A JP63069697A JP6969788A JPH01243555A JP H01243555 A JPH01243555 A JP H01243555A JP 63069697 A JP63069697 A JP 63069697A JP 6969788 A JP6969788 A JP 6969788A JP H01243555 A JPH01243555 A JP H01243555A
Authority
JP
Japan
Prior art keywords
film
bump
substrate
parts
bump electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63069697A
Other languages
Japanese (ja)
Other versions
JP2672557B2 (en
Inventor
Shigeru Osawa
滋 大澤
Susumu Kimijima
君島 進
Shoichi Inoue
正一 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63069697A priority Critical patent/JP2672557B2/en
Publication of JPH01243555A publication Critical patent/JPH01243555A/en
Application granted granted Critical
Publication of JP2672557B2 publication Critical patent/JP2672557B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To obtain an infrared image sensing element at a good yield by a method wherein openings are formed in parts where two or more bump electrodes are to be formed and in a peripheral part of a substrate where the bump electrodes are not formed and two or more bumps are formed at the openings by a plating method. CONSTITUTION:Signal input contact parts 12 are formed on the surface of an Si substrate 11; Al electrodes 13 and an insulating layer 14 are formed on the surface. A Ti film 15 and, then, a Cu film 16 are formed on this surface. Openings 17c, 17d are formed in photoresist films 17a, 17b in parts where bump electrodes are to be formed and in parts which are adjacent to the parts and where the bump electrodes are not formed. The photoresist film in the parts where the bump electrodes are not formed is exposed to light. A Cu layer 18 and, then, an In layer 19 are formed by a plating method. An exposed photoresist film 27 in the parts where the bump electrodes are not formed is developed and removed. The substratum Cu film 16 in an exposed part and a bump in the parts where the bump electrodes are not formed are removed. By this setup, it is possible to obtain an infrared image sensing element at a good yield.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は半導体装置の製造方法に係り、特に基板に複数
の金属電極が形成されこれにバンプ電極が形成された半
導体装置の製造に適用される。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a semiconductor device in which a plurality of metal electrodes are formed on a substrate and bump electrodes are formed thereon. Applicable to the manufacture of

(従来の技術) 本発明に係るバンプ電極を有する半導体装置の製造方法
を赤外線撮像素子(rnfra−Red CCD、以下
Ir1CCDと略称する)の製造方法を例示して以下に
説明する。
(Prior Art) A method for manufacturing a semiconductor device having bump electrodes according to the present invention will be described below by exemplifying a method for manufacturing an infrared imaging device (RNFRA-Red CCD, hereinafter abbreviated as Ir1CCD).

IRCCDでは、赤外線センサーとして良好な半導体材
料である、例えばIn5b(インジウム・アンチモン)
や、IIgCdTe (水銀・カドミウム・テルル)な
どの基板に光ダイオードを格子状に形成したものを受光
部とし、この受光部で発生する電子を、各セルごとに5
i−COD素子に転送して画像を得る。この方法は、受
光部、及び5i−CCD部の特性を各々最適にすること
ができるので、最も一般的に用いられる方法である。各
セルを接続するには、普通双方にInなどの軟らかい金
属を形成し、対応する電極を突合わせて接続する、いわ
ゆるバンプ電極構造が用いられる。
IRCCD uses semiconductor materials that are good for infrared sensors, such as In5b (indium antimony).
The light receiving section is a grid of photodiodes formed on a substrate such as IIgCdTe (mercury, cadmium, tellurium), etc., and the electrons generated in this light receiving section are divided into 5
It is transferred to the i-COD device to obtain an image. This method is the most commonly used method because it can optimize the characteristics of the light receiving section and the 5i-CCD section. To connect each cell, a so-called bump electrode structure is usually used in which a soft metal such as In is formed on both sides and the corresponding electrodes are butted and connected.

次に、叙上の如き用途に供される、従来のバンプ電極を
有する5i−CCDの製造方法につき、第2図を参照し
て次に説明する。
Next, a method for manufacturing a conventional 5i-CCD having bump electrodes, which is used for the above-mentioned applications, will be described with reference to FIG.

第2図aは、バンプ電極を形成する前の5i−CCDの
要部断面を示し、Si基板101の表面には、信号入力
コンタクト部102が64 X 64個形成され1表面
上にはA1電極103と、例えばSiO□等の絶縁層1
04が形成されている。この上に全面に蒸着、あるいは
スパッタ法によりTi膜105. Cu膜106を順次
形成する。次に、フォトレジスト19107を形成し、
バンプ電極を形成する部分のフォトレジスト膜107に
開口部107aを形成する(第2図b)。続いて選択メ
ツキ法によりCu層108. ■n層109を順次形成
する。
FIG. 2a shows a cross section of the main part of the 5i-CCD before forming the bump electrodes. On the surface of the Si substrate 101, 64×64 signal input contact portions 102 are formed, and on one surface there is an A1 electrode. 103 and an insulating layer 1 of SiO□, for example.
04 is formed. A Ti film 105 is deposited on the entire surface by vapor deposition or sputtering. Cu films 106 are sequentially formed. Next, photoresist 19107 is formed,
An opening 107a is formed in the photoresist film 107 in a portion where a bump electrode is to be formed (FIG. 2b). Subsequently, a Cu layer 108 is formed using a selective plating method. (2) N-layers 109 are sequentially formed.

(第2図C)。次に、前記フォトレジスト膜107を除
去(第2図d)したのち、前記In層109をマスクと
して前記Cu膜106. Ti膜105を順次エツチン
グにより除去してInバンプ電極が形成される(第2図
e)。
(Figure 2C). Next, after removing the photoresist film 107 (FIG. 2d), using the In layer 109 as a mask, the Cu film 106. The Ti film 105 is sequentially removed by etching to form In bump electrodes (FIG. 2e).

前記従来の方法で形成されたバンプ電極は、第2図eに
示す様に、バンプ電極を形成した領域の周辺部のバンプ
電極の高さが、中央部のバンプ電極の高さに比べて高く
なる。
In the bump electrode formed by the conventional method, as shown in FIG. 2e, the height of the bump electrode at the periphery of the area where the bump electrode is formed is higher than that at the center. Become.

(発明が解決しようとする課題) 叙上の従来の方法によって基板上に形成されるバンプ電
極の高さが1周辺部が中央部に比べて高くなる。これは
電気メツキ特有の現象で、パターン周辺部で電流密度が
大きくなるためである。この様にメツキの厚みのばらつ
きがあるため、同様にして、Inバンプを形成した受光
部と、対応する端子電極を突合わせて一体化したときに
、基板中央部のInバンプ電極の高さが低いので接続さ
れず、そのため、その部分が画像欠陥になるという解決
すべき課題があった。
(Problems to be Solved by the Invention) The height of the bump electrode formed on the substrate by the above-mentioned conventional method is higher at one peripheral portion than at the central portion. This is a phenomenon unique to electroplating, and is due to the fact that the current density increases at the periphery of the pattern. Because of this variation in the plating thickness, when the light receiving area on which In bumps are formed and the corresponding terminal electrodes are butted together and integrated, the height of the In bump electrodes at the center of the substrate will be There was a problem to be solved in that it was not connected because it was low, resulting in an image defect in that part.

本発明は上記の点に鑑みなされたもので、複数のバンプ
電極の高さを均一化し、よって対向する基板の端子電極
との突合わせ接続を、確実に行い得るように改良された
バンプ電極を有する半導体装置の製造方法を提供するこ
とを目的とする。
The present invention has been made in view of the above points, and provides an improved bump electrode that makes the height of a plurality of bump electrodes uniform, thereby making it possible to reliably butt connect the terminal electrodes of the opposing substrate. An object of the present invention is to provide a method for manufacturing a semiconductor device having the following methods.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 本発明にかかる半導体装置の製造方法は、複数の電極が
形成された基板上に金属膜を形成する工程と、前記金属
膜上に2オドレジスト膜を形成する工程と、前記フォト
レジスト膜に対し複数のバンプ電極が形成される部分お
よびバンプ電極が形成されない基板周縁の部分にも開口
部を形成する工程と、前記開口部に選択めっき法により
複数層のバンプを形成する工程と、前記バンプ電極が形
成されない基板周縁の部分のフォトレジスト膜に露光を
施してこれを除去する工程と、前記基板周縁の部分のバ
ンプを除去する工程を含むものである。
(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a step of forming a metal film on a substrate on which a plurality of electrodes are formed, and a step of forming a 2-odresist film on the metal film. a step of forming openings in the photoresist film at a portion where a plurality of bump electrodes are to be formed and at a peripheral edge of the substrate where no bump electrodes are to be formed; and forming a plurality of layers of bumps in the openings by selective plating. The method includes a step of forming a photoresist film, a step of exposing and removing a photoresist film at a portion of the peripheral edge of the substrate where the bump electrode is not formed, and a step of removing the bump at the portion of the peripheral edge of the substrate.

(作 用) 本発明により形成したバンプ電極は、高さが揃っている
ため、5i−CODと受光部とを対応する端子電極を突
合わせて一体化したときに、全面で均一に圧着されて電
気的導通が得られることから水留り良< IR−CCD
を作ることが出来る。
(Function) Since the bump electrodes formed according to the present invention have the same height, when the 5i-COD and the light receiving part are integrated by butting the corresponding terminal electrodes, the bump electrodes formed according to the present invention are crimped uniformly over the entire surface. Water retention is good because electrical continuity is obtained < IR-CCD
can be made.

(実施例) 以下、本発明の−っの実施例を図面を参照して説明する
(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第1図aはバンプを形成する前の5i−CCDの要部断
面を示し、Si基板110表面には信号入力コンタクト
部12が80μmピッチで64 X 64個形成され、
表面上にはAlff1極13と、例えば5un2等のM
縁、1Wi4が形成されている。この表面にTi膜15
、次いでCu膜を蒸着法によって形成する。rigts
はバリヤメタルであり、Cu膜16はメツキ用の電極膜
である。
FIG. 1a shows a cross section of the main part of the 5i-CCD before bumps are formed, and 64×64 signal input contact portions 12 are formed on the surface of the Si substrate 110 at a pitch of 80 μm.
On the surface, there is Alff1 pole 13 and M such as 5un2.
Edge, 1Wi4 is formed. Ti film 15 on this surface
Then, a Cu film is formed by a vapor deposition method. rigts
is a barrier metal, and the Cu film 16 is an electrode film for plating.

次いでポジ形のフォトレジスト膜17を全面に形成し、
次にバンプ電極を形成する部分、及びそれに近接したバ
ンプ電極を形成しない部分のフォトレジスト膜17a、
17bに20 μm X 20 μmの開口部17c。
Next, a positive photoresist film 17 is formed on the entire surface,
Next, a photoresist film 17a in a portion where a bump electrode is to be formed and a portion in which a bump electrode is not to be formed adjacent thereto;
17b has an opening 17c of 20 μm x 20 μm.

17dを設ける(第1図b)。信号入力コンタクト部の
外側に形成するバンプの列の数は、64 x 64個の
バンプの均一度を見て決めるのが望ましいが、5列形成
すると、かなり均一にすることが出来る6次に、前記バ
ンプ電極を形成しない部分のフォトレジスト膜を感光せ
しめる。図中の27は感光したフォトレジスト膜である
(第1図C)。
17d (Fig. 1b). The number of bump rows to be formed on the outside of the signal input contact section is preferably determined by looking at the uniformity of 64 x 64 bumps, but if five rows are formed, the number of bumps can be fairly uniform. A portion of the photoresist film where the bump electrode is not formed is exposed to light. 27 in the figure is a photoresist film exposed to light (FIG. 1C).

次に、フォトレジスト膜17が感光しない様にCu層1
8を次いでInJ119をいずれもメツキにて形成する
(第1図d)。
Next, the Cu layer 1 is made so that the photoresist film 17 is not exposed to light.
8 and then InJ119 is formed by plating (FIG. 1d).

次に、前記Cu層18は1例えば基板を硫酸銅浴のCu
メツキ液中に浸し、室温にて下地金属膜のCu膜16を
電極とし、所定電流にて数十分メツキを行って形成する
。これにより、十数μmの厚みのCuJ118が形成さ
れる。また、 In層19は、前記Cu層18が形成さ
れた基板を硼ふっ化浴に浸し、所定の電極値にて数十分
メツキを行うことにより、十数μmの厚さに形成される
。このとき、バンプを形成した領域の周辺部(バンプ電
極を形成しない部分)ではバンプは高くなるが、バンプ
を形成した中央部(バンプ電極を形成する部分)ではバ
ンプの高さはほぼ同じになる。次に、前記バンプ電極を
形成しない部分の感光したフォトレジスト膜27を現像
して除去する(第1図e)。
Next, the Cu layer 18 is coated with a copper sulfate bath.
It is immersed in a plating solution and plated at room temperature using the Cu film 16 as the underlying metal film as an electrode for several minutes at a predetermined current. As a result, CuJ 118 having a thickness of more than ten μm is formed. Further, the In layer 19 is formed to a thickness of more than ten μm by immersing the substrate on which the Cu layer 18 is formed in a borofluoride bath and plating it at a predetermined electrode value for several tens of minutes. At this time, the height of the bump becomes higher at the periphery of the area where the bump is formed (the area where the bump electrode is not formed), but the height of the bump is approximately the same at the central area where the bump is formed (the area where the bump electrode is formed). . Next, the exposed portions of the photoresist film 27 where the bump electrodes will not be formed are developed and removed (FIG. 1e).

次に、Cuのエッチャントで露出部の下地Cu膜16、
及びバンプ電極を形成しない部分のバンプを除去する(
第1図f)。
Next, the base Cu film 16 of the exposed portion is treated with a Cu etchant.
and remove bumps in areas where bump electrodes will not be formed (
Figure 1 f).

次いで、フォトレジス1〜膜17を除去し、残ったバン
プ電極間の下地のCu膜16をエツチングで除去し、次
にTi膜15をエツチングで除去する。この様に、バン
プを形成した領域で周辺部の高い不要のバンプを除去す
ることにより、高さの揃ったバンプ電極を有する5i−
CCDが得られる。(第1図g)。
Next, the photoresist 1 to film 17 are removed, the underlying Cu film 16 between the remaining bump electrodes is removed by etching, and then the Ti film 15 is removed by etching. In this way, by removing unnecessary high bumps on the periphery of the bump-formed area, the 5i-
A CCD is obtained. (Figure 1g).

〔発明の効果〕〔Effect of the invention〕

以上述べたように1本発明によればバンプ電極の高さが
全面で揃っているので、同様にして受光部にもバンプを
形成した後1図示を省略した平行度の高い圧接装置を用
い、 5i−CCD基板と受光部を対向して保持し、所
定の温度・圧力で数分間圧接して一体化させる。このよ
うにすれば、圧接の圧力が全面で均一にかかるので、端
子電極の接続が確実に行われて歩留り良< IRCCD
を得ることが出来る。
As described above, according to the present invention, the height of the bump electrodes is the same over the entire surface, so after forming bumps on the light receiving part in the same way, using a pressure welding device with high parallelism (not shown), The 5i-CCD substrate and the light receiving section are held facing each other and are pressed together at a predetermined temperature and pressure for several minutes to integrate them. In this way, the pressure of pressure welding is applied uniformly over the entire surface, ensuring that the terminal electrodes are connected reliably, resulting in a high yield.
can be obtained.

本発明は上記実施例に限られるものではなく、その趣旨
を逸脱しない範囲で種々変形実施することが出来る。例
えば、エツチングで除去するバンプの径の大きさは、所
定部分のバンプの大きさと異なっても良い。また、バン
プ電極を形成しない部分の開口部の列の数も、メツキの
均一度を見て適当に決めることが出来る。
The present invention is not limited to the above-described embodiments, and can be modified in various ways without departing from the spirit thereof. For example, the size of the diameter of the bump removed by etching may be different from the size of the bump in a predetermined portion. Furthermore, the number of rows of openings in the portion where bump electrodes are not formed can be appropriately determined by considering the uniformity of plating.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a−gは本発明にかかる一実施例のバンプ電極の
製造方法を工程順に示すいずれも断面図。 第2図g ”−’ eは従来例のバンプ電極の製造方法
を工程順に示すいずれも断面図である。 11・・・基板    12・・・信号入力コンタクト
部13・・・AI電極   14・・・絶縁層15・・
・Ti膜     16・・・Cu膜17・・・フォト
レジスト(未感光)膜27・・・フォトレジスト(感光
)膜
FIGS. 1a to 1g are cross-sectional views showing a method for manufacturing a bump electrode according to an embodiment of the present invention in the order of steps. Figure 2g''-'e are cross-sectional views showing the conventional bump electrode manufacturing method in the order of steps. 11...Substrate 12...Signal input contact portion 13...AI electrode 14...・Insulating layer 15...
・Ti film 16...Cu film 17...Photoresist (unsensitized) film 27...Photoresist (photosensitive) film

Claims (2)

【特許請求の範囲】[Claims] (1)複数の電極が形成された基板上に金属膜を形成す
る工程と、前記金属膜上にフォトレジスト膜を形成する
工程と、前記フォトレジスト膜に対し複数のバンプ電極
が形成される部分およびバンプ電極が形成されない基板
周縁の部分に開口部を形成する工程と、前記開口部に選
択めっき法により複数のバンプを形成する工程と、前記
バンプ電極が形成されない基板周縁の部分のフォトレジ
スト膜に露光を施してこれを除去する工程と、前記基板
周縁の部分のバンプを除去する工程を含む半導体装置の
製造方法。
(1) A step of forming a metal film on a substrate on which a plurality of electrodes are formed, a step of forming a photoresist film on the metal film, and a portion where a plurality of bump electrodes are formed on the photoresist film. and a step of forming an opening in a portion of the peripheral edge of the substrate where no bump electrode is formed, a step of forming a plurality of bumps in the opening by a selective plating method, and a photoresist film on a portion of the peripheral edge of the substrate where the bump electrode is not formed. A method for manufacturing a semiconductor device, comprising: exposing and removing bumps on the substrate; and removing bumps on a peripheral edge of the substrate.
(2)金属膜を溶解しバンプを溶解しないエッチング剤
で基板周縁の部分のバンプを除去することを特徴とする
請求項1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the bumps at the peripheral edge of the substrate are removed using an etching agent that dissolves the metal film but does not dissolve the bumps.
JP63069697A 1988-03-25 1988-03-25 Method for manufacturing semiconductor device Expired - Lifetime JP2672557B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63069697A JP2672557B2 (en) 1988-03-25 1988-03-25 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63069697A JP2672557B2 (en) 1988-03-25 1988-03-25 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01243555A true JPH01243555A (en) 1989-09-28
JP2672557B2 JP2672557B2 (en) 1997-11-05

Family

ID=13410310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63069697A Expired - Lifetime JP2672557B2 (en) 1988-03-25 1988-03-25 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2672557B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274102A (en) * 1995-03-31 1996-10-18 Nec Corp Method for forming in bump
JP2016189404A (en) * 2015-03-30 2016-11-04 富士通株式会社 Terminal manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274102A (en) * 1995-03-31 1996-10-18 Nec Corp Method for forming in bump
JP2016189404A (en) * 2015-03-30 2016-11-04 富士通株式会社 Terminal manufacturing method

Also Published As

Publication number Publication date
JP2672557B2 (en) 1997-11-05

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