JPS6085577A - Manufacture of thin film photoelectric conversion element - Google Patents
Manufacture of thin film photoelectric conversion elementInfo
- Publication number
- JPS6085577A JPS6085577A JP58193633A JP19363383A JPS6085577A JP S6085577 A JPS6085577 A JP S6085577A JP 58193633 A JP58193633 A JP 58193633A JP 19363383 A JP19363383 A JP 19363383A JP S6085577 A JPS6085577 A JP S6085577A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- film
- photoelectric conversion
- conversion element
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010409 thin film Substances 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 10
- 238000009713 electroplating Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 230000015572 biosynthetic process Effects 0.000 claims abstract 5
- 239000010408 film Substances 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 4
- 238000007747 plating Methods 0.000 abstract description 13
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 239000011651 chromium Substances 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- 229910052804 chromium Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical group [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 3
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910017604 nitric acid Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910000365 copper sulfate Inorganic materials 0.000 description 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000012153 distilled water Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003792 electrolyte Substances 0.000 description 1
- 239000008151 electrolyte solution Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/208—Particular post-treatment of the devices, e.g. annealing, short-circuit elimination
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Development (AREA)
- Sustainable Energy (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、薄膜光電変換素子の製造□方法に係り、特に
、サンドイッチ型の薄膜光電変換素子の製造方法に関す
る・。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film photoelectric conversion element, and particularly relates to a method for manufacturing a sandwich type thin film photoelectric conversion element.
最近、太陽電池やイメージセンサ等の大面積化、長尺化
に伴い、大面積にわたって堆積可能にアモルファスシリ
コン等の光電変換薄膜を用いた薄膜光電変換素子の開発
が進められている。BACKGROUND ART Recently, as solar cells, image sensors, etc. have become larger in area and longer in length, development of thin film photoelectric conversion elements using photoelectric conversion thin films such as amorphous silicon that can be deposited over large areas has been progressing.
特に、イメージセンナの場合、原稿と同一幅をもつセン
ナ部を形成することにょ力、１対１結像が可能となり、
原稿とセンサ部とを密着させることができると共に、縮
小光学系が不要となることによシ、原稿読み取り部の小
型化が容易に可能となる。In particular, in the case of an image sensor, it is possible to form a sensor part with the same width as the document, and one-to-one imaging is possible.
Since the document and the sensor section can be brought into close contact with each other and a reduction optical system is not required, it is possible to easily downsize the document reading section.
薄膜光電変換素子は、構造的に見て、第１電極と第２電
極とによって光導電体層をはさんだサンドイッチ構造と
、光導電体層上に対向電極を形成したプレーナ構造とに
大別されるが、センサ部の高密度化の観点からみて、通
常はサンドイッチ構造のものを使用することが多い。Thin film photoelectric conversion elements are structurally divided into two types: a sandwich structure in which a photoconductor layer is sandwiched between a first electrode and a second electrode, and a planar structure in which a counter electrode is formed on the photoconductor layer. However, from the viewpoint of increasing the density of the sensor section, a sandwich structure is usually used.
ところで、サンドイッチ構造の光電変換素子は、例えば
セラミック基板上に着膜形成された複数個のクロム電極
（第１電極）と透光性の酸化インジウム錫（ＴＴＯ）電
極（第２電極）とによって光導電体層としてのアモルフ
ァスシリコン層を挾んだ構造をとっている。このアモル
ファスシリコン層は、モノシランガス（５ＩＨ４）のグ
ロー放電分解法等によって、クロム電極上に堆積せしめ
られるわけであるが、堆積されるべき面積が大きくなれ
ばなるほど、全面にわたって均一なアモルファスシリコ
ン層を形成するのは難しく、ピンホールの発生をまぬが
れ得ないことがある。これは、製造装置内のダストが基
板表面に付着すること等の外因の他に、薄膜成長のメカ
ニズムと関係する内因をもつことが多いためである。By the way, a photoelectric conversion element having a sandwich structure is configured to emit light using, for example, a plurality of chromium electrodes (first electrode) and a translucent indium tin oxide (TTO) electrode (second electrode) formed as a film on a ceramic substrate. It has a structure with amorphous silicon layers sandwiched between them as conductive layers. This amorphous silicon layer is deposited on the chromium electrode by glow discharge decomposition of monosilane gas (5IH4), etc., but the larger the area to be deposited, the more uniform the amorphous silicon layer will be over the entire surface. It is difficult to do so, and pinholes may occur. This is because, in addition to external causes such as dust in the manufacturing equipment adhering to the substrate surface, there are often internal causes related to the thin film growth mechanism.
ここで、サンドイッチ構造の光電変換素子において、光
導電体層にピンホールが存在することによって生じる素
子としての機能の変化を考えてみる。Here, in a photoelectric conversion element having a sandwich structure, a change in the function of the element caused by the presence of a pinhole in the photoconductor layer will be considered.
オず、サンドイッチ構造の光電変換素子の最も簡単表等
側回路を考えると、第１図に示す如くなる。直列抵抗Ｒ
３け、電極の接触抵抗と外部回路の抵抗との和であり、
並列抵抗Ｒ１１ｈは光導電体層自体の抵抗でちる。ここ
で、光導電体層にピンホールが無く、第１電極と第２電
極との間でショートが発生しなければ並列抵抗Ｒａｈは
無限大に）と考えて良い。第１図中、■、は入射光の強
度に比例した光電流、Ｉｊはダイオードに流れる電流、
■ｓｈは、ショート等によるもれ電流である。If we consider the simplest front-to-side circuit of a sandwich-structured photoelectric conversion element, it will be as shown in FIG. Series resistance R
Number 3 is the sum of the contact resistance of the electrode and the resistance of the external circuit,
The parallel resistance R11h is determined by the resistance of the photoconductor layer itself. Here, if there is no pinhole in the photoconductor layer and no short circuit occurs between the first electrode and the second electrode, the parallel resistance Rah can be considered to be infinite. In Figure 1, ■ is a photocurrent proportional to the intensity of incident light, Ij is a current flowing through the diode,
(2) sh is a leakage current due to a short circuit or the like.
ここで外部回路を流れる電流を１とすると、１ ＝−ｒ
、＋ｒｊ＋ｒ、ｈ ・・−・・（１）が成立する。Here, if the current flowing through the external circuit is 1, then 1 = -r
,+rj+r,h...(1) holds true.
光導電体層にピンホールの無い理想的な光電変換素子即
ち、並列抵抗Ｒｓｈ−ω、ＲＦ、＝０の場合の電流−電
圧特性曲線（１−ｖ曲線）を第２図に示す。ここで、■
ｌは光入射時の特性曲線、Ｉ２は、暗時の特性曲線であ
る。Ｒｓｈ””ωであるからＩ ｚＱであり、光入射時
には光電流−ＩＬが支配ｈ
的とカリ、暗時においては、ダイオードを流れる電流１
、が支配的となる。FIG. 2 shows a current-voltage characteristic curve (1-v curve) for an ideal photoelectric conversion element without pinholes in the photoconductor layer, that is, for parallel resistance Rsh-ω, RF, = 0. Here,■
1 is a characteristic curve when light is incident, and I2 is a characteristic curve when it is dark. Since Rsh""ω, IzQ, and when light is incident, the photocurrent -IL is dominant, and in the dark, the current flowing through the diode is 1
, becomes dominant.
ここで、光導電体層において、第１電極と第２電極とが
重なシ合う部分にピンホールが発生すると、第１電極と
第２電極との間が一部短絡し、並列抵抗Ｒｓｈが大幅に
減少する。この場合の電流−電圧特性曲線を第３図に示
す。ここではＲ＝Ｑとしておく。Ｉ３は光入射時の特性
曲線、Ｉ４は、暗時の特性曲線である。Here, if a pinhole occurs in the photoconductor layer where the first electrode and the second electrode overlap, a short circuit will occur between the first electrode and the second electrode, and the parallel resistance Rsh will increase. significantly reduced. The current-voltage characteristic curve in this case is shown in FIG. Here, it is assumed that R=Q. I3 is a characteristic curve when light is incident, and I4 is a characteristic curve when it is dark.
この場合、たとえば、ダイオード電流ｒ、ＺＯの・々イ
アス領域では関係式（１）は、
■ター１． ＋ ｌ５ｈ
２−■ ＋−・・−・・（２）
Ｒｓｈ
となシ、光照射時においても暗時においても、電流■の
電圧Ｖ依存性が大きいことからもわかるように、第２図
に示された理想的な光電変換素子のもつ特性に比べて、
大幅に特性が低下している。In this case, for example, in the diode current r and ZO region, the relational expression (1) becomes: (1). + l5h 2-■ +-...-... (2) Rsh As can be seen from the large dependence of the current on the voltage V both during light irradiation and in the dark, Figure 2 shows that Compared to the characteristics of the ideal photoelectric conversion element shown,
Characteristics have significantly deteriorated.
すなわち、太陽電池においては、順バイアス領域すなわ
ちＬＶ〉０領域が利用されるが、理想的な光電変換素子
の場合に比べ、ピンホールを有する場合は変換効率が悪
い。That is, in a solar cell, a forward bias region, that is, a LV>0 region is used, but the conversion efficiency is lower in the case of a pinhole than in the case of an ideal photoelectric conversion element.
一方、イメージセンサでは、逆バイアス領域すなわちＶ
〈０の領域を利用するが、理想的な光電変換素子に比べ
、明暗比が大幅に低下している。On the other hand, in an image sensor, the reverse bias region, that is, V
Although the <0 region is utilized, the contrast ratio is significantly lower than that of an ideal photoelectric conversion element.
このように、光電変換素子の光導電体層におけるピンホ
ールの発生は、太陽電池においては、変換効率の低下お
よび開放端電圧の低下をもたらし、イメージセンサにお
いては光学像の読み取り能力の低下を招く等、致命的な
欠陥であシ、素子としての製造歩留りの低下が太き々問
題となっている。In this way, the occurrence of pinholes in the photoconductor layer of a photoelectric conversion element leads to a decrease in conversion efficiency and open-circuit voltage in solar cells, and a decrease in the ability to read optical images in image sensors. These are fatal defects, and a decline in the manufacturing yield of devices has become a serious problem.
本発明は、前記実情に鑑みてなされたもので、万一、光
導電体層にピンホールが発生した場合にも、素子特性に
太き々影響を及ぼすことのないようにし、光電変換素子
の製造歩留りの低下を防ぐことを目的とする。The present invention has been made in view of the above-mentioned circumstances, and even if a pinhole occurs in the photoconductor layer, the device characteristics will not be significantly affected, and the photoelectric conversion device can be improved. The purpose is to prevent a decline in manufacturing yield.
〔発明の構成〕
前記目的を達成するため、本発明の方法は、第１電極上
に形成された光導電体層すなわち、光電変換膜中にピン
ホールが発生した場合にも、その上すなわち、ピンホー
ルに第２電極が堆積しないようにし、第１電極と第２電
極との間の短絡を防ごうとするものである。[Structure of the Invention] In order to achieve the above-mentioned object, the method of the present invention is applicable to the case where a pinhole is generated in the photoconductor layer, that is, the photoelectric conversion film formed on the first electrode, and also to This is intended to prevent the second electrode from being deposited in the pinhole and to prevent short circuits between the first and second electrodes.
すなわち、サンドイッチ構造の光電変換素子を、製造す
るにあたり、基板上に形成された第１電極上に光電変換
膜を着膜した後、電解メッキを行なうことにより、前記
光電変換膜中に露呈する第１電極上に金属を析出させる
工程と、次いで第２電極を着膜形成した後に１析出され
た前記金属をエツチング除去することにより、金属上の
第２電極を除去する工程とを含むことを特徴とするもの
である。That is, when manufacturing a photoelectric conversion element having a sandwich structure, a photoelectric conversion film is deposited on a first electrode formed on a substrate, and then electrolytic plating is performed to remove the first electrodes exposed in the photoelectric conversion film. It is characterized by comprising a step of depositing a metal on one electrode, and then a step of removing the second electrode on the metal by etching and removing the deposited metal after forming a second electrode. That is.
以下、本発明の光電変換素子の製造方法について、図面
を参照しつつ実施例に基づいて説明する。EMBODIMENT OF THE INVENTION Hereinafter, the manufacturing method of the photoelectric conversion element of this invention is demonstrated based on an Example with reference to drawings.
まず、商品名コーニング７０５９≠とじて市販されてい
るガラス基板１０表面金体に蒸着法によって、膜厚的２
０００にのクロムＣｒ膜を堆積した後、フォトリソグラ
フィー法にょ勺、第４図に示す如く第１電極としてのク
ロム電極２のツクターニングを行なう。First, a film with a film thickness of 2
After depositing a chromium Cr film of 0.000 mm, the chromium electrode 2 serving as the first electrode is turned by photolithography as shown in FIG.
次いで、モノシランガス（５ＩＨ４）のグロー放電分解
法によって、第５図に示す如く光電変換膜としてのアモ
ルファス水素化シリコン層３を膜厚的１μｍとなるよう
に堆積する。Next, as shown in FIG. 5, an amorphous hydrogenated silicon layer 3 as a photoelectric conversion film is deposited to a thickness of 1 μm by glow discharge decomposition of monosilane gas (5IH4).
この後、硫酸銅ＣｕＳＯ４・５Ｈ２０＋蒸留水をメッキ
液とし、陽極としてプラチナ板（ｐｔ ）を使用してな
る電解メッキ処理装置を使用し、銅のメッキ生成膜４を
ピンホールすなわち、光電変換膜内のクロム電極露呈部
に生成させる。この電解メッキ処理装置は、第９図に示
す如く、電解液槽３１内に浸漬された陽極３２と陰極３
３とよりなるもので・ガラス基板１をメッキ液内に浸漬
し、陰極３３に前記クロム電極２を接続せしめ、これと
該陽極との間に約６ｖの電圧を印加し、暗所で、約１分
間通電する。このようにして第６図に示す如く、前記ア
モルファス水素化シリコン層３の着膜工程で発生したピ
ンホール５内に、アモルファス水素化シリコン層３より
も約５μｍ突出するように銅メツキ生成膜４（金属析出
柱）を形成するわけである。Thereafter, using an electrolytic plating apparatus that uses copper sulfate CuSO4.5H20 + distilled water as a plating solution and a platinum plate (PT) as an anode, the copper plating film 4 is formed into pinholes, that is, inside the photoelectric conversion film. It is generated on the exposed part of the chromium electrode. As shown in FIG. 9, this electrolytic plating processing apparatus consists of an anode 32 and a cathode 3 immersed in an electrolytic solution tank 31.
3. The glass substrate 1 is immersed in a plating solution, the chromium electrode 2 is connected to the cathode 33, a voltage of about 6 V is applied between this and the anode, and the plating is carried out in a dark place. Turn on electricity for 1 minute. In this way, as shown in FIG. 6, the copper plating produced film 4 is formed so as to protrude by about 5 μm from the amorphous silicon hydride layer 3 into the pinhole 5 generated in the process of depositing the amorphous silicon hydride layer 3. (Metal deposit pillars) are formed.
そして更に、充分、洗浄を行なった後、反応性スパッタ
リング法によって、室温にて第２電極としての酸化イン
ジウム錫（ｒＴｏ ） 膜５を第７図の如く、約７００
１堆積させる。Further, after thorough cleaning, an indium tin oxide (rTo) film 5 as a second electrode is deposited at room temperature using a reactive sputtering method with a thickness of about 700% as shown in FIG.
1 deposit.
最後に、希硝酸を主成分とするエツチング液に浸漬し、
銅メツキ生成膜をエツチング除去することにより、前記
ピンホール上の第２電極をも除去せしめられ、第８図の
如くなる。Finally, it is immersed in an etching solution containing dilute nitric acid as its main component.
By etching away the copper plating film, the second electrode above the pinhole is also removed, resulting in the result as shown in FIG.
このようにして、光電変換層内のピンホール発生部位で
は第２電極が除去されることにより、第２電極と第１電
極との間のショートの発生を防ぐことが可能となり、信
頼性の高い光電変換素子を得ることができる。In this way, the second electrode is removed at the pinhole occurrence site in the photoelectric conversion layer, making it possible to prevent short circuits between the second electrode and the first electrode, resulting in highly reliable A photoelectric conversion element can be obtained.
なお、実施例における銅メツキ生成膜は、フォトリソグ
ラフィー技術のリフトオフ法におけるレジストの働きと
同様の働きをするものであり、従って、メッキ生成膜と
しては、銅に限定されるものではなく、他の金属でも同
様の効果を呈することが可能である。The copper plating film in the examples has a similar function to that of a resist in the lift-off method of photolithography, and therefore, the plating film is not limited to copper, and may be other than copper. Similar effects can also be achieved with metals.
また、実施例においては、金属生成膜すなわち銅メツキ
生成膜のエツチングに用いるエツチング液としては、希
硝酸を用いたが、必ずしもこれに限定さり、るものでは
ない。この時は、第２電極および第１電極をエツチング
しないものかあるいはこれらに対するエツチング速度が
極めて小さいエツチング液を選ぶことが大切である。Furthermore, in the embodiment, dilute nitric acid was used as the etching solution for etching the metal-formed film, that is, the copper-plated film, but the present invention is not necessarily limited to this. At this time, it is important to select an etching solution that does not etch the second electrode and the first electrode or has an extremely low etching rate for these.
更に、電解メッキ工程においては、光電変換膜を絶縁性
に保つととすなわち、暗所で行なうことが重要である。Furthermore, in the electrolytic plating process, it is important to keep the photoelectric conversion film insulating, that is, to perform it in a dark place.
以上、説明してきたように、本発明の方法によれば、光
電変換膜の形成後に、電解メッキを行なうことにより、
絶縁性の光電変換膜中のピンホール部に、金属を析出芒
せ、咀に、この上に第２電極ヲ形成した後、エツチング
により、該金属をエツチング除去することにより、この
ピンホール上の第２電極をも除去し、ビンホール−ヒに
は第２′区極が存在しない状態にし、第２電極と第１電
極とのショートを防ぎ、信頼性の高い光′出、変換素子
を提供することが可能となる。As explained above, according to the method of the present invention, by performing electrolytic plating after forming the photoelectric conversion film,
A metal is deposited on the pinhole in the insulating photoelectric conversion film, a second electrode is formed thereon, and then the metal is removed by etching. The second electrode is also removed, and the second electrode is not present in the bin hole, thereby preventing short circuit between the second electrode and the first electrode, and providing a highly reliable light output and conversion element. becomes possible.
第１図は、サンドイッチ型光電変喚素子の等何回路を示
す図、
第２図は、理想的な光電変換素子の電流−電圧特性曲線
を示す図、
第３図は、光電変換層において、第１電極と第２電極と
が重々り合う部分にピンホールが発生、した場合の光電
変換素子の電流−電圧・特性的ａｆＦ示す図、
第４図乃至第８図は、本発明実施例の光電変換素子の製
造工程を示す図、第９図は、本発明実施例の光電変換素
子の製造工程で用いられる電解メッキ処理装置を示す図
である。
１・・・ガラス基板、２・・・クロム電極、３・・・ア
モルファス水素化７９３７層、４・・・銅メツキ生成膜
、５・・・酸化インジウム錫膜、３１・・・電解液槽、
３２・・・陽極、３３・・・陰極、■ｌ、ｒ３・・・光
照射時のＩ−Ｖ特性曲線、■２＋丁４・・・暗時のＴ−
Ｖ特性曲線。
第１図
第２図
第３図
第４□ 第８図
第５図
第６図
第７図
第９図FIG. 1 is a diagram showing a circuit of a sandwich-type photoelectric conversion device, FIG. 2 is a diagram showing a current-voltage characteristic curve of an ideal photoelectric conversion device, and FIG. 3 is a diagram showing a current-voltage characteristic curve of an ideal photoelectric conversion device. Figures 4 to 8 show the current-voltage characteristic afF of the photoelectric conversion element when a pinhole occurs in the portion where the first electrode and the second electrode overlap. FIG. 9, a diagram showing the manufacturing process of a photoelectric conversion element, is a diagram showing an electrolytic plating processing apparatus used in the manufacturing process of a photoelectric conversion element according to an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Glass substrate, 2... Chrome electrode, 3... Amorphous hydrogenated 7937 layer, 4... Copper plating film, 5... Indium tin oxide film, 31... Electrolyte tank,
32...Anode, 33...Cathode, ■l, r3...I-V characteristic curve during light irradiation, ■2+d4...T- in darkness
V characteristic curve. Figure 1 Figure 2 Figure 3 Figure 4 □ Figure 8 Figure 5 Figure 6 Figure 7 Figure 9
Claims (1)
ンドイッチ構造の薄膜光電変換素子を製造するにあたシ
、基板上に第１の電極を形成し、この上に絶縁性の光電
変換薄膜を堆積した後、電解メッキ法によって、前記光
電変換薄膜中の一ンホールに起因する第１の電極の露呈
部に金属生成膜を析出せしめる電解メッキ工程と、更に
、この上に第２の電極を形成した後、前記金属生成膜を
エツチング除去することにより、この金属生成膜上の第
２電極をも除去するためのエツチング工程とを含むこと
を特徴とする薄膜光電変換素子の製造方法。To manufacture a thin film photoelectric conversion element having a sandwich structure in which a photoelectric conversion thin film is sandwiched between first and second electrodes, the first electrode is formed on a substrate, and an insulating photoelectric conversion thin film is formed on the first electrode. After depositing, an electrolytic plating step is performed to deposit a metal-forming film on the exposed portion of the first electrode caused by a hole in the photoelectric conversion thin film, and a second electrode is further deposited on this. A method for manufacturing a thin-film photoelectric conversion element, comprising the step of etching away the metal-generated film after formation, thereby also removing the second electrode on the metal-generated film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58193633A JPS6085577A (en) | 1983-10-17 | 1983-10-17 | Manufacture of thin film photoelectric conversion element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58193633A JPS6085577A (en) | 1983-10-17 | 1983-10-17 | Manufacture of thin film photoelectric conversion element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6085577A true JPS6085577A (en) | 1985-05-15 |
| JPH0221663B2 JPH0221663B2 (en) | 1990-05-15 |
Family
ID=16311184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58193633A Granted JPS6085577A (en) | 1983-10-17 | 1983-10-17 | Manufacture of thin film photoelectric conversion element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6085577A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6147291A (en) * | 1984-08-14 | 1986-03-07 | Ricoh Co Ltd | Multicolor thermal recording method |
| EP0236936A2 (en) * | 1986-03-11 | 1987-09-16 | Siemens Aktiengesellschaft | Method for avoiding short-circuits during the production of electrical components, particularly for amorphous silicon solar cells |
| JPH02223924A (en) * | 1989-02-27 | 1990-09-06 | Hitachi Ltd | Production of display panel |
| US6132585A (en) * | 1992-07-01 | 2000-10-17 | Canon Kabushiki Kaisha | Semiconductor element and method and apparatus for fabricating the same |
-
1983
- 1983-10-17 JP JP58193633A patent/JPS6085577A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6147291A (en) * | 1984-08-14 | 1986-03-07 | Ricoh Co Ltd | Multicolor thermal recording method |
| EP0236936A2 (en) * | 1986-03-11 | 1987-09-16 | Siemens Aktiengesellschaft | Method for avoiding short-circuits during the production of electrical components, particularly for amorphous silicon solar cells |
| EP0236936A3 (en) * | 1986-03-11 | 1989-03-29 | Siemens Aktiengesellschaft | Method for avoiding short-circuits during the production of electrical components, particularly for amorphous silicon solar cells |
| JPH02223924A (en) * | 1989-02-27 | 1990-09-06 | Hitachi Ltd | Production of display panel |
| US6132585A (en) * | 1992-07-01 | 2000-10-17 | Canon Kabushiki Kaisha | Semiconductor element and method and apparatus for fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0221663B2 (en) | 1990-05-15 |
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