JPH0754499B2 - Address control circuit - Google Patents

Description

The present invention relates to an address control circuit that controls a plurality of memory addresses having different priorities to effectively use an address bus.

(Prior Art) In a microprocessor, in order to perform so-called prefetch control, a memory address for prefetching a machine language instruction, and a memory address for reading and writing a memory operand required when executing a machine language instruction A plurality of memory addresses having different priorities occupying the address buses such as the above are controlled to execute the machine language instruction execution processing.

FIG. 3 is a block diagram showing the configuration of an address control circuit for controlling a plurality of memory addresses having different priorities. The address control circuit shown in the figure uses a memory area specification method (segment method) that specifies each area for each instruction or data, and reads and writes the prefetch memory address of the machine language instruction and the memory operand in the machine language instruction. It controls the memory address to be performed.

The address control circuit includes a first effective address generation circuit 1 that generates an effective address for reading and writing a memory operand of a machine language instruction, and a second effective address generation circuit 3 that generates an effective address for prefetching a machine language instruction.
And a selection circuit 5 for instructing the first effective address generation circuit 1 and the second effective address generation circuit 3 to generate an effective address.
And a switching circuit 7 for switching the effective addresses generated by the first effective address generating circuit 1 and the second effective address generating circuit 3.
And a switching control circuit 9 for controlling the switching operation of the switching circuit 7, and an effective address register 11 for temporarily holding an effective address generated by the first effective address generating circuit 1 or the second effective address generating circuit 3. Have

Further, a segment base register group 13 in which information necessary for calculating a physical address corresponding to an effective address is stored, a switching circuit 15 for switching information output from this segment base register group 13, and this switching circuit.
A switching control circuit 17 for controlling the switching operation of 15 and the effective address and switching circuit stored in the effective address register 11.
The information output from the segment base register group 13 selected by 15 is added to calculate the physical address, and the physical adder 19 temporarily stores the physical address calculated by this base adder 19. And a register 21.

Furthermore, a monitoring circuit for monitoring the usage status of the address bus
23 and a memory 25 in which machine language instructions and data are stored
And a start circuit controlled by the monitoring circuit 23 to start access to the memory 25 with the physical address held in the physical address register 21 when the address bus is empty
Have 27 and.

Next, in such a configuration, a case where a memory operand read request and a machine language instruction prefetch request occur simultaneously in a machine language instruction will be described. Here, of these requests, the read request of the memory operand is assumed to have a higher priority of execution processing than the prefetch request of the machine language instruction.

Therefore, the first effective address generation circuit 1 is selected by the selection circuit 5
The effective address of the memory operand requested to be read by the effective address register is switched via the switching circuit 7 switched to the first effective address generating circuit 1 side.
Transferred to 11 and held.

The effective address held in the effective address register 11 is
Transmitted from the segment base register selected by the switching circuit 15 from the segment base register group 13,
The information corresponding to the effective address held in the effective address register 11 is added by the base adder 19 to calculate the physical address corresponding to the effective address. The calculated physical address is transferred to and held in the physical address register 21.

Then, when the monitoring circuit 23 confirms that the address bus is empty, the monitoring circuit 23 instructs the start circuit 27 to access the memory 25 with the physical address held in the physical address register 21, A read request for the memory overlay is executed.

In this way, the read request of the memory operand is executed. However, the prefetch request of the machine language instruction that occurs at the same time as the read request of the memory operand may require the read and write requests of the memory operand again. Therefore, it is not performed until the access to the memory 25 is completed. After the memory 25 has been accessed, if there is no request to read or write the memory operand, an effective address for making a prefetch request for a machine language instruction is generated from the second effective address generation circuit 3 and The same process as the read request of the memory operand is performed, and the prefetch request of the machine language instruction is executed.

(Problems to be Solved by the Invention) As described above, in the above-mentioned address control circuit, when memory accesses with different priorities occur simultaneously, after the memory accesses with high priorities are completed, An effective address for accessing a memory with a low priority is generated, this effective address is converted into a physical address, and a memory with a low priority is accessed.

Therefore, even if the address bus is empty after the high-priority memory access is completed, it takes time to convert the effective address to the physical address. There is a problem that a low memory access cannot be performed and an execution process accompanied by the memory access cannot be performed at high speed.

Therefore, the present invention has been made in view of the above, and when the memory access with a plurality of different priorities is performed, the use efficiency of the address bus is improved, and the execution processing accompanied by the memory access is speeded up. An object is to provide an address control circuit that can be implemented.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention relates to an address generating means for generating a plurality of effective addresses having different priorities for occupying an address bus, and the address. A conversion unit that converts the effective addresses sequentially generated by the generation unit into physical addresses in the generation order, a storage unit that stores a plurality of physical addresses sequentially obtained by the conversion unit for each priority, and a conversion unit. Transfer means for sequentially transferring the obtained physical addresses to the storage means, and when the use state of the address bus is monitored and the address bus becomes empty, the priority order is selected from the plurality of physical addresses stored in the storage means. And an address supply means for selecting a physical address and supplying it to the memory.

(Operation) In the address control circuit according to the present invention, when a plurality of memory accesses having different priorities are performed, the physical address for each memory access is calculated regardless of the priorities, and each physical address is assigned to each priority. Each of them is stored and held separately, and the memory is accessed sequentially from the highest priority.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an address control circuit according to an embodiment of the present invention. Similar to the address control circuit shown in FIG. 3, the address control circuit shown in the figure has a memory address for prefetching a machine language instruction, a memory operand read in the machine language instruction, and a memory operand read for writing. It controls the memory address for writing. Further, the address control circuit of this embodiment calculates in advance the respective physical addresses for accessing the respective memories having different priorities, stores and holds the respective physical addresses separately, and makes the address bus empty. At a certain time, the memory access is immediately performed by the physical address stored and held.

In FIG. 1, the same reference numerals as those in FIG. 3 have the same functions, and the description thereof will be omitted. Therefore, the process of generating an effective address and calculating the physical address corresponding to this effective address is the same as that of the address control circuit shown in FIG. In FIG. 1, the storage holding unit 27
Stores and holds respective physical addresses for performing respective memory accesses having different priorities, determines the use state of the address bus and the priority order of memory access, and accesses the memory 25 with the stored and held physical addresses. To do. The storage / holding unit 27 includes switching circuits 29, 3
7, a switching control circuit 31, a first physical address register 33, a second physical address register 35, a switching circuit 37, and an instruction circuit 39.

The switching circuit 29 performs a physical address (hereinafter referred to as "first physical address") for making a read / write request of a memory operand in the machine language instruction calculated by the base adder 19 or prefetching a machine language instruction. A physical address (hereinafter, referred to as “second physical address”) for supplying the first physical address to the first physical address register 33, and the second physical address to the second physical address register.
Supply to 35.

The switching control circuit 31 controls the switching operation of the switching circuit 29.

The first physical address register 33 receives the first physical address from the base adder 19 via the switching circuit 29, and temporarily holds this first physical address. The second physical address register 35 receives the second physical address from the base adder 19 via the switching circuit 29, and temporarily holds this second physical address.

The switching circuit 37 switches between the first physical address register 33 and the second physical address register 35, and supplies the respective physical addresses held in the respective address registers to the memory 25.

The instruction circuit 39 monitors the use state of the address bus and gives an instruction to the switching circuit 37 to access the memory 25 at a memory address having a high priority.

As described above, this embodiment is constructed, and the operation of this embodiment will be described below with reference to FIG.

FIG. 2 is a timing chart of the address control circuit shown in FIG. ₁ , in which the read or write processing of the memory operand in the machine language instruction is α ₁ , and the read or write processing of the next memory operand is α ₁ . _{2. It} is assumed that the prefetching process of the machine language instruction is β, that it takes 1 clock to convert the effective address to the physical address, and 2 clocks to access the memory by the physical address.
The memory access associated with the reading and writing of the memory operand in the machine language instruction has a higher priority than the memory access associated with the prefetching of the machine language instruction.

Here, reading of the memory operand in the machine language instruction α ₁
The case where the prefetching β of the machine language instruction and the machine language instruction occur simultaneously will be described.

When the memory operand read α ₁ in the machine language instruction and the machine language instruction prefetch β occur simultaneously, the effective address of the memory operand read α ₁ becomes
It is supplied from the effective address generation circuit 1 to the effective address register 11 via the switching circuit 7. The segment base register group 13 corresponding to the effective address supplied to the effective address register 11 at the first clock
The information given from the segment base register selected from among the above through the switching circuit 15 is added by the base adder 19 to be converted into the first physical address.

This first physical address is transferred to the first physical address register 33 via the switching circuit 29 at the second clock, and the first physical address is transferred to the first physical address register 33.
It is stored and held in the physical address register 33. Further, the prefetching β of the machine language instruction supplied from the second effective address register 3 to the effective address register 11 via the switching circuit 7
Effective address is converted into a second physical address by the second clock.

The first physical address stored and held in the first physical address register 33 is instructed by the instruction circuit 39 to the switching circuit 37 when it determines that the address bus is empty, and then switches to the switching circuit 37 at the third and fourth clocks. Is supplied to the memory 25 via. As a result, the memory 25 is accessed at the first physical address and the memory operand read α ₁ is performed.

Also, the second physical address converted by the second clock is
It is transferred to the second physical address register 35 at the third clock and stored and held. Further, since the prefetching β of the machine language instruction is followed by the reading α ₂ of the memory operand, the effective address of the reading α ₂ of this memory operand is converted into the first physical address at the third clock, and the first physical address is converted. Are transferred to the first physical address register 33 at the fourth clock and are stored and held.

Here, since reading and writing of the operand in the machine language instruction has a higher priority than the prefetch of the machine language instruction, the first physical address stored and held in the first physical address register 33 is the fifth physical address and the fifth physical address. It is supplied to the memory 25 in 6 clocks and memory access is performed. Then, after the memory access at the first physical address is completed, the second
The second physical address stored and held in the physical address register 35 is supplied to the memory 25 at the seventh and eighth clocks for memory access and prefetching β of the machine language instruction.
Is performed.

In this way, since the memory access with the highest priority is purely executed, the physical address of the prefetch β of the machine language instruction is calculated before the memory access of the reading α ₂ of the memory operand is performed. It is stored and held in the second physical address register 35. As a result, if the memory access for reading the memory operand α ₂ is completed and the address bus is empty, it is possible to immediately access the memory at the second physical address, and the memory access for reading the memory operand α ₂ is completed. Shortly after
A memory access for prefetching β of a machine language instruction can be executed.

In this embodiment, there are two types of memory accesses having different priorities, but the present invention is not limited to this, and when there are two or more types of memory accesses having different priorities, the types of memory access are different. It suffices to prepare a register for storing and holding physical addresses for the same memory access.

[Effects of the Invention] As described above, according to the present invention, physical addresses for memory accesses having different priorities are calculated regardless of the priorities, and the physical addresses are stored and held separately for each priority. Since the memory access is performed according to the priority order, the memory access with the low priority order can be performed immediately after the memory access with the high priority order is completed. As a result, the use efficiency of the address bus is improved, and the execution process involving memory access can be performed at high speed.

[Brief description of drawings]

1 is a block diagram showing the configuration of an address control circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of FIG. 1, and FIG. 3 is a block diagram showing a conventional configuration of the address control circuit. . (Explanation of symbols representing main parts of the figure) 1 ... First effective address generating circuit 3 ... Second effective address generating circuit 11 ... Effective address register 19 ... Base adder 25 ... Memory 29 ... Switching Circuit 31 …… Switching control circuit 33 …… First physical address register 35 …… Second physical address register 37 …… Switching circuit 39 …… Instructing circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-48-91943 (JP, A) JP-A-49-131649 (JP, A) JP-A-50-128948 (JP, A)

Claims (1)

[Claims] 1. An address generating means for generating a plurality of effective addresses occupying an address bus and having different priorities, and a converting means for converting the effective addresses sequentially generated by the address generating means into physical addresses in the order of generation. Storage means for respectively storing a plurality of physical addresses sequentially obtained by the conversion means for each priority order, transfer means for transferring the physical addresses sequentially obtained by the conversion means to the storage means, and use state of the address bus And an address supply means for selecting a physical address from a plurality of physical addresses stored in the storage means in accordance with the priority and supplying it to the memory when the address bus becomes free. Address control circuit.