JPS6382537A - Address control circuit - Google Patents

Abstract

PURPOSE:To enhance the using efficiency of an address bus and to attain a high speed execution processing with a memory access by making access to a memory according to a priority to the memory of a different priority. CONSTITUTION:When the reading of a memory operand in a mechanical language instruction and the prefetch of the mechanical language instruction are simultaneously generated, the execution address for reading the memory operand is supplied to an execution address register 11 through a switching circuit 7 from the first execution address generating circuit 1 according to the priority. The execution address supplied to the execution address register 11 is added to information applied through a switching circuit 15 from a segment base register selected from segment base register groups 13 corresponding to this execution address by the first clock by a base adder 19 and transformed to the first physical address.

Description

DETAILED DESCRIPTION OF THE INVENTION OBJECTS OF THE INVENTION (Field of Industrial Application) The present invention relates to an address control circuit that controls a plurality of memory addresses with different priorities and effectively uses an address bus.

(Prior Art) In a microprocessor, in order to perform so-called preemption control, memory addresses for prefetching machine commands, reading of memory operands required when executing machine instructions, etc. Execution processing of machine language instructions is performed by controlling a plurality of memory addresses with different priorities that occupy the address bus of the memory address cap associated with writing.

FIG. 3 is a block diagram showing 114 configurations of an address control circuit that controls a plurality of memory addresses having different destinations lα. The address control circuit shown in the figure is a memory block that specifies each area for each instruction and data.
J3 in the Alff1 specification method (segment 1 to method), reads the memory address for prefetching of a machine language instruction and the memory operand in the machine language instruction.

It sets the memory address for writing to It, II 0[1.

This address control circuit consists of a first effective address generation circuit 1 that generates an effective address for reading and writing memory operands of machine n instructions, and a second effective address generation circuit 1 that generates an effective address for prefetching machine language instructions. circuit 3, and a selection circuit 5 that instructs the first effective address generation circuit 1 and the second effective address generation circuit 3 to generate an effective address.
and a switching circuit 7 for switching the effective addresses generated by the first effective address generation circuit 1 and the second effective address generation circuit 3.
, a switching control circuit 9 that controls the switching operation of the switching circuit 7, and an effective address register 11 that temporarily holds the effective address generated by the first effective address generation circuit 1 or the second effective address generation circuit 3. have.

Additionally, there is a segment base register group 13 in which information necessary for calculating the physical address corresponding to the effective address is stored, and this segment base register group 13.
a switching circuit 15 that switches the information output from the switching circuit 15; a switching control circuit 17 that controls the switching operation of the switching circuit 15;
a base adder 19 that adds the effective address stored in the effective address register 11 and information output from the segment base register group 13 selected by the switching circuit 15 to produce a physical address; The physical address register 21 temporarily holds the physical address calculated in step 19.

Furthermore, a monitoring circuit 23 that monitors the use state of the address bus, a memory 25 in which machine language instructions and data are stored, and a physical address register 25 controlled by the monitoring circuit 23, when the address bus is in an empty state. The start circuit 27 starts accessing the memory 25 using the physical address held in the memory 25.

Next, a case will be described in which, in such a configuration, a memory operand read request and a machine language instruction prefetch request occur simultaneously in a machine language instruction.

Here, it is assumed that among these requests, a memory operand read request has a higher execution processing priority than a machine language instruction prefetch request.

Therefore, the first effective address generation circuit 1 is the selection circuit 5.
The effective address of the memory operand selected by and requested to read is transferred to the effective address register 11 and held there via the switching circuit 7 which is switched to the first effective address generation circuit 1 side.

The effective address held in the effective address register 11 is selected from the segment base register group 13 by the switching circuit 1.
5 is sent from the segment base register selected by 5, and is added by the base adder 19 to the information corresponding to the effective address held in the effective address register 11.
A physical address corresponding to the effective address is revealed. This physical address is written to physical address register 2.
1 and held.

Then, when the address bus is confirmed by the monitoring circuit 23 to be in an empty state, the monitoring circuit 23
, the memory 25 is accessed using the physical address held in the physical address register 21, and a memory operand read request is executed.

In this way, a memory operand read request is executed, but a machine language instruction prefetch request that occurs at the same time as a memory operand read request may cause a memory operand read or write request to be requested again. Therefore, it will not be performed until the access to the memory 25 is completed. Then, after the access to the memory 25 is completed, if there is no memory operand read or old loading request, the second effective address generation circuit 3 generates an effective address for making a prefetch request for a machine language instruction. Thereafter, processing similar to that for a memory operand read request is performed, and a machine language instruction prefetch request is executed.

(Problems to be Solved by the Invention) As explained above, in the address control circuit described above, when memory accesses with different priorities occur simultaneously, after the memory access with a higher priority is completed, (Support) An effective address for performing a memory access with a low priority is generated, this effective address is converted into a physical address, and a memory access with a low priority is performed.

Therefore, even if the address bus is free after a high-priority memory access is completed, it takes time to convert an effective address to a physical address, so the high-priority memory access is immediately There is a problem in that low memory access cannot be performed and execution processing that involves memory access cannot be performed at high speed.

The present invention has been made in view of the above problems, and it is an object of the present invention to improve the efficiency of address bus use when performing memory accesses with multiple different priorities, and to speed up execution processing that involves memory accesses. The purpose of the present invention is to provide an address control circuit that can perform the following operations.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides effective address generation means for generating a plurality of effective addresses with different priorities to occupy an address bus, and A conversion means converts an address into a physical address corresponding to this effective address, a storage holding means stores and holds physical addresses separately for each priority, and selects a physical address for each priority so that each physical address has priority. A transfer means for transferring the data to the storage and holding means to be stored and held separately in the order fσ, and a physical transfer means for monitoring the usage status of the address bus and when the address bus becomes free, the physical data is stored in the storage and holding means according to the priority order. and an access means for selecting an address and accessing the memory.

(Function) In the address control circuit of the present invention, when performing multiple memory accesses with different priorities, the physical address for each memory access is calculated regardless of the priority, and the physical address is calculated for each priority. They are stored and maintained separately, and memory accesses are performed sequentially starting with the one with the highest priority.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an address control circuit according to an embodiment of the present invention. Similar to the address control circuit shown in FIG. 3, the address control circuit shown in FIG. This controls the memory address to which data is written. Further, the address control circuit of this embodiment selects in advance each physical address for each memory access with different priorities, stores and holds each physical address separately, and maintains the address bus in an empty state. At times, memory accesses are performed using physical addresses that are stored and held immediately.

Components in FIG. 1 with the same symbols as those in FIG. 3 have the same functions, and a description of "A" will be omitted.

Therefore, the process in which an effective address is generated and a physical address corresponding to this effective address is calculated is similar to that of the address control circuit shown in FIG. 3. In FIG. 1, the storage/holding unit 27 stores and holds physical addresses for performing memory accesses with different priorities, and determines the use status of the address bus and the priority of memory access, and stores/holds them. The device 25 is accessed using the specified physical address. This storage holding section 27 includes switching circuits 29 and 37, a switching control circuit 31, a first
It is composed of a physical address register 33, a second physical address register 35, a switching circuit 37, and an instruction circuit 39.

The two switching circuits read the memory operand in the machine language instruction calculated by the base adder 19.

A physical address for making a write request (hereinafter referred to as the "first physical address") or a physical address for prefetching a machine language instruction (hereinafter referred to as the "second physical address")
, and supplies the first physical address to the first physical address register 33 and the second physical address to the second physical address register 35.

The switching control circuit 31 controls switching operations of the two switching circuits.

The first physical address register 33 receives a first physical address from the base adder 19 via the switching circuit 29 and temporarily holds this first physical address. The second physical address register 35 receives a second physical address from the base adder 19 via the switching circuit 29 and temporarily holds this second physical address.

The switching circuit 37 switches between the first physical address register 33 and the second physical address register 35 and supplies each physical address held in each address register to the memory 25.

The instruction circuit 1839 monitors the usage status of the address bus and also assigns the memory 25 at a memory address with a high priority.
This is to give an instruction to the switching circuit 37 to access the .

This embodiment is constructed as described above, and the operation of this embodiment will now be described with reference to FIG. 2.

FIG. 2 is a timing chart of the address control circuit shown in FIG. 1. In the figure, the read or write process of the memory operand in the machine 5n instruction is performed by α1, and the read or write process of the next memory operand is performed by α2.
Assume that the prefetching process of a machine language instruction is β, that one clock is required to convert an effective address to a physical address, and two clocks are required for memory access using a physical address.

Also, reading memory operands in machine language instructions.

It is assumed that memory reaccess associated with input/output has a higher priority than memory access associated with prefetching of semantic language instructions.

Here, reading αt of memory operand in machine language instruction
A case will be explained in which a prefetch β of a machine language instruction and a prefetch β of a machine language instruction occur simultaneously.

tiv = If the memory operand read α1 in the instruction and the machine language instruction prefetch β occur simultaneously, the effective address of the memory operand read α1 will be
The signal is supplied from the first effective address generation circuit 1 to the effective address register 11 via the switching circuit 7. The effective address supplied to this effective address register 11 is based on the information given via the switching circuit 15 from a segment base register selected from the segment base register group 13 corresponding to this effective address at the first clock. The address is added by an adder 19 and converted into a first physical address.

This first physical address is transferred to the first physical address register 33 via two switching circuits using the second clock.
It is stored and held in the first physical address register 33. Further, the real 'A+ address of the prefetch β of the machine language instruction supplied from the second effective address register 3 to the effective address register 11 via the switching circuit 7 is converted into a second physical address by the second clock.

When the instruction circuit 39 determines that the address bus is empty and instructs the switching circuit 37, the first physical address stored and held in the first physical address register 33 is transferred to the third
and is supplied to the memory 25 via the switching circuit 37 at the fourth clock. This allows memory 2 to be used at the first physical address.
5 is accessed, and reading α1 of the memory operand is performed.

Also, the second physical address converted by the second clock is
At the third clock, it is transferred to the second physical address register 35 and stored and held. Furthermore, since the memory operand read α2 follows the prefetch β of the number domain instruction, the effective address of this memory operand read α2 is converted to the first physical address by the third clock, and this first physical address is , the first physical address register 3 at the fourth clock.
3 and stored and held.

Here, ■ Read the operand in the machine command.

Since prefetching has a higher priority than prefetching machine language instructions, the first physical address stored and held in the first physical address register 33 is supplied to the memory 25 at the fifth and sixth clocks, and is stored in the memory 25 at the fifth and sixth clocks. Access is made. After the memory access at this first physical address is completed, the second physical address stored and held in the second physical address register 35 is supplied to the memory 25 at the seventh and eighth clocks, and the memory access is completed. The prefetch β of the global command is performed.

In this way, memory accesses are executed in order of priority, but before the memory access for reading α2 of the memory operand is performed, the physical address of the prefetch β of the machine language instruction is calculated and the second It is stored and held in the physical address register 35. As a result, if the memory access for reading the memory operand α2 is completed and the address bus is in an empty state, it becomes possible to immediately access the memory at the second physical address, and immediately after the memory access for reading the memory operand α2 is completed. ni, Rb't 2 fi? Memory access of prefetch β of the J instruction can be executed.

Note that in this embodiment, there are two types of memory accesses with different priority orders, but the invention is not limited to this, and if there are two or more types of memory accesses with different priority orders, the It is the same as the type (all you need to do is prepare a register to store and hold the physical address for pre-memory access).

[Effects of the Invention] As explained below, according to the present invention, physical addresses for performing memory accesses with different entry orders are calculated regardless of the entry order, and storage is performed separately for each priority order. Since memory accesses are performed according to priority order, memory accesses with lower priorities can be performed immediately after memory accesses with higher priorities are completed. This improves address bus usage efficiency and allows execution processing involving memory access to be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a configuration of an address control circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram of FIG. 1, and FIG. 3 is a block diagram showing a conventional configuration of an address control circuit. It is a diagram. (Explanation of symbols representing main parts in the diagram) 1... First effective address generation circuit 3... Second effective address generation circuit 11... One effective address register... Base adder 25... ...Memory 29...Switching circuit 31...Switching control circuit 33...First physical address register 35...Second physical address register 37...Three switching circuits...Instruction circuit

Claims (1)

[Claims] An effective address generation means that generates multiple effective addresses with different priorities to occupy the address bus, a conversion means that converts the effective address into a physical address corresponding to this effective address, and a physical address that is stored separately for each priority. a storage/holding means for storing, a transfer means for selecting physical addresses for each priority and transferring the physical addresses to the storage/holding means to be stored and held separately for each priority; 1. An address control circuit comprising access means for monitoring and accessing a memory by selecting a physical address stored in the storage holding means in accordance with priority when the address bus becomes vacant.