JPH0752824B2 - Integrated circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to an integrated circuit having a plurality of pulse width modulation circuits.

[Prior Art] In a conventional integrated circuit having a plurality of pulse width modulation circuits, as shown in FIG. 3, the contents of the data buffers 12 and 13 in each pulse width modulation circuit and the frequency division counters 11 and 14 are divided. The coincidence with the count value is detected by the coincidence circuits 15 and 16, and the coincidence signal is sent to the 1-bit latches 17 and 18. In this case, in order to detect the match between the contents of the data buffers 12 and 13 and the count values of the frequency division counters 11 and 14,
Frequency division counters 11 and 14 and coincidence circuits 15 and 16 are prepared for 12 and 13 respectively.

[Problems to be Solved by the Invention] In the above-described conventional integrated circuit, one division counter and one coincidence circuit are required for one data buffer, so that the number of pulse width modulation circuits is equal to the number of pulse width modulation circuits. Requires a round counter and matching circuit. Therefore, there is a problem that the total number of circuit elements increases, and as a result, the chip area of the integrated circuit increases.

The present invention has been made in view of the above circumstances, and provides an integrated circuit that can have a plurality of pulse width modulation circuits while avoiding an increase in the number of circuit elements and can reduce the chip area. With the goal.

[Means for Solving the Problems] The integrated circuit according to the present invention shares a combination of one frequency division counter and one coincidence circuit for a plurality of pulse width modulation circuits and switches the pulse width modulation circuits. It is characterized by having a switching circuit.

[Operation] In the present invention, the contents of the pulse width modulation circuit selected by the switching circuit and the contents of the frequency division counter are compared by the coincidence circuit. Then, when the switching circuit is switched, the contents of another pulse width modulation circuit and the contents of the frequency division counter are compared, so that one set of frequency division counter and coincidence circuit can be shared for a plurality of pulse width modulation circuits. it can.

If each of the plurality of pulse width modulation circuits has a data buffer composed of a plurality of bits and a 1-bit latch that outputs a signal having a pulse width corresponding to the content of the data buffer, the 1-bit The output pulse width is controlled by resetting the latch of (1) based on the comparison result of the contents of the data buffer and a part of the contents of the frequency division counter.

[Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, 1 is a frequency division counter, the least significant bit (LSB) of which
By controlling the switching circuits 7 and 8 in accordance with the logic output a of the
Select one of each. Here, the switching circuit 7 is composed of tristate buffers 7A to 7F and an inverter 7G, and the switching circuit 8 is composed of AND gates 8A and 8B and an inverter 8C. The upper bits b to d of the frequency division counter 1 are compared with the output of the data buffer 2 or 3 selected by the switching circuit 7 in the coincidence circuit 4. This matching circuit 4 is EXNO
It is composed of R gates 4A to 4C, a NAND gate 4D and an inverter 4E.

If a data match is found as a result of this comparison,
The selected 1-bit latch 5 or 6 is reset by the output h of the inverter 4E. On the other hand, when all of the high-order bits b to d of the frequency division counter 1 are "L", the 1-bit latches 5 and 6 are unconditionally output by the output "i" of all "L" detection circuits 9 composed of NOR gates. Set. As a result, the pulse width modulation signals whose duty ratios are designated in the data buffer 2.3 are obtained as the outputs A and B of the 1-bit latches 5 and 6, respectively.

FIG. 2 shows that data buffers 2 and 3 have "110" and "10" respectively.
A to i and 1 in FIG. 1 when 1 "is stored
The timing waveforms of the A and B signals are shown.

As shown in FIG. 1, the frequency division counter 1 outputs the pulses a to b shown in FIG. Here, the data buffer switching circuit 7 selects the contents of the data buffer 2 when the output a of the least significant bit (LSB) of the frequency division counter 1 is "H", and the contents of the data buffer 3 when the output a is "L". Is selected.
The data selected by the switching circuit 7 is compared with the output signal b, c, d of the upper 3 bits of the frequency dividing counter 1 in the coincidence circuit 4. When the high-order bits b to d of the frequency division counter 1 and each bit of the selected data buffer match,
The output h of the coincidence circuit 4 becomes "H". Further, the 1-bit latch switching circuit 8 outputs a to select a data buffer.
Is "H", 1-bit latch 6 is selected and output a is "L"
Then, the 1-bit latch 5 is selected. Therefore, the 1-bit latch 6 is reset when the signal a is "H" and the signal h is "H", and the 1-bit latch 5 is reset when the signal a is "L" and the signal h is "H". To be done. Further, when the output signals b, c, d of the upper 3 bits of the frequency division counter 1 are all "L", all the outputs "L" are detected by the detection circuit 9.
When the output i of the detection circuit 9 becomes "H", the 1-bit latch 5 or 6 is unconditionally set by "L" or "H" of the signal a, respectively. As a result, the outputs A and B of the 1-bit latches 5 and 6 become pulse width modulation signals corresponding to the values designated by the data buffers 2 and 3.

As described above, in the present invention, the switching circuit switches the plurality of pulse width modulation circuits. In this case, the output signal of the least significant bit of the frequency division counter 1 can be used as a control signal for selecting one of the plurality of data buffers. Therefore, since the plurality of data buffers share the combination of one frequency dividing counter and one matching circuit, the total number of circuit elements can be reduced. Therefore, the chip area of the integrated circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing a timing waveform of each signal in FIG. 1 when “110” and “101” are stored in the data buffers 2 and 3, respectively, and FIG. 3 is a circuit diagram showing a conventional integrated circuit. . 1; division counter, 2, 3; data buffer, 4; match circuit, 5,
6; 1-bit latch, 7; data buffer switching circuit, 8; 1-bit latch switching circuit, 9; detection circuit, a, b, c, d; frequency division counter output (of which a is a pulse width modulation circuit switching signal), e, f, g: Matching signal of each bit of the frequency dividing counter buffer, h: Matching signal of frequency dividing counter and data buffer, i: All "L" detection signals of frequency dividing counter output, A, B: Pulse width modulation signal

Claims (3)

[Claims] 1. A counter circuit, a matching circuit having one input connected to the output of the counter circuit, and a first output to be selectively connected to another input of the matching circuit.
And a second data buffer, and one of the first and second data buffers connected between the outputs of the first and second data buffers and the other input of the matching circuit, in accordance with a control signal. A switching circuit for connecting the output of the same to the other input of the matching circuit. 2. The counter circuit outputs the lower bits as the control signal to the switching circuit, outputs the upper bits excluding the lower bits to the matching circuit, and the matching circuit outputs the first data buffer. 2. The integrated circuit according to claim 1, wherein a match is detected by selectively comparing the upper bit or the upper bit or the second data buffer with the upper bit. 3. A first and second output buffer connected to the output of the matching circuit, wherein the first and second output buffers select the output of the matching circuit according to the control signal. The integrated circuit according to claim 1, wherein the integrated circuit holds and outputs the data.