JP3119502B2 - Pulse generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generation circuit, and more particularly to a pulse generation circuit using a read-only memory.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional pulse generating circuit has a counting circuit 2 composed of a binary counter, a read-only memory (which outputs an output from the counting circuit 2 as address data and outputs a pulse). ROM) 4.

[0003] counting circuit 2 counts the clock pulses P _in, and outputs the ROM4 the count result as the address data D. ROM4 is pre pulse generation information stored in the, ROM4 is generates and outputs a pulse output P _{ou t} on the basis of the address data D and the pulse generation information.

[0004]

In the conventional pulse generation circuit, the access time of the ROM 4 is required for pulse generation, and the frequency of the pulse output P _out is limited by the access time of the ROM 4, so that the frequency of the pulse output is There was a problem that it could not be higher.

An object of the present invention is to realize a high-frequency circuit which is not limited by the access time of a ROM.

[0006]

According to the first aspect of the present invention,
Counts the (i) clock pulse, double the result of the counting
Output as address data consisting of several bits
Counting circuit as a binary counter and (b) address
Pulse generation information corresponding to the data is stored.
A read-only memory that inputs address data excluding the least significant bit from several circuits and outputs a corresponding pulse; and (c) removes the least significant bit output from the counting circuit.
Input address data, and
A delay circuit that delays and outputs the delay
Pulse generation information corresponding to the
Input the address data output from the delay circuit.
Te, and another read-only memory which outputs a corresponding pulse, and a switching circuit for switching <br/> alternately connect two read-only memory mentioned above by the output of the least significant bit (e) the address data pulse In the generation circuit
You.

That is, according to the first aspect of the present invention, the binder
Exclude the least significant bit from the counting circuit as recounter
Address data to one read-only memory.
Input the address data to the delay circuit and
After delaying by one clock pulse of the lock pulse, another read
Supply to the read-only memory. Each read-only
The memory stores the pulse generation information corresponding to the address data.
It is remembered. Switching the pulse output from now on
Input to the circuit. The switching circuit is used for address data.
Two readings described above by outputting the least significant bit
The connection of the dedicated memory is alternately switched. The counting circuit is
Since it is a null counter, the address excluding the least significant bit
The switching circuit alternates between pulse outputs based on data.
Pulse output with double frequency.
Will be done.

[0008]

An embodiment of the present invention will be described below with reference to the drawings.

[0009] Figure 1 is a block diagram of the present embodiment, the counting circuit 10 configured in FIG binary counter counts the clock pulses P _in, the least significant of the address
The data is output to the read-only memory (ROM) 12 and the ROM 14 as address data D excluding bits. RO
The M12 and the ROM 14 are arranged in parallel with the
M14 is connected to the counting circuit 10 via the delay circuit 16. The ROM 12 and the ROM 14 are connected to a switching circuit 18. The switching circuit 18 is a counting circuit 1
Connected to 0.

[0010] The ROM 12, are stored in advance the pulse generation information, ROM 12 outputs to the switching circuit 18 generates a pulse P _a on the basis of the address data D and the pulse generation information. Address data D to the delay circuit 16 is ROM 14, 1 clock equivalent of clock pulses P _in than at the input to ROM 12, is inputted with a delay. ROM 14 also, also have pre pulse generation information is stored, ROM 14 outputs to the switching circuit 18 generates a pulse P _b on the basis of the address data D and the pulse generation information. The switching circuit 18 is a counting circuit 10
, And switches the connection of the ROM 12 or the ROM 14 as appropriate.

FIG. 2 illustrates the operation of each component of the present embodiment.
FIG.₁Is the clock pulse P_inof
Indicates the period, P_TwoIs the address data output to the ROM 12.
Indicates the decimal display of data D,_ThreeIs R from the delay circuit 16
Decimal display of address data D output to OM14
Is shown. P_FourIs the pulse P_aIs the address of ROM12
And corresponding to_FiveIs the pulse P_bOf ROM14
Are shown in correspondence with the P_FourAnd P_FiveDiagonal at
The area indicated by the line is the access of ROM12 or ROM14.
Indicates the time period during which the output becomes unstable depending on the time.
You. Also, P₆From the counting circuit 10 to the switching circuit 18
Control signal C, P₇Is the pulse output P _outThe ROM
12 and the address of the ROM 14.
You. P₆Is P ₁Must be synchronized with the control signal
C is the output of the least significant 1 bit of the address of the counting circuit 10
It is performed by doing.

In the present embodiment having the above-counted by the clock pulses P _in the counting circuit 10 shown in P _1, is output to the ROM12 as the address data D.
The address data D is output to the ROM 14 via the delay circuit 16 with a delay for one clock pulse P _in as shown at P ₃ . In ROM12 pulse P _a shown in P ₄ via its access time is generated and outputted to the switching circuit 18. ROM1
4 even pulse P _b shown in P ₅ via its access time
Is generated and output to the switching circuit 18, but the ROM
14, the address data D is input with a delay.
Pulse P _b is for one clock equivalent pulse P _a clock pulse P _in than as shown in P ₄ and P _5, is generated as a pulse delayed.

A control signal C for activating the switching circuit 18
Is P₆P as shown₁Clock pulse P shown in_inSame as
Expected, pulse P_bSwitching circuit 18 in accordance with the generation of
Switch to ROM 14 side. Access tie of ROM14
The pulse P_bIs not generated, but the pulse
P_bAnd a pulse P whose period has progressed for one clock equivalent _a
Has been generated, and at that time, the switching circuit 18
Pulse P_aWill be output
You. Similarly, a pulse is generated during the access time of the ROM 12.
P_aIs not generated, but the pulse P_aAnd one clock phase
Pulse P whose period is delayed for the time being_bHas been generated,
At that time, the switching circuit 18 is closed to the ROM 14 side.
With pulse P_bIs output. Therefore over time
From the switching circuit 18₇The pulse output P shown in_out
Is output.

As described above, according to the present embodiment, the frequency of the pulse output P _out can be reduced to half that of the conventional pulse generation circuit.

[0015]

The present invention as described above, according to the present invention is, in the two ROM pulse generating circuit, one of the ROM is connected to the counting circuit via a delay circuit, the switching circuit causes coupled to circuit switched each ROM Is operated by the address data of the counting circuit, so that the frequency of the pulse output can be increased without being limited by the access time of the ROM.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a pulse generation circuit according to the present invention.

FIG. 2 is an explanatory diagram for explaining the operation of the components in the embodiment of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of an example of a conventional pulse generation circuit.

[Explanation of symbols]

10 counter circuit 12, 14 ROM 16 delay circuit 18 switching circuit P _in a clock pulse D address data P _a, P _b ROM output pulse C control signals P _out pulse output

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-62-245885 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 3/78

Claims (1)

(57) [Claims] A clock pulse is counted, and the counting result is calculated.
A counting circuit as a binary counter that outputs as address data composed of a plurality of bits, and pulse generation information corresponding to the address data are stored.
A read-only memory for inputting address data excluding the least significant bit from the counting circuit and outputting a corresponding pulse; and an address excluding the least significant bit output from the counting circuit.
Input the address data, and
A delay circuit that delays the output by an amount corresponding to the clock and outputs pulse generation information corresponding to the address data are stored.
Cage, enter the address data outputted from the delay circuit
And force, and characterized by including the corresponding other read-only memory which outputs a pulse, and a switching circuit by the output of the least significant bit of the address data is switched alternately connect the two read only memory Pulse generation circuit.