JPS6285515A - Digital integrated circuit - Google Patents

Abstract

PURPOSE:To actuate plural circuit within an integrated circuit IC just with a single input terminal by applying the 1st or 2nd pulse signal delivered from a digital IC again to this IC. CONSTITUTION:An input buffer 5 is connected to an input terminal 2 for external signal set within a digital IC1. The buffer 5 is connected to an AND gate 6 and this gate 6 is connected to the 1st glitch deleting circuit 7. The circuit 7 is connected to the 1st pulse detecting circuit 8 and the circuit 8 is connected to the 1st internal circuit 9 containing a switch. Furthermore an AND gate 11, the 2nd glitch deleting circuit 12, the 2nd pulse detecting circuit 13 and the 2nd internal circuit 14 containing a switch are connected successively to the buffer 5. The signal of the 1st pulse output circuit 16 is delivered via a buffer 18 and at the same time supplied to the gate 6 via a buffer 19 and also supplied to the gate 11 via an inverter 15. Thus plural circuits are actuated just with a single input terminal.

Description

[Detailed description of the invention] [Industrial application field] Unpublished No. 11 relates to digital integrated circuits, and in particular relates to digital integrated circuits equipped with a switch function,
Specifically, by applying a pulse signal output from a digital integrated circuit to the integrated circuit, one external signal input terminal of the integrated circuit is used to operate multiple switches inside the integrated circuit. The present invention relates to a digital integrated circuit equipped with a switch function for the purpose of

[Conventional technology]

Digital integrated circuits, which generally have many parts, are used [1] by applying predetermined signals and voltage levels to external input terminals of the integrated circuit.
It operates the switches inside the integrated circuit.

4 and 5 are block diagrams showing examples of conventional digital integrated circuits.

In FIG. 4, an internal circuit 23 of an integrated circuit 20 is connected to an input terminal 21 for an external signal of the integrated circuit 20 via a buffer 22 for human power, and an input terminal 7'-21 is It operates by adding ``LL level''.

In FIG. 5, the first internal circuit 38 of the integrated circuit 24
．． second internal circuit 37, third internal circuit 38. . . . An example of operating the n-th internal circuit 39 is shown.

Here, the first input terminal 1'29, the second input terminal -30,
Third input terminal 31. ...by the n-th input terminal 32! j-“H level” of parallel data obtained, ′
Information on the L level ° is manually input from the external signal input terminal 2C of the integrated circuit 24 as serial data sd by the parallel-serial conversion circuit 28.

Inside the integrated circuit 24, this serial data s
The serial-to-parallel conversion circuit 35 converts d into parallel data pdl- at "H level" or "L level".
pdn, the first internal circuit 36, the second internal circuit 37 . The respective switches of the third internal circuit 38, . . . the n-th internal circuit 33 are activated.

At this time, in order to latch the serial data sd to the serial-parallel conversion circuit 35, the launch pulse output circuit 27 and the latch pulse external 41''-'f input terminal 25 are required.

In addition, 33 and 34 in Fig. 5 are buff Ts for human power, respectively.
In FIGS. 4 and 5, Vcc is Ichihara, and G is ground.

[Problem that the invention seeks to solve]

[-As mentioned above, the circuit system shown in FIG. 4 has the drawback that in order to operate one internal switch, one external signal input terminal is occupied.

According to the circuit system shown in Figure 5, a parallel-to-serial conversion circuit and a latch pulse output circuit are required outside the integrated circuit, which has the disadvantage that the advantages of integrating the circuit are lost. When designing an integrated circuit, it is common to provide more functions and increase versatility in order to lower the price. However, on the other hand, the external signal input/output terminals of integrated circuits are subject to limitations such as their strength and the size of the integrated circuit package.
The number cannot be increased in proportion to the degree of integration of an integrated circuit; in other words, the restriction on the number of input/output terminals 7 for external signals is a major obstacle in designing an integrated circuit having many functions.

[Level L for solving problems]

A digital integrated circuit according to the present invention includes first and second pulse output circuits that output first and second pulse signals having different periods, respectively, and first and second pulse output circuits that output the first and second pulse signals, respectively. second output end f
-, one input terminal for an external signal -, a first AND gate that is connected to the input terminal and then connected to the first pulse output circuit via an inverter;
When connected to the input terminal f-, a second AND gate is connected to the second pulse output circuit via an input terminal; It has first and second pulse detection stages that are connected to each other and perform pulse detection, and the first and second pulse detection stages are connected to each other and perform pulse detection, and the first and second pulse detection stages output from the digital integrated circuit are , by applying voltage to the digital integrated circuit, it is possible to operate multiple circuits in the digital integrated circuit with one input terminal.
Embodiment] Next, an embodiment of the end 111 will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment for unissued use.

Inside the digital integrated circuit 1 shown in the figure, an input buffer 5 is connected to an input terminal 1'-2 for an external signal.
The buffer 5 is connected to the gates 1 and 6 of 51, the AND gate 6 is connected to the first grip removal circuit 7, and the glitch removal circuit 7 is connected to the first pulse detection circuit 8.
The pulse detection circuit 8 is connected to a first circuit having a switch.
It is connected to the internal circuit 9 of.

Similarly, the input rough r5 is connected to the second ant game 1-11, the second glitch removal circuit 12, the second pulse detection circuit 13, and the second internal circuit 14 having a switch.
are connected in order.

Inside the integrated circuit l, a first pulse output circuit 16
The signal Sl is sent to the buffer 18 at the output terminal 3 of the integrated circuit l.
At the same time, it is inverted by the inverter 10 and output to the other input terminal of the first AND gate 6.

Similarly, the signal S2 of the second pulse output circuit 17 is outputted to the output terminal 4 of the integrated circuit 1 via the buffer 19, and at the same time is inverted by the inverter 15 and output to the other input terminal of the second AND gate 11. has been done.

■, Here, input terminal 2 for external signals of integrated circuit l is set to “L”.
By applying the signal SO of "level", the buffer 5
(via the first AND gate 6 and the second AND gate)
11 becomes "L level" signals S3 and S4, which pass through the first glitch removal circuit 7 and the second glitch removal circuit 12, respectively, and are then sent to the first pulse detection circuit 8 and the second glitch removal circuit 12.
The pulse detection circuit 13 sends an "L level" signal S5 to the first internal circuit 9 and the second internal circuit 14, respectively.
, S6 are applied.

II. Furthermore, when a signal SO of "°H level" is applied to the input terminal 2 for external signals, the negation of the first pulse Sl is outputted to the output S3 of the first AND gate 6, and a glitch occurs. From the first pulse detection circuit 8 via the removal circuit 7,
A 'H level' signal S5 is applied to the first internal circuit 9. The negation of the second pulse s2 is output to the output S4 of the second anti-game 1-11, and the glitch removal circuit I2 is from the second pulse detection circuit 13 to the second internal circuit 1
A signal s6 of "H level" is applied to the signal s6.

■Thirdly, when the first output terminal 3 is connected in advance to the input terminal 2 for external signals as shown by the chain line in FIG. As shown in FIG. 2, a Gritsuna g1 is output based on the difference between the sum of the delay times of the output buffer 18 and the input buffer 5 and the delay time of the inverter 1o. However, it is removed by the first glyph removal circuit 7, and the pulse detection circuit 8 of :51 determines that there is no pulse, and the "L level" signal s5 is
is applied to the switch in the internal circuit 9 of the .

Note that the signal Sll in FIGS. 1 and 2 is the signal S1
indicates a signal pulse delayed by the output buffer 18 and the input buffer 5.

At the same time, a signal S3 which is an AND of the first delayed pulse Sit and the negation of the second pulse S2 is output to the second glitch remover 11 as shown in FIG. Via the circuit 12, the second pulse detection circuit 13 determines that a pulse is present, and applies an "H level" signal S6 to the second internal circuit 14.

■, again. Even when the second output terminal 4 is connected to the input terminal 2, the "H level" signal S5. A signal S6 at "L level" is output to the second pulse detection circuit 13.

As a result, the switches in the internal circuits 9 and 14 of the integrated circuit 1 can be operated independently by the input terminal 2 for external signals.

Here, the first glitch removal circuit 7 and the second glitch removal circuit 12 deny the first pulse output St, deny the second pulse output S2, and deny the first delayed pulse output Sll.
and the negation of the second pulse output S2, and the logical product output S3 of the second delayed pulse output and the negation of the first pulse output S1, respectively, are configured so as not to be mistakenly recognized as glitches. Of course, it must be done.

Note that the glitch removal circuit 7.12 and the pulse detection circuit 8.
For example, one stage of pulse detection 'r that performs glitch removal and pulse detection simultaneously by combining 13 with
There is a circuit shown in Figure 3.

Reference numerals 51 to 54 in the figure represent a plurality of flip-flops connected in series, and the output terminals Q of each of the flip-flops 51 to 54 are connected to an OR gate 55, which outputs a control signal to an output terminal 56. . At the clock terminal T of each flip-flop 51-54.

A clock signal ck is inputted via a diagonal terminal 57.

58 is an input terminal, which is connected to the input terminal of the first flip-flop 51, and the output terminal Q of the first flip-flop 51 is connected to the input terminal of the second flip-flop 52. Similarly, the second flip-flop 52 is connected to a third flip-flop 53, and the third flip-flop 53 is connected to a fourth 7-lip flop 54.

When the signals S3 in FIGS. 1 and 2 are input to the input terminal f-58, a signal of "L" is sent to the output terminal 56, and the signals S4 in FIGS. 1 and 2 are input. Then, an "H" signal is sent to the output terminal 56.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of regular and different pulse signal outputs, which are used for purposes other than the multi-hair switch function, are required for the multi-purpose switch moat. Since it can be used for other input signals, it has the effect of reducing the need for input terminals for external signals that control switches inside the integrated circuit.

Furthermore, since the signal applied to the integrated circuit is a signal output from the integrated circuit, there are advantages such as no additional circuitry external to the integrated circuit is required, and no initial settings are required when the power is turned on.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment according to the present invention, Fig. 2 is a time chart explaining the embodiment of the present invention, and Fig.
The figure is a block diagram specifically showing a part of the embodiment shown in FIG.
Figure 4 and 0'! FIG. 5 is a block diagram showing each conventional example. l...Digital integrated circuit? ... Input terminal 3.4 ... Output terminal 5 ... Input buffer 6.11 ... AND gate 7.12 ... Glitch removal circuit 8, +3 ... Pulse detection circuit 9,! 4...Internal circuit of integrated circuit 10.15...Inverter 18, 17...Pulse output circuit 18.19...Output buffer Patent applicant !t: Uchihara P¥ discount
, , , Figure 2 Figure 4

Claims (1)

[Claims] First and second pulse output circuits that respectively output first and second pulse signals having different fixed cycles; and first and second pulse output circuits that output the first and second pulse signals, respectively. a second output terminal; one input terminal for an external signal; a first AND gate connected to the input terminal and connected to the first pulse output circuit via an inverter; a second AND gate connected to the input terminal and connected to the second pulse output circuit via an inverter; and a second AND gate connected to the first and second AND gates to perform pulse detection. A digital integrated circuit comprising: first and second pulse detection means;