JP2689735B2 - Serial signal switching control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial signal switching control circuit, and more particularly to a signal switching control circuit when a plurality of control units control other circuits using serial signals in a digital communication device or the like.

[0002]

2. Description of the Related Art A conventional serial signal switching control circuit is shown in FIG. The figure shows a configuration in which data from two control packages 1 and 2 is switched by the switching control package 3 and input to the controlled package 4.

The control package 1 has a parallel-serial (P / S) converter 11 for converting the control parallel signal 12 into a control serial signal 14. Note that 13
Is a frame pulse of the serial signal 14, and 15 is a clock.

The control package 2 also has a parallel-serial conversion section 21 similar to the control package 1. In addition, 23 is a frame pulse of the serial signal 24,
25 is a clock.

Furthermore, the switching control package 3 has a switching control unit 33 and selectors 31, 32 and 37, and based on a switching control signal 36 output from the switching control unit 33, the selectors 31, 32 and 37 are simultaneously operated. Switch.

The controlled package 4 receives the control serial signal 34 output from the selector 31 in the switching control package 3, converts it into a control parallel signal 43, and separates it. It has a (S / P) converter 41. The frame pulse 35 and the clock 38 output from the selectors 32 and 37 are also input to the serial-parallel converter 41.

Next, the operation of the above-mentioned conventional serial signal switching control circuit will be described with reference to the time chart of FIG. In the figure, the control serial signal 14 and the frame pulse 1 output from the control package 1 in FIG.
3, clock 15 is shown. Similarly, the control serial signal 24, the frame pulse 23, and the clock 25 output from the control package 2 are also shown.

The switching control signal 36 switches the selectors 31, 32 and 37 in FIG. 1 according to the polarity (H or L).

Furthermore, the figure also shows the control serial signal 34, frame pulse 35, and clock 38 after selector selection. Based on these signals, the controlled package responds to the frame pulse 35 in the controlled package. As a result, the parallel signal 43 is generated. In FIG. 4, the parallel signal 43 of the serial-parallel converter 41 in the controlled package is shown as being output at the trailing edge of the frame pulse 35.

In the controlled package 4, the parallel signal 43
Based on the above, communication control and the like are performed.

By the way, in the conventional serial signal switching control circuit shown in FIG. 3, the control serial signal and the frame pulse output from the control packages of the two systems are asynchronous between the two systems. Therefore, as shown in FIG. 4, the interval between the frame pulses 35 before and after the generation of the switching control signal 36 becomes shorter than the correct cycle of one frame. As a result, since the serial pulse 35 having an incorrect cycle is input to the serial-parallel converter 41 on the controlled package side, the control parallel signal 43
Has a drawback in that "A" and "B" are mixed as in the data D, and erroneous data in which the output bit position is shifted is output, resulting in erroneous control.

[0012]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional drawbacks, and an object thereof is to provide a serial signal switching control circuit in which erroneous data is not output.

[0013]

The serial signal switching control circuit according to the present invention is a switching means for simultaneously switching and transmitting a plurality of types of externally input serial data and a frame pulse corresponding to each of them and defining a frame of the corresponding serial data. A serial signal switching control circuit which sequentially holds the serial data from the switching means and sends one frame of the serial data as parallel data in response to the frame pulse. It is characterized in that it has a prohibition means for prohibiting the input of the frame pulse to the conversion means immediately after the operation.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an embodiment of a serial signal switching control circuit according to the present invention, and the same portions as those in FIG. 3 are designated by the same reference numerals. In the figure,
The serial signal switching control circuit of the present embodiment latches the switching control signal 36 with the frame pulse 35 after switching selection, and the gate 55 that takes the exclusive OR of the latched signal and the switching control signal 36. And a pulse generation circuit 50 including an output 52 from an exclusive OR gate
And a gate 53 that takes the logical sum of the frame pulse 35 after switching and selection are added to the circuit of FIG.

The control package 1 converts the control parallel signal 12 into a control serial signal 14, and supplies the control serial signal 14 and the frame pulse 1 to the switching control package 3.
3 and clock 15 are transmitted. Similarly, the control package 2 sends the control serial signal 2 to the switching control package 3.
4, the frame pulse 23 and the clock 25 are transmitted.
In addition, the switching control package 3 selects one of the control serial signal, the frame pulse, and the clock from the two-system control package based on the information of the switching control signal 36 output from the switching control unit 33. , 32
And 37.

FIG. 2 shows a time chart of the operation of each part of the circuit of this embodiment when the switching control signal 36 changes from L to H. When the switching control signal changes from L to H, the control serial signal 34 after the selector is selected.
And the frame pulse 35 becomes as shown in FIG. Here, by latching the switching control signal 36 with the frame pulse 35 after switching selection, the output 51 is sent out from the latch circuit 54 in the pulse generation circuit 50.
Further, the exclusive OR of this output 51 and the switching control signal 36 is output 52 from the pulse generation circuit 50.
Is sent as

The output 52 is a signal which becomes H from the time when the switching control signal 36 changes from L to H to the time when the frame pulse 32 rises next time. That is, it becomes H only when the levels of the original switching control signal and the latched switching control signal are different.

A frame pulse 42, which is a signal obtained by ORing the output 52 and the frame pulse 35 after selector selection through the OR gate 53, masks the first pulse of the frame pulse 35 after switching control. It becomes a waveform. Therefore, erroneous data in which the output bit position is shifted at the time of switching is not output as the control parallel signal 43. Therefore, the control data E of the control package 1 before switching is held until the next falling edge of the frame pulse appears.

That is, the input of the frame pulse immediately after the switching operation, which is the portion where the malfunction occurs, is prohibited.

In this embodiment, the control package is 2
Although the case of one sheet has been described, it is obvious that the present invention can be applied to the case of including three or more control packages. In that case, the number of input terminals of each selector may be increased.

[0022]

As described above, according to the present invention, erroneous control is not performed at the time of switching by prohibiting the input of the frame pulse immediately after the switching operation so that erroneous control data is not serial-parallel converted. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a serial signal switching control circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of each unit in FIG.

FIG. 3 is a block diagram showing a configuration of a conventional serial signal switching control circuit.

FIG. 4 is a time chart showing the operation of each unit in FIG.

[Explanation of symbols]

 13, 23, 35, 42 Frame pulse 14, 24, 34 Serial signal 15, 25, 38 Clock 31, 32, 37 Selector 50 Pulse generation circuit 53 OR gate

Claims (1)

(57) [Claims] 1. A switching means for simultaneously switching and transmitting a plurality of kinds of externally input serial data and a frame pulse corresponding to each of them and defining a frame of the corresponding serial data, and serial data from the switching means. A serial signal switching control circuit having a conversion means for sequentially holding and transmitting one frame thereof as parallel data in response to the frame pulse, wherein the frame to the conversion means immediately after the switching operation by the switching means A serial signal switching control circuit having a prohibiting means for prohibiting pulse input.