GB1586153A - Data transmission - Google Patents

Description

(54) DATA TRANSMISSION (71) We, SIEMENS AKTIENGESELL SCHAFT, a German Company, of Berlin and Munich, Federal Republic of Germany, do hereby declare the invention for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement:- The invention is concerned with arrangements for setting up differing operating modes in a called data receiver which is supplied with a plurality of call signals from a calling data transmitter, and relates to receivers having such facilities.

It is possible to set up differing operating modes in a called data receiver by transmitting to the data receiver control signals together with the usual call signals. In this case a control stage which recognises both the call signals and the control signals must be provided in the data receiver. However, a circuit arrangement of this kind necessitates a high outlay as it must be ensured, for example, that the control signals are not analysed as call signals.

Therefore the aim of the present invention is to provide a circuit arrangement which permits the setting up of differing operating modes in a called data receiver in a simple manner.

According to the present invention there is provided a data receiver including an arrangement for setting up different operating modes of the receiver in response to call signals received thereby from a calling data transmitter, the arrangement comprising a serial to parallel converter in which received call signals cah be stored, and a comparator arranged in operation to compare the call signals stored in the serial to parallel converter with addresses assigned to the receiver and to produce, upon recognition of said call signals in non inverted form, a first mode control signal serving to set up a first mode of operation of the receiver and, upon recognition of said call signals predetermined one(s) of which are in inverted forin, a second mode control signal serving to set up a second mode of operation of the receiver.

Preferably the comparator is arranged to produce the second mode control signal when the call signals are received alternately in non-inverted and inverted form.

In a preferred embodiment the comparator comprises a plurality of EQUIVA LENCE gates followed by AND-gates and NOR-gates.

In the following exemplary embodiments of the present invention will be described making reference to the accompanying drawings in which: Figure 1 is a block circuit diagram of a circuit arrangement which is provided in a calling data transmitter and which serves to produce signals to be transmitted; Figure 2 is a block circuit diagram of a circuit arrangement which is provided in a called data receiver and which serves to set up differing operating modes; and Figure 3 is a circuit diagram of a comparator.

The circuit arrangement illustrated in figure 1 which serves to produce call signals in a data transmitter comprises a multiplexer MX, the inputs of which are supplied with signals RS1 to RS3 emitted from switches SW1 to SW3 and with data signals D1 produced in a data source DQ. The signals RS1 to RS3 and the data signals D1 each have six bits, and are fed in parallel to the relevant inputs of the multiplexer MX. Five bits represent the characters to be transmitted in accordance with the fiveelement code CCITT No. 2, whereas the sixth bit is a parity bit.In each case one of the signals RS1 to RS3 or the data signals D1 is emitted from the output of the multiplexer MX as signals S1 and fed to a code converter CU1. The code converter CU1 produces signals S2 which are assigned to the signals S1 and which have seven bits of which four bits have the binary value 0 and three bits the binary value 1.

Via a switch SW4, a signal RQS is emitted to the code converter CU1 which causes a special signal RQ to be produced therein as signal S2. This may, for example, be a repetition signal indicating that the transmitted data is a repeat of data pre viously transmitted but incorrectly received (as in ARQ system).

The signals S2 are fed to the parallel inputs of a shift register SR1. With the aid of timing pulses T1 produced in a pulse generator TG1, the signals S2 are input in parallel fashion into the shift register SR1 and subsequently read out therefrom in serial fashion. The signals S3 which are read out in serial fashion are supplied to a first input of an EXCLUSIVE-OR-gate Al. Signals S4 produced by the pulse generator TGl are present at the second input of the EXCLU SIVE-OR gate Al. When the signals S4 have the binary value 0, data signals D2 whose binary values correspond to the binary values of the signals S3 are emitted from the output of the EXCLUSIVE-OR gate Al.When the signal S4 assumes the binary value 1, the binary values of the data signals D2 correspond to the inverted binary values of the signals S3. The data signals D2 are transmitted to the data receiver.

When a remote data receiver is called, the address of the data receiver is set up with the aid of the switches SW1 to SW3.

The signals RSl to RS3 each represent, for example, binary-coded digits between 0 and 9. When the remote data receiver is called, firstly the switch SW4 is closed and in the code converter CUl the signal RQS produces the special character RQ which for example is formed from the binary values 0110100. This special character RQ is input into the shift register SR1 as signal S2 and subsequently emitted as data signal D2. It will be assumed that the signal S4 has the binary value 0. The multiplexer MX subsequently switches through the signals RS1 to RS3 as signals S1 consecutively to the code converter CUl.

The code converter CUl produces signals S2 assigned to the signals S1 which it likewise emits consecutively to the shift register SR1. When a first operating mode is to be set up in the data receiver, the switch SW5 remains open and the signal S4 retains its binary value 0. The binary values of the data signals D2 are thus always equal to the binary values of the signals S3.

If a second operating mode is to be set up in the called data receiver, a switch SW5 is closed and the signal S4 alternately assumes the binary value 0 and the binary value 1. During the transmission of the special character RQ, the signal S4 has the binary value 0. During the transmission of the character set up by the switch SW1, the binary values of the signals S3 are inverted by the EXCLUSIVE-OR gate Al. During the transmission of the character assigned to the switch SW2, the signal S4 again has the binary value 0 and the binary values of the signals S3 are not inverted. During the transmission of the character assigned to the switch SW3, the signal S4 reasumes the binary value 1 and the binary values of the data signals D2 correspond to the inverted binary values of the signals S3.

If the first operating mode is to be set up in the data receiver, the call signals formed from the special characters RQ and the characters assigned to the switches SWI to SW3 are transmitted in non-inverted form as data signals D2 to the data receiver.

If however, the second operating mode is to be set up in the data receiver, the characters assigned to the switch SW1 and the switch SW3 which are present at the output of the code converter CU1 are transmitted in inverted form to the data receiver whereas the characters assigned to the special characters RQ and those assigned to the switch SW2 are transmitted in noninverted form to the data receiver.

The circuit arangement illustrated in figure 2 which serves to set up differing operating modes in a called data receiver contains a serial to parallel converter (a shift register SR2), a pulse generator TG2, an EXCLUSIVE-OR gate A2, a code converter CU2, a comparator VG and three switches SW6 to SW8. The call signals which are emitted from the data transmitter and which are formed from the special characters RQ and from the characters assigned to the switches SW1 to SW3 are input in serial form into the shift register SR2 by the data signals D2. During the input, the pulse generator TG2 emits timing pulses T2 to the shift register.The data signals D2 are simultaneously present at a first input of the EXCLUSIVE-OR gate A2, whereas signals S5 are present at the second input. From its output the EXCLUSIVE-OR gate A2 emits data signals D3 via the code converter CU2 to a data output DS. In dependence upon the binary value of the signal S5, the data signals correspond either to the data signals D2 or to the inverted data signals D2.

From its parallel outputs, the shift register SR2 emits signals R1 to R4 (7 bits each) assigned to the call signals to first inputs of a comparator VG. Address signals AD1 to AD3 produced in switches SW6 to SW8 are present at the second inputs of the comparator VG. The address signals AD1 to AD3 are to identify the particular data receiver. The signals R1 represent the special character RQ whereas the signals R2 to R4 are assigned to the addresses set up by means of the switches SW1 to 5W3 in the data transmitter. When the comparator VG recognises the presence of the special character RQ and the signals AD1 to AD3 are identical to the signals R2 to R4, the comparator VG recognises a first operating mode to be set up in the data receiver and emits a signal SARQ from its output.When the comparator VG recognises the special character RQ and the signals R2 and R4 are identical to the inverted signals AD 1 and AD3, and furthermore the signals R3 are identical to the non-inverted signals AD2, the comparator VG recognises a second operating mode to be set up in the data receiver and emits a signal SFEC from its output. The signal SARQ is fed for example to the pulse generator TG2 and when this occurs the pulse generator TG2 emits a signal S5 having the binary value 0 so that the data signals D3 correspond to the data signals D2. The signal SFEC can likewise be fed to the pulse generator TG2 and when this occurs the signal S5 assumes the binary value 1 in the case of each second character and the data signals D3 then in each case correspond to the inverted data signals D2.

During the first operating mode set up by the signal SARQ following code conversion into the five-element code in the code converter, the data signals are thus switched through to the data output DS whereas in the case of the second operating mode which is set up by the signal SFEC either a non-inverted character or the corresponding inverted character is fed to the data output. As a result of the inversion of each second character during the second operation mode, the inversion of each second character effected in the data transmitter as a result of the closure of the switch is cancelled so that the data signals D3 in each case correspond to the signals S3 in the data transmitter. The code converter CU2 is provided at its input and at its output with a shift register (not illustrated).

With the aid of these shift registers a seriesparallel conversion is carried out prior to the code conversion and a parallel-series conversion is carried out following the code conversion.

The comparator VG illustrated in figure 3 contains 21 EQUIVALENCE gates A3 to A23, three NOR-gates N1 to N3 and six AND-gates U1 to U6. The NOR-gate N1 and AND-gate U1 check whether the call signal stored in the first stage of the shift register SR2 represents the special character RQ having the binary values 0110100. The signals Rill, R14, R16 and R17 assigned to the binary value 0 in the special character RQ are present at the inputs of the NOR-gate N1.When all of these signals have the binary value 0, the NOR-gate N1 emits a signal having the binary value 1 to a first input of the ANDgate Ui. The signals R12, R13 and R15 assigned to the binary value 1 in the special character RQ are present at the further inputs of the AND-gate U1. When these signals have the binary value 1, whereas all the signals at the inputs of the NORgate N1 have the binary value 0, the ANDgate U1 emits a signal S6 to the AND-gates U2 and U3. The signals ADil to AD17, AD21 to AD27, and AD31 to AD37 assigned to the signals AD1 to AD3 are present at each of the first inputs of the EQUIVALENCE gates A3 to A23.The signals R21 to R27, R31 to R37, and R41 to R47 assigned to the call signals R2 to R4 are present at the second inputs of the EQUIVALENCE gates A3 to A23. When the binary values of the signals AD1 to AD3 agree with the binary values of the signals R2 to R4, the EQUIVALENCE gates A3 to A23 emit signals having the binary values 1 from their outputs. In this case the signals at the inputs of the ANDgates U4 to U6 likewise possess the binary value 1 and since the outputs of these AND-gates U4 to U6 are connected to the inputs of the AND-gate U2, if the signal S6 is simultaneously present the AND-gate U2 emits the signal SARQ which serves to set up the first operating mode from its output.

If every second one of the call signals, i.e. those characters assigned to the switches SW1 and SW3 are transmitted in inverted form to the data receiver and stored correspondingly in the shift register SR2, the EQUIVALENCE gates A3 to A9 and A17 to A23 emit signals having the binary value 0 from their outputs. These signals are applied to the inputs of the NOR-gates N2 and N3 and since all signals at the inputs of the NOR-gates N2 and N3 have the binary 0, these emit signals having the binary value 1 to the AND-gate U3.If, simultaneously, the special character RQ is recognised, the signal S6 has the binary value 1, the signal assigned to the switch SW2 is transmitted in non-inverted form, and the AND-gate U5 emits a signal having the binary value 1, the signal SFEC at the output of the AND-gate U3 assumes the binary value 1 in order thus to set up the second operating mode. The signal SARQ simultaneously possesses the binary value 0.

If either the special character RQ is not recognised or not all the binary values of the signals R2 to R4 are identical to those of the signals AD1 to AD3 or to those of the signals AD2 and of the inverted signals AD1 and AD3, the comparator VG emits neither the signal SARQ nor the signal SFEC. Only when the special character RQ is recognised and all the binary values of the signals R2 to R4 are identical to those of the signals AD1 to AD3, is the signal SARQ produced and the first opera ting mode set up in the data receiver. When the special character RQ is recognised and the binary values of the signal R3 are identical to those of the signal AD2 and at the same time the binary values of the signals R2 and R4 are identical to those of the inverted signals AD1 and AD3, does the comparator VG emit, from its output, the signal SFEC which sets up the second operating mode.

With the aid of the comparator VG at the same time a very simple check is carried out to establish whether the call signals are identical to predetermined signals and whether the first or the second operating mode is to be set up in the data receiver. The outlay required for setting up the second operating mode consists, for example, merely in the NOR-gates N2 and N3 and in the AND-gate U3.

In order to be able to set up a plurality of operating modes, it is also possible to transmit less than two or more than two call signals in inverted form to the data receiver in dependence upon the particular operating mode to be set up. In order to be able to recognise a further operating mode, it is again merely necessary to provide NOR-gates and a subsequently connected AND-gate.

The arrangements described have the advantage that they necessitate a relatively low outlay since the comparator which is arranged in the data receiver and serves to recognise the address can be used to recognise the desired operating mode. The desired operating mode is determined simultaneously with the address of the called called data receiver. The arrangemest also has the advantage that it is unnecessary to transmit a separate control signal from the data transmitter to the data receiver in order to set up the desired operating mode.

WHAT WE CLAIM IS: 1. A data receiver including an arrangement for setting up different operating modes of the receiver in response to call signals received thereby from a calling data transmitter, the arrangement comprising a serial to parallel converter in which received call signals can be stored, and a comparator arranged in operation to compare the call signals stored in the serial to parallel converter with addresses assigned to the receiver and to produce, upon recognition of said call signals in non inverted form, a first mode control signal serving to set up a first mode of operation of the receiver and, upon recognition of said call signals predetermined one(s) of which are in inverted form, a second mode control signal serving to set up a second mode of operation of the receiver.

2. A data receiver according to claim 1, in which the serial to parallel converter is a shift register.

3. A data receiver according to claim 1 or 2, in which the comparator is arranged to produce the second mode control signal when the call signals are received alternately in non-inverted and inverted form.

4. A data receiver according to claim 1, 2 or 3, in which the comparator comprises a plurality of EQUIVALENCE gates followed by AND-gates and NOR-gates.

5. A data receiver substantially as herein described with reference to figures 2 and 3 of the accompanying drawings.

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (5)

**WARNING** start of CLMS field may overlap end of DESC **. ting mode set up in the data receiver. When the special character RQ is recognised and the binary values of the signal R3 are identical to those of the signal AD2 and at the same time the binary values of the signals R2 and R4 are identical to those of the inverted signals AD1 and AD3, does the comparator VG emit, from its output, the signal SFEC which sets up the second operating mode. With the aid of the comparator VG at the same time a very simple check is carried out to establish whether the call signals are identical to predetermined signals and whether the first or the second operating mode is to be set up in the data receiver. The outlay required for setting up the second operating mode consists, for example, merely in the NOR-gates N2 and N3 and in the AND-gate U3. In order to be able to set up a plurality of operating modes, it is also possible to transmit less than two or more than two call signals in inverted form to the data receiver in dependence upon the particular operating mode to be set up. In order to be able to recognise a further operating mode, it is again merely necessary to provide NOR-gates and a subsequently connected AND-gate. The arrangements described have the advantage that they necessitate a relatively low outlay since the comparator which is arranged in the data receiver and serves to recognise the address can be used to recognise the desired operating mode. The desired operating mode is determined simultaneously with the address of the called called data receiver. The arrangemest also has the advantage that it is unnecessary to transmit a separate control signal from the data transmitter to the data receiver in order to set up the desired operating mode. WHAT WE CLAIM IS:

1. A data receiver including an arrangement for setting up different operating modes of the receiver in response to call signals received thereby from a calling data transmitter, the arrangement comprising a serial to parallel converter in which received call signals can be stored, and a comparator arranged in operation to compare the call signals stored in the serial to parallel converter with addresses assigned to the receiver and to produce, upon recognition of said call signals in non inverted form, a first mode control signal serving to set up a first mode of operation of the receiver and, upon recognition of said call signals predetermined one(s) of which are in inverted form, a second mode control signal serving to set up a second mode of operation of the receiver.

2. A data receiver according to claim 1, in which the serial to parallel converter is a shift register.

3. A data receiver according to claim 1 or 2, in which the comparator is arranged to produce the second mode control signal when the call signals are received alternately in non-inverted and inverted form.

4. A data receiver according to claim 1, 2 or 3, in which the comparator comprises a plurality of EQUIVALENCE gates followed by AND-gates and NOR-gates.

5. A data receiver substantially as herein described with reference to figures 2 and 3 of the accompanying drawings.