JPH0630003A - Multiplex transmitter - Google Patents

Abstract

PURPOSE:To reduce the burden of a processor by detecting the change of data with a data change detector means and rewriting the data according to its change to produce and transmit a message corresponding to the rewriting contents by a data holding means. CONSTITUTION:When the output pulse of a pulse converter 13a0 is inputted to a latch 14a, the code of the 1st bit of the latch 14a is set at '1' and all other bits of the latches 14a and 14b are set at '0'. Therefore this fact shows that the 1st bit of a latch 15a is changed. A set pulse SP0 is produced in the timing when the rewriting of the contents of latches 14a, 14b, 15a and 15b are complete. Thus the contents of the latch 14a are inputted to a transmission shift register 16, and a set pulse SP4 is produced in the next timing. Then the contents of the latch 14a are transmitted from the register 16 as the serial data. The contents of the latches 14b, 15a and 15b are transmitted via the register 16 in the next timing in the same way.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplex transmission device mounted on an automobile or the like.

[0002]

2. Description of the Related Art This kind of multiplex transmission device has been introduced for the purpose of preventing the signal line from being enlarged due to the electronic control of automobiles, and the status signals of various auxiliary devices of automobiles are transmitted to various parts of the vehicle. They are housed in the arranged nodes respectively, and these nodes are connected by multiplex transmission lines to transmit and receive signals in a time-division manner, which significantly reduces the number of wiring lines required for signal transmission and reception. is doing. An example of such a multiplex transmission apparatus is disclosed in Japanese Patent Laid-Open No. 2-1649.

FIG. 5 shows an example of the overall configuration of a multiplex transmission device. As shown in the figure, the front multiplex node FN, the combination switch multiplex node CS, the meter multiplex node MT, the rear multiplex node RN, etc. are connected to each other by a multiplex bus MB. Each multi-node accommodates ON / OFF signals and the like of auxiliary devices and switches in the vicinity thereof. Further, messages are transmitted and received between these multiple nodes via the multiplex bus MB.

FIG. 4 shows an example of a frame format of a message transmitted / received between multiple nodes. As shown in FIG. 4, the message has a message start code SOM,
Message priority MP, network identification code NID, data identification code DID, data field DF, error check code ER, data end code EO
D, a network control acknowledgment area ANK, a message end code EOM, and the like.

Here, the message start code SOM is a code indicating the beginning of the message, the message priority MP is a code indicating the priority of the message, the network identification code NID is a code identifying the network, and the data identification code DID is the following data. It is a code for identifying the contents of the field DF, and is a code which allows the receiving node to freely select messages on the multiplex bus MB. The receiving node checks the data identification code DID to determine whether the message is necessary for its own node, and fetches it if necessary.

The data field DF has a fixed length of 4 bytes, and has a valid / invalid designation area V / I and a data area D.
It consists of T and. The data area DT consists of 2 bytes (= 16 bits), and various data such as data indicating the ON / OFF state of the auxiliary devices accommodated in the node that issued the message is written in the data DT area.

The valid / invalid designation area V / I is composed of 2 bytes like the data DT, and each bit thereof corresponds to each data in the lower 2 bytes of the data area DT, and the valid / invalid of each data is bit. It is a designated code that is designated for each item. This valid / invalid designated area V / I is the data D
This is introduced in order to construct a signal system that can be commonly used for all vehicle types by designating valid / invalid of each data in T for each vehicle type. If the valid / invalid designation code is not used, the entire area of the data field DF (= 4
All bytes) can be used as the data area DT.

The error check code ER is a code for error check by CRC, the data end code EOD is a code indicating the end of the data including the CRC code, and the acknowledgment area ANC is a reception response signal of all nodes connected to the network. ACK return area, message end code EOM is a code indicating the end of the message.

[0009]

In a multiplex transmission apparatus using a communication IC controlled by a microprocessor or the like, when each node transmits a message, each node turns on / off various auxiliaries accommodated in the node. The OFF state is checked and those data are written in the data area DT of the message and transmitted. Therefore, it takes time to create a message, and the processing time for message transmission becomes long.
Also, since such message creation is usually performed by software processing by the microprocessor,
The processing load of software is heavy.

On the other hand, the ON / OFF data of the auxiliary devices is considered to be sufficient if only the changed data is notified to other nodes when the contents thereof change. It is desirable that a hardware circuit can automatically and quickly notify other nodes without the aid of software.

The present invention has been made in view of the above circumstances, and an object thereof is to immediately detect a change in data content in a multiplex transmission device by a hardware circuit. The purpose is to notify other nodes of the change.

[0012]

In order to solve the above-mentioned problems, the transmission circuit of the multiplex transmission device of the present invention is effective for a data area in which various kinds of transmission data are written and correspondence of each transmission data in the data area. A transmitting circuit of a multiplex transmission device for transmitting / receiving a message including a valid / invalid area for entering / invalid information between nodes, and a data change detecting means for detecting a change in transmission data and a valid / invalid area are set. Effectiveness/
In addition to holding invalid information, when a change in transmission data is detected by the data change detecting means, valid / invalid information corresponding to the changed transmission data is set to "valid" indicating that the transmission data has changed. Data for holding valid / invalid setting means for setting and transmission data set in the data area, and rewriting the contents of the changed transmission data according to the change when the change in the transmission data is detected by the data change detecting means. When a change in the transmission data is detected by the holding means and the data change detecting means, based on the contents of the valid / invalid setting means and the data holding means, the valid data corresponding to the transmission data including the changed contents of the transmission data is included. / A transmission control means for creating and transmitting a message in which invalid information is set to "valid".

The receiving circuit of the multiplex transmission apparatus of the present invention is
A receiving circuit of a multiplex transmission device for transmitting and receiving a message between nodes, which includes a data area for writing various transmission data and a valid / invalid area for writing valid / invalid information corresponding to each transmission data in the data area. , Valid / invalid information of valid / invalid area in received message Valid / invalid
The invalid information holding means, the data holding means for holding the transmission data of the data area in the received message, the valid / invalid information of the valid / invalid information holding means and the transmission data of the data holding means are input, and the valid / invalid is input. It is provided with a valid / invalid judging means for judging that the information having "valid" is the contents of the transmission data corresponding thereto and selecting and outputting the transmission data.

[0014]

In the transmitting circuit, when the transmission data changes,
The data change detecting means detects this, and the valid / invalid setting means sets the valid / invalid information corresponding to the changed transmission data to "valid" indicating that the transmission data has changed. The data holding means rewrites the contents of the changed transmission data according to the change. Based on these contents, the transmission control means creates a message including the contents of the changed transmission data and making the validity / invalidity information corresponding to the transmission data “valid”, and transmits the message.

In the receiving circuit that receives this message,
The valid / invalid holding means holds the valid / invalid information of the valid / invalid area in the received message, the data holding means holds the transmission data of the data area in the received message, and the valid / invalid judgment means validates them. / It judges that "valid" of the invalid information is the contents of the transmission data corresponding to it, and selects and outputs the transmission data.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 shows a configuration example of a multi-node of a multiplex transmission apparatus as an embodiment of the present invention, and FIG. 1 shows a configuration example of a circuit portion related to enable / disable control of a transmission circuit in the multi-node of this embodiment. However, FIG. 2 shows a configuration example of a circuit portion relating to the enable / disable control of the receiving circuit in the multiplex node of this embodiment.

In FIG. 3, the multi-node is the transmission circuit 1,
The reception circuit 2, a clock generator 3 that generates a clock used in the node, a transmission / reception control unit 4 that controls overall transmission / reception, a bus interface unit 5 and the like are configured. The transmission circuit has 16 input ports PA0 to PA7, PB0 to
PB7 and these input ports PA0-PA7, P
ON / OFF signals of various auxiliary devices and the like are input to B0 to PB7. The receiving circuit 2 has 16 output ports PC0 to PC7 and PD0 to PD7, to which drive circuits such as various auxiliary devices are connected. The bus interface unit 5 is connected to the multiple buses to interface the transmission and reception of messages with other nodes.

In the transmission circuit of FIG. 1, 16 switches SW0 to SW7 consisting of two groups A and B are switches for indicating the ON / OFF states of corresponding auxiliary devices and the like. When an auxiliary device or the like changes its state from OFF to ON or from ON to OFF, a contact signal that is grounded is output only when switching. These switches S
W0~SW7 analog low-pass filter 11a ₀ for each denoising ~11a _6, 11b ₀ ~11b ₆ via the transmission circuit 1 input port PA0~PA7, PB0~PB
Input to 7.

Input ports PA0-PA7, PB0-P
Signal input to B7 are input further each pulse converter _{13a 0 ~13a 6, 13b 0 ~13b} 6 via a digital low-pass filter _{12a 0 ~12a 6, 12b 0 ~12b} 6. These pulse converters 13a ₀ ~
13a _6, 13b ₀ ~13b ₆ is the corresponding switch SW
When a contact signal is input from, it operates to generate and output a pulse having a constant pulse width.

Numerals 14a and 14b are latches for generating a code of each bit of the 16-bit valid / invalid designated area V / I in the message. The latch 14a is a high-order 1 byte of the valid / invalid designated area. 14b is the lower one
It generates a byte code and has 8-bit parallel input and output terminals. Output pulses from the pulse converters 13a _{0 to} 13a ₆ are input to the input bits of the latch 14a, and output pulses from the pulse converters 13b _{0 to} 13b ₆ are input to the input bits of the latch 14b. Each bit of the latches 14a and 14b is "0" in the initial state, but is set to "1" when the output pulse from the corresponding pulse converter is input, while the clear signal CLR is input. It operates so that all bits are cleared to "0".

Reference numerals 15a and 15b are latches for generating data of each bit of the 16-bit data area DT in the message. The latch 15a is the upper 1 byte of the data area DT, and the latch 15b is the lower 1 byte thereof. It generates data and has an 8-bit parallel input terminal and an 8-bit parallel output terminal. The output pulse from the pulse converters 13a _{0 to} 13a _{6 is} supplied to each input bit of the latch 15a and the latch 1
The pulse converters 13b _{0 to} 13b are provided for the respective input bits of 5b.
Output pulses from ₆ are input respectively. Each bit of the latches 15a and 15b is composed of a toggle flip-flop or the like. When an output pulse is input from the corresponding pulse converter, the output of the bit is changed between "0" and "1" at each input. It operates to switch alternately with.

These latches 14a, 14b, 15a, 1
The 8-bit parallel outputs of 5b are input to the transmission shift register 16, respectively. The transmission shift register 16 has an 8-bit parallel input, and when the set pulse SP4 is input, the transmission shift register 16 operates to perform parallel-serial conversion into serial data and output the serial data. When the set pulses SP0, SP1, SP2, and SP3 are input to the latches 14a, 14b, 15a, and 15b, the latch register 14a, 14b, 15a, and 15b stores its own data in the shift register 16
It is designed to be sent to.

Each of the pulse converters 13 is connected to the OR gate 17a.
Output pulses from a _{0 to} 13a ₆ are input, and OR
Output pulses from the pulse converters 13b _{0 to} 13b ₆ are input to the gate 17b. These OR gates 17
The output signals of a and 17b are input to the transmission control unit 18 as transmission request pulses. Upon receiving the transmission request pulse, the transmission control unit 18 operates to give a control signal for timing generation to the timing generation unit 19.

Further, the timing generator 19 is based on these control signals and latches 14a, 14b, 14a, 14
b, set pulse SP0 to the transmission shift register 16
SP4, clear signal CLR to the latches 14a and 14b,
Operation clock CK0 to the transmit shift register 16, a digital low-pass filter 12a ₀ ~12a _6, 12b ₀ ~1
Operable to deliver to respectively generate operation clocks CK1 to 2b _6.

In the receiving circuit of FIG. 2, the message input from the multiplex bus is input to the receiving shift register 21 via the bus interface section. The reception shift register 21 operates to serially convert the input serial data into an 8-bit parallel output. Receive shift register 2
The parallel output bit of 1 is the data latches 23a, 23b, 2
8 bits are input in parallel to 4a and 24b, respectively. Here, the data latches 23a and 23b are for latching the code of the valid / invalid designation area V / I in the message, the data latch 23a latches the upper 1 byte thereof, and the data latch 23b latches the lower 1 byte thereof. The data latches 24a and 24b are for latching the data in the data area DT in the message. The data latch 24a latches its upper 1 byte and the data latch 24b latches its lower 1 byte.

Each data latch 23a, 23b, 24a,
24b is an 8-bit parallel output, and the parallel output signals of the data latches 23a and 24a are valid / invalid determination unit 2
5a are separately input to the data latch 23.
The parallel output signals of b and 24b are separately input to the valid / invalid determination unit 25b.

The valid / invalid decision units 25a and 25b have 8-bit parallel outputs, and each output bit has a high level state (logic 1), a low level state (logic 0), and a high impedance like a three-state gate. State (logical 1 is 0
It is possible to take 3 states of (not but) and data latch 2
Only when the valid / invalid code from 3a, 23b is "1", the corresponding output bit of itself is set to "1" according to the data (output bit value from the data latches 24a, 24b) corresponding to the valid / invalid code. When the valid / invalid code is "0", the output bit is set to a high impedance state.

The output signals of each bit from the valid / invalid decision units 25a and 25b are buffer amplifiers 26a ₀ to 26a _0- .
Output port PC through 26a ₆ and 26b _{0 to} 26b ₆
0 to PC7, PD0 to PD7.

The timing generator 22 has latches 23a, 23 based on the system clock and control signals.
It generates timing signals RP0 to RP3 that give data latch timings to b, 24a, and 24b, and generates and outputs port output pulses that give output timing to the valid / invalid determination units 25a and 25b.

The operation of this embodiment circuit will be described below.
Now, on the side of the transmission circuit 1, it is assumed that the auxiliary devices corresponding to the switch SW0 of the group A have changed from OFF to ON. Then, the switch SW0 generates a contact signal only at the time of the change and outputs it to the analog low-pass filter 11a ₀ ,
Pulse converter 1 through digital low-pass filter 12a ₀
3a ₀ , whereby the pulse converter 13a ₀ outputs a pulse having a constant pulse width.

When the output pulse of the pulse converter 13a ₀ is input to the latch 15a, the first bit of the 8-bit data of the latch 15a becomes "1". This is the upper side 1 of the data area DT corresponding to the switch SW0.
This is equivalent to setting the first bit data of the byte to "1" indicating "ON". In this way, the latch 15
Each of a and 15b inverts the content of the bit every time a switching signal is input from the switch SW corresponding to each bit of the held data, thereby turning on / off the auxiliary devices corresponding to each switch SW. It can be displayed depending on the state of each bit of the held data.

When the output pulse of the pulse converter 13a ₀ is input to the latch 14a, the code of the first bit in the 8-bit data of the latch 14a becomes "1".
Since the other bits of the latches 14a and 14b are all "0", the change of the code of the first bit to "1" is caused by the change of the first bit of the latch 15a (that is, the data corresponding to the switch SW0). It indicates that there is a state change in the first bit data of the upper 1 byte of the area DT.

The output pulse of the pulse converter 13a ₀ is input to the transmission controller 18 via the OR gate 17a. Then, the transmission controller 18 starts control for outputting the message to the multiplex bus, and sends a control signal to the timing generator 19, which causes the timing generator 19 to generate and output various signals such as a set pulse.

First, the latches 14a, 14b, 15a, 1
The set pulse SP0 is generated at the timing when the rewriting of the contents of 5b is completed, the contents of the latch 14a are input to the transmission shift register 16, and the set pulse SP4 is generated at the next timing, and the contents of the latch 14a are shifted. The set pulse SP1 is generated from the register 16 as serial data, the set pulse SP1 is generated at the next timing, the content of the latch 14b is input to the transmission shift register 16, and the set pulse SP4 is generated at the next timing as the serial data. The set pulse SP2 is generated at the next timing, the contents of the latch 15a are input to the transmission shift register 16, the set pulse SP4 is generated at the next timing, and the contents are transmitted as serial data. Set pulse SP
3 is generated, the content of the latch 15b is input to the transmission shift register 16, and the set pulse SP is generated at the next timing.
4 is generated and its contents are transmitted as serial data.

As a result, the contents of the valid / invalid area V / I of 2 bytes and the data area DT of 2 bytes in the data field DF in the message are sequentially transmitted in that order, and other codes are multiplexed. Messages are assembled and sent to multiple buses. When the transmission of this message is completed, the timing generator 19 generates the clear signal CLR, which causes the latches 14a, 1
The contents of 4b are all cleared to "0".

On the other hand, on the receiving circuit 2 side, the contents of the data field DF of the received message are the timing signals RP0 to RP generated by the timing generator 22.
3, the upper 1 byte of the valid / invalid designated area V / I is latched in the data latch 23a, the lower 1 byte thereof is latched in the data latch 23b, and the data area D
The upper 1 byte of T is stored in the data latch 24a and the lower 1
The bytes are latched in the data latch 24b.

When the latching of each data is completed, the timing generator 22 outputs a port output pulse. As a result, the valid / invalid determination units 25a and 25b search for a bit in which "1" is set among the parallel output bits (valid / invalid designation bit) of the valid / invalid data latches 23a and 23b,
Of the parallel output bits (data bits) of the data latches 24a and 24b, the corresponding valid / invalid designating bit is "1".
The bit value ("0" or "1") is output to the output port. In addition, the output of the corresponding data bit whose valid / invalid designating bit is "0" is set to a high impedance state, which affects the previous state of the drive circuit of the auxiliary device connected to the output port of the receiving circuit side. Try not to.

With the above-mentioned configuration, on the transmission circuit side, only when there is a change in the status of the auxiliary device or the like, the status change information (information of ON or OFF) of the auxiliary device and the auxiliary device thereof. The valid / invalid designating code indicating that there was a status change is sent as a message, and the receiving circuit side recognizes which auxiliary device has the status change based on the message, and performs appropriate processing accordingly. Can be done.

As described above, according to the present invention, the valid / invalid designation area V / I introduced to cope with the change of the vehicle type and the like is provided.
The code is used as a code for indicating that a state change of the auxiliary device or the like has occurred, and the control is performed.

In the above-mentioned embodiment, all the data in the data area DT of the transmitting side is converted into a message and transmitted, but the present invention is not limited to this, and as will be understood from the principle of the present invention, the data area It is also possible to insert some dummy data into data other than the change data in DT to create a message and send it.

[0041]

As described above, according to the present invention, in the multiplex transmission device, when there is a change in the data content, the hardware circuit immediately detects the change and notifies the other node of the change content. become able to. As a result, the burden on the microprocessor can be reduced, so that a high-performance microprocessor is not required, and the cost can be reduced. Further, since the message creation processing can be transmitted only by hardware processing without spending software processing time, the communication speed can be increased.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a multiple node of a multiplex transmission apparatus as an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a circuit portion related to valid / invalid control of a transmission circuit in a multiplex node of this embodiment.

FIG. 3 is a diagram showing a configuration example of a circuit portion related to enable / disable control of a receiving circuit in the multiplex node of this embodiment.

FIG. 4 is a diagram showing a frame format of a message transmitted and received between nodes of a multiplex transmission device.

FIG. 5 is a diagram showing an example of the overall configuration of a multiplex transmission device.

[Explanation of symbols]

1 transmitter circuit 2 receiver circuit 3 clock generator 4 transmission / reception control unit 5 bus interface unit 11a _{0 to} 11a ₆ , 11b _{0 to} 11b ₆ analog low-pass filter 12a _{0 to} 12a ₆ , 12b _{0 to} 12b ₆ digital low-pass filter 13a ₀ ˜13a ₆ , 13b ₀ ˜13b ₆ Pulse converter 14a, 14b, 15a, 15b Latch 16 Transmission shift register 17a, 17b OR gate 18 Transmission controller 19 Timing generator 21 Shift register 22 Timing generator 23a, 23b Valid / invalid data latches 24a, 24b data latches 25a, 25b enable / disable determination unit buffer amplifier 26a ₀ ~26a _6, 26b ₀ ~26b
₆

Claims (2)

[Claims] 1. A multiplex transmission apparatus for transmitting and receiving a message between nodes, which includes a data area for writing various transmission data and a valid / invalid area for writing valid / invalid information corresponding to each transmission data in the data area. A transmission circuit, which holds data change detecting means for detecting a change in transmission data and valid / invalid information set in the valid / invalid area, and the change in transmission data is detected by the data change detecting means. Sometimes, valid / invalid setting means for making valid / invalid information corresponding to the changed transmission data “valid” indicating that the transmission data has changed, and holding the transmission data to be set in the data area. A data holding means for rewriting the contents of the changed transmission data when the change of the transmission data is detected by the data change detecting means. And a change in the transmission data is detected by the data change detecting means, the transmission data including the changed contents of the transmission data is dealt with based on the contents of the valid / invalid setting means and the data holding means. A transmission circuit of a multiplex transmission device, comprising: a transmission control unit that creates and transmits a message in which the valid / invalid information is "valid". 2. A multiplex transmission apparatus for transmitting and receiving a message between nodes, which includes a data area for writing various transmission data and a valid / invalid area for writing valid / invalid information corresponding to each transmission data in the data area. A receiving circuit, valid / invalid information holding means for holding valid / invalid information of a valid / invalid area in a received message, data holding means for holding transmission data of a data area in a received message, The valid / invalid information of the valid / invalid information holding means and the transmission data of the data holding means are input, and it is determined that the valid / invalid information is “valid” if the content of the corresponding transmission data is changed. Then, a receiving circuit of a multiplex transmission device comprising a valid / invalid judging means for selecting and outputting the transmission data.