JPH0750920B2 - MUSE system sound decoder time base adjustment circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a time axis adjustment circuit installed in a MUSE type sound decoder.

2. Description of the Related Art Currently, the MUSE system is planned as part of a new television broadcasting service using broadcasting satellites.

In this MUSE system, an analog audio signal, which has been conventionally transmitted by an image signal and a frequency division multiplexing system, is digitized and then transmitted by an image signal and a time division multiplexing system.

That is, on the transmitting side, after analog signals are digitized by pulse code modulation, they are time-axis compressed to about 1/16 and transmitted in burst form within the vertical blanking period between video fields, while receiving On the side, the time-axis-compressed burst-shaped digital signal is expanded on the time axis to be converted into a continuous audio signal, and then converted into an analog signal.

Further, in the MUSE system, the image signal is sent out as an FM modulated wave, and the time-axis-compressed digital audio signal is a differential carrier wave (RF carrier) used for FM modulation of the image signal.
It is transmitted as a phase-modulated signal. Therefore, a data pair obtained by differentially modulating a continuous 2-bit voice data pair is called a symbol, and the concept of this symbol is used to MUSE.
The transmission format of the system is specified.

That is, the transmission format of the MUSE system is defined by the line number and the transmission sample number, as shown in FIG.
Each line corresponds to one horizontal scanning period of the image signal, and each transmission sample consists of one symbol.

The first field of image information starting from the 44th line and ending at the 576th line, and the maximum of 112 starting from the 605th line
During the vertical blanking period existing between the second field of the image information which passes through the fifth line and ends with the next fifth line, 37 lines of audio information are transmitted. Further, 38 lines of audio information are transmitted within the vertical blanking period existing between the second field and the next first field of the image information. 480 transmission samples are assigned to one line of each audio information area.

The first and second fields of image information are composed of control signals associated with the image signal, and the audio information area is composed of control signals associated with the audio signal.

The size of the audio information area is alternately set to 37 lines and 38 lines for the purpose of synchronizing all signal systems including video signals. Similarly, from the viewpoint of synchronization, there are two types of transmission formats for each audio information area: a leap field that appears periodically once every 15 fields and a non-leap field that appears 14 times in between. .

Both the non-leap field and the leap field have a configuration in which control signals including a guard signal and an introduction symbol signal are arranged before and after the voice signals of transmission sample numbers 20 to 475 except for the last line.

In the MUSE format transmission format shown in FIG. 3, since the audio information side does not include signals for bit synchronization and frame synchronization, the audio information demodulation system (sound decoder) on the receiving side uses video information and audio information. The video demodulation system receives the timing signal necessary for discriminating the signal on the time axis.

However, in the analog system in which video demodulation is performed and the digital system in which audio demodulation is performed, the timing signal on the video demodulation side cannot be used as it is on the audio demodulation side because there is a considerable difference in signal delay time. It is necessary to adjust the time axis between systems.

This time axis adjustment is usually performed by adjusting the time axis of the audio information so that the sound decoder side synchronizes with the timing signal supplied from the video demodulation side.

Conventionally, in the time axis adjustment on the sound decoder side, the time axis of audio information is adjusted using a variable delay circuit and a buffer memory for time axis adjustment such as a register file.

Problems to be Solved by the Invention In the above-mentioned conventional time axis adjustment method, there is a problem that it takes time and effort to adjust the time axis by the variable delay circuit, and an extra buffer memory for time axis adjustment is required.

Configuration of the Invention Means for Solving the Problems A time axis adjustment circuit of the present invention which solves the problems of the above-mentioned prior art, is a phase demodulation circuit for demodulating four-phase phase of voice information and converting it into a symbol string, and this voice A first time axis adjusting circuit for adjusting the time axis within one symbol period is provided between the symbol array and the time axis expanding circuit for expanding the symbol array on the time axis.

Further, the time base adjustment of the present invention comprises a second time base adjustment circuit capable of changing the write timing to the time base expansion memory in the time base expansion circuit by an integer multiple of the symbol period.

That is, the time axis adjustment circuit of the present invention completes analog time axis adjustment of one symbol period or less at the preceding stage of the time axis expansion circuit, and performs pure digital digital time axis adjustment of an integral multiple of the remaining symbol period. It is configured so as to facilitate the time axis adjustment work in the final adjustment stage by performing it in the time axis expansion circuit as a circuit.

Further, the time-axis adjusting circuit of the present invention is configured so that the buffer memory for the time-axis adjustment is unnecessary by performing the digital time-axis adjustment by adjusting the write timing to the time-axis expansion memory. ing.

Further, the time-axis adjusting circuit of the present invention adjusts the delay amount given to the symbol by the analog first time-axis adjusting circuit over the maximum delay time of a half symbol period or more and one symbol period or less almost continuously. An analog time axis adjustment as a whole by using a cascade connection circuit consisting of an analog variable delay circuit and a digital delay circuit that selectively gives a delay amount of approximately half the symbol period to the symbol. It is configured to be able to perform efficiently in a short time.

Hereinafter, the operation of the present invention will be described in detail with reference to Examples.

Embodiment FIG. 1 is a functional block diagram showing the configuration of a MUSE system sound decoder in which a time axis adjustment circuit of one embodiment of the present invention is installed, together with a video information demodulation system.

The input terminal IN is supplied with a carrier wave modulated by video information and audio information as shown in FIG.
At 20, it is converted to a frequency in the video information band. The video information included in this video information band is converted into various sync signals and analog baseband video signals by the FM demodulator 21, passed through the de-emphasis circuit 22, and then converted into corresponding digital signals by the A / D conversion circuit 23. To be done. The bit synchronization reproduction / frame synchronization detection circuit 24 reproduces the bit synchronization signal from the digital signal supplied to the video signal processing system (not shown) and detects the frame synchronization signal.

On the other hand, the audio information included in the video information frequency band output from the down converter 20 is converted into the audio information frequency band in the down converter 11, and the four-phase phase demodulation circuit 12
At, the sequence of symbols (p ', q') is restored. The audio signal portion of this symbol string is the time axis adjustment circuit 15
After passing through A, the time-axis expansion circuit 16 forms a time-axis expanded symbol (P, Q), and then the differential demodulation circuit 17 restores the parallel bit pair (D1, D2) audio data, and the parallel / serial After being converted into complete serial data (D) by the conversion circuit 18, it is converted into an analog audio signal by the BS-II PCM decoder 19.

Further, the timing control circuit 14, the timing information on the video side from the bit synchronous reproduction / frame period detection circuit 24,
A timing signal to be distributed to each circuit in the sound decoder is created based on the leap field determination result from the leap field determination circuit 13. For the leaf field determination circuit, refer to the specification of a patent application entitled “Leap field signal determination circuit”, which is a separate application of the present applicant.

On the analog video demodulation side, particularly on the de-emphasis circuit 22, a considerably large signal delay occurs, so the timing signals supplied from the bit synchronization reproduction / frame synchronization detection circuit 24 to the timing control circuit 14 on the sound decoder side are four-phase. The timing of the symbols output from the phase demodulation circuit 12 is typically delayed by several symbol periods to ten and several symbol periods.

The time axis adjustment circuit 15A delays the symbols supplied from the four-phase phase demodulation circuit 12 to the time axis expansion circuit 16 within a range of one symbol period or less, thereby the timing control circuit 14A.
Synchronizes the clock signal of the symbol period created based on the timing information of the image system with the phase of the symbol supplied to the time axis expansion circuit. That is, the time axis adjustment circuit
The 15A adjusts the time axis so that the time difference between the symbol and the clock signal is an integral multiple of the symbol period.

The time-axis adjusting circuit 15B delays the write command W'which is supplied from the timing control circuit 14 to the time-axis expanding memory in the time-axis expanding circuit 16 and which has been advanced by a few tens of symbol periods in advance, by an integral multiple of the symbol period. By doing so, the write command signal W in which the output time of the head audio signal of each line and the write start time are matched is supplied to the time axis expansion circuit 16.

As shown in FIG. 2, the time axis adjustment circuit 15A includes a variable delay circuit 1a, a switch 2a, a half clock delay circuit 3a and a switch for synchronizing the time axis compressed symbol p'with a clock signal having the same cycle as the symbol cycle. Variable delay circuit 1b, switch 2b, half-symbol delay circuit for synchronizing the time-compressed symbol q'with the p system consisting of 4a and the clock signal.
3b and q system consisting of switch 4b.

The variable delay write 1a, 1b consists programmable delay line, such as PAD35N, giving a delay amount in the range of 0～35N _sec for the symbols appearing in a cycle of 60n _sec. Further, the half clock delay circuit 3a, 3b consists of the delay flip-flop circuits, such as F174, delaying the clock signal equal to the symbol period only 30n _sec equal to half clock period. The switches 2a and 2b are composed of short pins and the like, and transmit either the delayed signal output from the variable delay circuits 1a and 1b or the non-delayed signal that does not pass through these delay circuits to the subsequent stage. Similarly, the switches 4a and 4b are also composed of short pins and the like, and output either the half clock delay signal output from the half clock delay circuits 3a and 3b or the non-delay signal not passing through these delay circuits.

The synchronization with the clock signal by each variable / selection element is performed by comparing the phase of the monitor signal from the monitor terminal MNT with the phase of the clock signal from the timing control circuit 14 in the final adjustment stage of the sound decoder. .

Similarly, the write command signal W'from the time axis adjustment circuit 15B
And W are adjusted in the final adjustment stage of the sound decoder, using a logic analyzer etc. to detect how many clock cycles the clock signal and the symbol (p, q) of the audio signal are different, and select switch This is performed by opening and closing the group S to correct the amount of deviation. According to the opening / closing of the selection switch group S, the number of cascade connection stages of the built-in delay flip-flop circuit group is changed, and the delay amount of an integral multiple of the clock cycle is inserted / removed.

Although the configuration in which the time axis adjustment circuit 15B is provided by a delay circuit that is separate from the timing control circuit 14 has been illustrated above, a variable timing generator that integrates these may be installed.

EFFECTS OF THE INVENTION As described in detail above, the time axis adjustment circuit of the present invention completes analog time axis adjustment of one symbol period or less in the preceding stage of the time axis expansion circuit, and the number of remaining symbol periods is an integer multiple. Since the digital time axis adjustment is performed in the time axis expansion circuit as a pure digital circuit,
This has the effect of facilitating the time axis adjustment work in the final adjustment stage.

Further, since the time axis adjusting circuit of the present invention is configured to perform the digital time axis adjustment by adjusting the write timing to the time axis expansion memory, the buffer memory for the time axis adjustment is not necessary and the circuit is simple.・ The effect of being cheaper is achieved.

Further, in the time axis adjustment circuit of the present invention, the analog first
The time axis adjustment circuit of (1) is connected in series with an analog part for adjusting the delay amount given to the symbol almost continuously and a digital part for selectively giving the delay amount of about half cycle to the symbol. Because of the configuration, the effect is that the analog time axis adjustment can be efficiently performed in a short time as a whole.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a MUSE system sound decoder in which the time axis adjusting circuit of the present invention is installed together with a video demodulation system, and FIG. 2 is a block showing the configuration of the first time axis adjusting circuit of FIG. FIG. 3 is a transmission format diagram of the MUSE system. 12 …… 4-phase phase demodulation circuit, 14 …… Timing control circuit, 15
A …… first time axis adjustment circuit, 15B …… second time axis adjustment circuit, 16 …… time axis expansion circuit, 24 …… bit synchronization / frame synchronization detection circuit, 1a, 1b …… variable delay circuit, 3a, 3b …… Half clock delay circuit, 4a, 4b …… Switch.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Yoshimichi Otsuka 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside the Japan Broadcasting Corporation Broadcasting Technology Laboratory (72) Inventor Yoshinori Izumi 1-10 Kinuta, Setagaya-ku, Tokyo No. 11 Broadcasting Technology Laboratory of Japan Broadcasting Corporation (72) Inventor Seiichi Koshi 1-10-11 Kinuta, Setagaya-ku, Tokyo Inside Broadcasting Technology Laboratory of Japan Broadcasting Corporation

Claims (1)

[Claims] 1. A first time-axis adjustment provided between a phase demodulation circuit for demodulating four-phase phase of voice information to convert it into a symbol sequence and a time-axis expansion circuit for time-axis extension of this voice symbol sequence. A circuit and a second timing changeable write timing to the time-axis expansion memory in the time-axis expansion circuit by an integer multiple of a symbol period
And a variable delay circuit capable of changing a delay amount given to a symbol over a maximum delay time of a half symbol period or more and a symbol period or less. MUSE characterized by being connected in cascade with a delay circuit capable of selectively providing a delay amount of approximately half the symbol period
Method Time axis adjustment circuit for sound decoder.