JPH0230292A - Sampling clock reproducing circuit - Google Patents

Abstract

PURPOSE:To synchronize the relative phase of a color burst at input and output sides by sampling a color subcarrier and a 1st phase reference signal for each prescribed sample of a transmission line clock and sending the resulting signal. CONSTITUTION:A 1st sampling clock phase-locked to the color subcarrier of an input television signal is generated from a clock generating circuit 3. The 1st sampling clock is inputted to a sampling circuit 6 via a frequency divider circuit 5 and sampled for each prescribed period obtained through the application of frequency division to a transmission line clock by a frequency divider circuit 7. The sampled signal is multiplexed onto coded information of the input television signal from a coder 4 by a multiplex circuit 8 and the resulting signal is sent. The 2nd sampling clock synchronously with the 1st sampling clock is generated at the receiver side by using a phase comparator circuit 14, a sampling circuit 15 and a clock generating circuit 21 or the like.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to the generation of a sampling clock for a device that samples and encodes a television signal and transmits the signal, and particularly relates to the generation of a sampling clock for a device that samples and encodes a television signal and transmits the signal. This relates to a circuit that reproduces on the receiving side.

(Prior art) When encoding and transmitting a color television signal, if sampling is performed using a sampling clock synchronized with the input television signal,
The sampling clock must be recovered on the receiving side. As a method of regenerating the sampling clock on the receiving side, there is a method of synchronizing the frequency so that the number of sampling clocks in a certain period is the same for both the transmitting and receiving side (for example, Japanese Patent Application No. 1982-1).
176 signal "Synchronizer of sampling frequency").

(Problem to be Solved by the Invention) In the conventional approach, only the frequencies of the sampling clock on the transmitting side and the sampling clock on the receiving side are matched, and even the phase relationship of the resampling clock is synchronized. Therefore, in the conventional method, when the television signal is encoded and transmitted (the color burst phase of the television signal reproduced on the receiving side is the phase shift of the sampling clock with respect to the color burst phase of the input television signal on the transmitting side) Therefore, when the coded and transmitted signals are switched and edited to create a television signal, the phase of each color burst fluctuates over time.

In order to synchronize the phase of this color burst, a separate device for phase synchronization such as a frame synchronizer is required.

(Means for Solving the Problems) The sampling clock regeneration circuit of the present invention includes means for generating a first sampling clock that is phase synchronized with the color subcarrier of an input television signal, and means for separating the first sampling clock. means for generating a first phase reference signal synchronized with the phase of the color subcarrier; and means for sampling the first phase reference signal at a constant period determined by dividing the transmission line clock. means for multiplexing the sampled first phase reference signal with information obtained by encoding an input television signal and transmitting the same; means for generating a phase reference signal; and means for sampling the second phase reference signal for each frame period obtained by dividing the frequency of the reproduced transmission line black and y on the receiving side; A phase difference signal representing the phase difference between the sampled first phase reference signal obtained by separating the received signal and the converted second phase reference signal is generated, and the phase difference signal is smoothed. a second sampling clock whose phase is synchronized with the first sampling clock according to the smoothed phase difference signal;
and means for generating a sampling clock.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In this example, an NTSC color television signal is A/D converted at a frequency three times the subcarrier frequency fsc, band compression encoded, transmitted at a bit rate of 45 Mb/s, and decoded on the receiving side. By performing D'/A conversion using a sampling clock synchronized in phase with the sampling clock on the transmitting side, the color burst phase of the reproduced color television signal is phase-synchronized with the color burst of the input television signal on the transmitting side. That's what I do.

The NTSC color TV signal input to input terminal 1 is A.
/D converter 2 and clock generation circuit 3. The clock generation circuit 3 generates a first phase reference signal whose frequency is 3 fsc and which is phase-synchronized with the color burst signal, and whose period corresponds to an integral multiple of the subcarrier. By phase synchronizing, the rising edge of the phase reference signal and the phase of the color subcarrier are synchronized.

The clock generation circuit 9 generates a clock of 44.736 MHz,
sampling a first phase reference signal at the beginning of each frame;
The sample values are multiplexed into predetermined time slots of the DS3 multiframe. In the other time slots, the video signal digitized by the A/D converter 2 is band compression coded by the encoder 4, and multiplexed with other necessary control signals and the like. A bipolar signal of 44.736 Mb/s, which has undergone U/B conversion, is output to the output terminal 10 on the transmitting side.

A bipolar signal input to an input terminal 11 on the receiving side is guided to a separation circuit 12 and a clock recovery circuit 13.

In response to the bipolar signal, the clock regeneration circuit 13 regenerates a 44.736 MHz transmission line clock and supplies it to the separation circuit 12.

After converting the input signal to B/U, the separation circuit 12 converts the DS3 frame to DMPX! , , separates the image data, control data, first phase reference signal, and pulse signal indicating the beginning of the frame of DS3 and supplies them to each section.

Tarock reproducing circuit 21 generates a second sampling clock signal. The sampling circuit 15 samples the second phase reference signal every frame period of DS3 and supplies it to the phase comparison circuit 14.

The phase comparison circuit 14 performs a phase comparison between the sampled first phase reference signal supplied from the separation circuit 12 and the sampled second phase reference signal. This is done by exclusive OR of signals. Phase comparison circuit 1
4 generates a phase comparison signal represented by a binary value of 0 or 1 according to its phase ratio axis, and outputs it to the smoothing circuit 18. The smoothing circuit 18 outputs +1 when the phase comparison signal is 1 and -1 when the phase comparison signal is 0.
The value of 1 is digitally integrated and smoothed for each frame period, the integrated value is D/A converted, and a smoothed phase comparison signal is supplied to the tarock reproduction circuit 21.

The clock regeneration circuit 21 includes a voltage controlled oscillator, and receives the smoothed phase comparison signal from the smoothing circuit 18.
The phase comparison signal is supplied to the voltage controlled oscillator as a control voltage, and a second sampling clock having a frequency corresponding to the control voltage is generated. The phase of the second sampling clock is fed back to the phase comparator circuit 14 via the frequency divider circuit 19 and the sampling circuit 15. fi Eventually, the first phase reference signal and the second phase reference signal become balanced at a point where the average phase difference between the High or Low level sections is 50%. Therefore, the first target signal clock and the second sampling clock are phase synchronized.

The image data separated by the separation circuit 12 is supplied to the decoder 17. The decoder 17 decodes the image data to reproduce a digital NTSC color television signal. D/A
The converter 20 performs D/A conversion on the digital NTSC color television signal, generates an analog television signal, and outputs it to the output terminal 22.

In the embodiment shown in FIG. 1, the color burst signal is sampled in the A/D converter 2 in synchronization with the first sampling clock, and the color burst signal is sampled in synchronization with the first sampling clock in the receiving side D/A converter 20. Since the D/A conversion is performed using the phase-synchronized second sampling clock, the color burst of the television signal input to the input terminal 1 and the color burst of the television signal output to the output terminal 22 are relative to each other. The phase can be synchronized to

(Effects of the Invention) As explained above, the present invention provides color subcarriers and sampling signals for each fixed sample of the transmission line clock.
The first phase reference signal on the transmitting side is sampled and transmitted, and the receiving side compares the phase with the second phase reference signal generated from the recovered clock.
can be synchronized with a second sampling clock at the receiver, resulting in a color burst of the input analog color television signal and a color burst of the reproduced color television signal at the receiver output. The relative phase between can be synchronized. Since the present invention has such effects, by employing the sampling tarlock reproducing circuit of the present invention, there is no need to use a frame synchronizer or the like to suppress phase fluctuations.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Input terminal, 2...A/D converter, 3...Tarlock generation circuit, 4...Encoder, U...Frequency dividing circuit,
6... Sampling circuit, 7... Frequency dividing circuit, 8... Multiplexing circuit, 9... Clock generation circuit, 10... Output terminal, 11... Input terminal, 1? ...-separation circuit, 13.
...Tarlock reproducing circuit, 14...Phase comparison circuit, 15
... Sampling circuit, 17... Decoder, 18... Smoothing circuit, 19... Frequency dividing circuit, 2o... D/A converter,
21... Clock regeneration circuit, 22... Output terminal.

Claims (1)

[Claims] means for generating a first sampling clock that is phase synchronized with the color subcarrier of the input television signal; and means for dividing the first sampling clock to generate a first phase reference signal that is phase synchronized with the color subcarrier. means for sampling the first phase reference signal at regular intervals obtained by dividing the transmission line clock; and means for encoding the input television signal by using the sampled first phase reference signal. means for multiplexing and transmitting the converted information, means for generating a second phase reference signal by dividing the second sampling clock reproduced on the receiving side, and a transmission line clock reproduced on the receiving side. means for sampling the second phase reference signal for each frame period obtained by frequency dividing the sampled first phase reference signal and the sampled second phase reference signal obtained by separating the received signal; means for generating a phase difference signal representing a phase difference with a phase reference signal, smoothing and outputting the phase difference signal; and means for phase synchronizing with a first sampling clock according to the smoothed phase difference signal. and means for generating a second sampling clock.