JPH0744580B2 - Data length conversion circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data length conversion circuit, and more particularly to a data length conversion circuit for converting a cell length in ATM.

[0002]

2. Description of the Related Art There is an ATM (Asynchronous Transfer Mode) as a transfer method for realizing a broadband ISDN. ATM is a communication mode in which communication information is divided into bit strings (cells) of fixed length, and the header at the beginning of each cell is attached with address information indicating its destination, etc., and the length of the cell is recommended by CCITT. Is 53 bytes. However, since the operation speed is high and 53 is a prime number, handling the data in units of 53 bytes makes the circuit configuration difficult. Therefore, a data length conversion circuit that converts the 53-byte cell length conforming to the CCITT recommendation into a 54-byte cell length is required to reduce the burden on the circuit configuration.

FIG. 6 is a block diagram of a conventional data length conversion circuit for converting the cell length. Reference numeral 12 is a write control unit that writes input data from an input side circuit (not shown) that handles cell length data of 53 bytes into a FIFO register, which will be described later, and 13 is a FIFO that stores the data output from the write control unit 12 in a first-in first-out system A register 14 is a read control unit that reads data from the FIFO register 13, converts the data length to 54 bytes in accordance with an output side circuit (not shown) that handles data having a cell length of 54 bytes, and outputs the read data. Also, EC, E
D and EF are from the input side circuit to the write control unit 12 respectively.
The input side clock signal, which indicates the cell length of the input data ED, the input data and the input data ED, WD is the write data output from the write control unit 12 to the FIFO register 13, and RD is the read control unit from the FIFO register 13. Read data, OC, OF output to 14
Are output-side clocks input from the output-side circuit to the read control unit 14, output-side frame signals indicating the cell length of the output data, and OD is output data output from the read control unit 14.

Next, the operation of such a data length conversion circuit will be described. When the input side clock EC, the input side frame signal EF, and the input data ED having a cell length of 53 bytes are input from the input side circuit, the write control unit 12 performs control for writing data in the FIFO register 13, Write data WD is output. Therefore, F
Write data WD is stored in the IFO register 13. Next, when the output side clock OC and the output side frame signal OF are input from the output side circuit, the read control unit 14 performs control for reading out data from the FIFO register 13. Therefore, the read data RD is output from the FIFO register 13. Then, the read control unit 14 converts the read data RD into output data OD having a cell length of 54 bytes and outputs the output data OD.

By providing the FIFO register 13 in the middle in this way, the cell length is converted from 53 bytes to 54 bytes, conversely from 54 bytes to 53 bytes, or from the speed of the input side clock EC to the output side clock. The speed conversion to the speed of OC and the like can be performed while the input side clock EC and the output side clock OC remain asynchronous. Further, at this time, the input data ED input to the write control unit 12
The cell length of the output data OD input to the read control unit 14 is fixed to 53 bytes or 54 bytes in advance, and each circuit of the data length conversion circuit is designed according to these cell lengths. .

[0006]

Since the conventional data length conversion circuit is constructed as described above, the cell lengths of the input data and the output data are fixed in advance, and it is necessary to consider what the cell length is. There was a problem that each circuit had to be designed. In order to solve the above problems, it is an object of the present invention to provide a data length conversion circuit that can easily convert the cell length without redesigning it according to the cell length of input data and output data.

[0007]

The present invention outputs first parallel data obtained by serial-parallel converting input data, and detects the data length of input data based on an input clock and an input frame signal. Then, when the detection signal is output from the serial-parallel converter that outputs the detection signal when the first data length is reached, fixed data is added as the final data of the first parallel data when the detection signal is output from the serial-parallel conversion unit. After that, the first parallel data is converted into write data, and when the detection signal is not output, the write control unit that converts the first parallel data into write data as it is, and the write data output from the write control unit FIFO register to be stored and data is read from the FIFO register and converted into second parallel data And the data length of the output data to be output is detected based on the output side clock and the output side frame signal, and when this data length is the first data length, the end of the second parallel data is detected. A parallel-serial conversion unit that performs parallel-serial conversion in the form of deleting data and outputs it as output data. When the second data length is reached, the second parallel data is directly parallel-serial converted and output as output data. Is to have.

[0008]

According to the present invention, when the input side clock, the input side frame signal, and the input data are input from the input side circuit, the input data is serial-parallel converted into the first parallel signal. The data is output, and the data length of the input data is detected. When the data length is the first data length, the detection signal is output. When the detection signal is output, fixed data is added as the final data of the first parallel data by the write control unit, and then the first parallel data is added.
When the parallel data is converted into the write data and the detection signal is not output, the first parallel data is converted into the write data as it is. Next, the data written in the FIFO register is read by the read control unit and converted into second parallel data. Then, the parallel-serial conversion unit detects the data length of the output data based on the output side clock and the output side frame signal from the output side circuit. When the data length is the first data length, the second length is detected. The final data of the parallel data is deleted so that it is parallel-serial converted and output as output data. When the second data length is reached, the second parallel data is directly parallel-serial converted and output as output data. .

[0009]

1 is a block diagram of a data length conversion circuit according to an embodiment of the present invention. Reference numeral 1 denotes a serial-parallel conversion unit, which inputs an input side clock E from an input side circuit (not shown).
When C, the input-side frame signal EF, and the input data ED are input, the first parallel clock, the first parallel frame signal, and the input data ED are output as serial-parallel converted first parallel data. With
When the cell length of the input data ED is 53 bytes which is the first data length, the detection signal is output. 2 is this serial-
When the detection signal is input from the parallel conversion unit 1, the first
The write controller 3 converts the final byte of the parallel data of the 54th byte into fixed data, converts the first parallel data into write data, and outputs the write data. The write controller 3 outputs the write data output from the write controller 2. The FIFO register 4 which stores data in the first-in first-out system receives the second parallel clock and the second parallel frame signal from the parallel-serial conversion unit, which will be described later, and receives the FIFO register.
The read control unit reads read data from the O register 3, converts the read data into second parallel data, and outputs the second parallel data.

Reference numeral 5 denotes a parallel-serial converter which outputs a second parallel clock and a second parallel frame signal when the output side clock OC and the output side frame signal OF are input from an output side circuit (not shown). The second parallel data output from the read control unit 4 is parallel-serial converted and output as output data OD. SC, SD, and SF are the first parallel clocks output from the serial-parallel converter 1, respectively.
First parallel data, first parallel frame signal,
S is the detection signal, PC and PF are the second parallel clock output from the parallel-serial conversion unit 5, the second parallel frame signal, and PD is the second parallel data output from the read control unit 4. .

Next, the operation of such a data length conversion circuit will be described. First, the input data ED is the write data W.
The operation on the input side which is converted to D and written in the FIFO register 3 will be described. FIG. 2 shows the input data E in the serial-parallel converter 1 in order to explain the operation on the input side.
FIG. 3 is a diagram showing the operation timing when the cell length of D is 53 bytes which is the first data length, and FIG.
Is a diagram showing the operation timing when the cell length is 54 bytes which is the second data length, and each number in the figure indicates the number of bytes starting from the first byte of one cell between the input side frame signals EF. ing.

As shown in FIGS. 2 and 3, when the input side clock EC, the input side frame signal EF, and the input data ED are input from the input side circuit, the serial-parallel converter 1 outputs the input side clock EC. For example, the first for 3 clocks
Parallel clock SC and input data ED are serial-
A first parallel frame signal SF indicating a single frame of the first parallel data SD, which is parallel-converted parallel data of, for example, 3 bytes, and a first parallel data SD corresponding to a single cell of the input data ED. Output.

The serial-parallel converter 1 detects the cell length of the input data ED by counting the input clock EC between the input frame signals EF. When 53 bytes are detected, the detection signal S is output as shown in FIG. 2, and when 54 bytes are detected, the detection signal S is output as shown in FIG.
The detection signal S is not output like the above. At this time, if the cell length of the input data ED is 53 bytes, uncertain data (-in FIG. 2) is contained at the 54th byte.

Next, the write controller 2 is provided with a serial-
The first parallel clock SC, the first parallel frame signal SF, and the first parallel data SD are input from the parallel conversion unit 1. Further, when the detection signal S is input, that is, when the cell length is 53 bytes, it is 54 which is the final data of the first parallel data SD as described above.
The uncertain data at the byte is converted into fixed data (for example, "0"). When the detection signal S is not input from the serial-parallel conversion unit 1, that is, when the cell length is 54 bytes, 5 of the first parallel data SD is used.
Of course, since the regular data is contained in the 4th byte, it is left as it is.

Then, the write control unit 2 performs control for writing the first parallel data SD into the FIFO register 3, and the first parallel clock SC and the first parallel clock SC.
The parallel frame signal SF is converted into write data WD and output. Therefore, the FIFO register 3
The write data WD is stored in.

Next, the operation of the output side for converting the data stored in the FIFO register 3 into the output data OD and outputting it will be described. FIG. 4 is a diagram showing the operation timing when the cell length of the output data OD in the parallel-serial conversion unit 5 is 53 bytes in order to explain the operation on the output side.
FIG. 5 is a diagram showing the operation timing when the cell length of the output data OD is 54 bytes. 4 and 5, A1 and A2 are second parallel clocks PC, respectively.
Is the final clock of one frame corresponding to one cell of the output data OD.

As shown in FIGS. 4 and 5, when the output-side clock OC and the output-side frame signal OF are input from the output-side circuit, the parallel-serial converter 5 receives, for example, three clocks of the output-side clock OC. The second parallel clock signal PC outputs the second parallel frame signal PF indicating one frame of the second parallel data PD.

At this time, the parallel-serial conversion unit 5
Detects the cell length of the output data OD to be output by counting the output clock OC between the output frame signals OF. When it is detected as 53 bytes, the interval between the final clock A1 of the second parallel clock PC and the next second parallel clock is two clocks of the output side clock OC as shown in FIG. When it is detected as 54 bytes, the output side clock OC is set to 3 clocks between the final clock A2 of the second parallel clock PC and the next second parallel clock as shown in FIG.

Next, when the second parallel clock PC and the second parallel frame signal PF are input from the parallel-serial conversion unit 5, the read control unit 4 receives the FIF.
Control for reading data from the O register 3 is performed.
Therefore, the read data RD is output from the FIFO register 3. Then, the read control unit 4 uses the second parallel clock PC and the second parallel frame signal PF.
Based on the above, the read data RD is converted into the second parallel data PD which is parallel data of 3 bytes, for example, and is output.

Then, the parallel-serial converter 5 is
The second parallel data PD output from the read control unit 4 is parallel-serial converted to output data OD, which is output in synchronization with the output clock OC. At this time, as shown in FIG. 4, when the interval between the final clock A1 of the second parallel clock PC and the next second parallel clock is two clocks of the output side clock OC, that is, the cell length of the output data OD is 53. In the case of bytes, the 54th byte (Fig. 4) which is the final data of the second parallel data PD.
Then, "0") is not output. Further, as shown in FIG. 5, when the period between the final clock A2 of the second parallel clock PC and the next second parallel clock is 3 clocks of the output side clock OC, that is, when the cell length is 54 bytes,
The 54th byte of the second parallel data PD is also converted and output as it is.

Therefore, regardless of whether the cell length of the input data ED and the output data OD is 53 bytes or 54 bytes, the cell length is converted and the speed of the input side clock EC to the speed of the output side clock OC is increased. The conversion can be done easily. In this embodiment, the serial-parallel converter 1 and the parallel-serial converter 5 have the first parallel data SD and the second parallel data PD of 3 bytes, but other numbers of bytes or bits may be used. Can handle.

[0022]

According to the present invention, whether the data length of the input data and the output data is the first data length or the second data length, the data length can be detected and the data length can be converted. Therefore, the data length conversion and the speed conversion can be easily performed without using a special control signal or the like. Further, since the operation speed of the internal circuit can be reduced by providing the serial-parallel converter and the parallel-serial converter, it is possible to reduce the power consumption.

[Brief description of drawings]

FIG. 1 is a block diagram of a data length conversion circuit that is an embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing when the cell length of input data in the serial-parallel conversion unit of FIG. 1 is 53 bytes.

FIG. 3 is a diagram showing an operation timing when a cell length of input data in the serial-parallel conversion unit of FIG. 1 is 54 bytes.

4 is a diagram showing an operation timing when the cell length of output data in the parallel-serial conversion unit of FIG. 1 is 53 bytes.

5 is a diagram showing an operation timing when the cell length of output data in the parallel-serial conversion unit of FIG. 1 is 54 bytes.

FIG. 6 is a block diagram of a conventional data length conversion circuit.

[Explanation of symbols]

 1 serial-parallel conversion unit 2 write control unit 3 FIFO register 4 read control unit 5 parallel-serial conversion unit EC input side clock EF input side frame signal ED input data SD first parallel data S detection signal PD second parallel data OC output side clock OF output side frame signal OD output data

Claims (1)

[Claims] 1. An external input side circuit to an input side clock,
By inputting the input data and the input side frame signal indicating the data length of this input data, and by inputting the output side clock signal indicating the output side clock and the data length to be output from the external output side circuit, Data length conversion for converting input data having a first data length or a second data length longer than the first data length to output data having a first data length or a second data length and outputting the output data to an output side circuit In the circuit, when the input data is the first data length which is obtained by converting the input data to serial-parallel converted first parallel data and detecting the data length of the input data based on the input side clock and the input side frame signal. Is a serial-parallel conversion unit that outputs a detection signal, and when the detection signal is output from the serial-parallel conversion unit, the first parallel A write control unit that converts the first parallel data into write data after adding fixed data as final data of the data, and converts the first parallel data as it is into write data when the detection signal is not output. A FIFO register that stores the write data output from the write control unit; a read control unit that reads the data from the FIFO register and converts the data into second parallel data for output; an output-side clock and an output-side frame; The data length of the output data to be output is detected based on the signal, and when the data length is the first data length, the final data of the second parallel data is deleted by parallel-serial conversion and output data is output. And outputs the second parallel data as it is when the second data length is reached. A data length conversion circuit, comprising: a parallel-serial conversion unit that performs rule-serial conversion and outputs as output data.