JPH0740259B2 - Parallel processor development system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a parallel processing device development system, and in particular, facilitates and speeds up debugging of hardware and software in the development of a data driven type (data flow) processor. The present invention relates to a parallel processing device development system having a development support environment (development support tool).

[Conventional technology]

FIG. 11 is a diagram showing the configuration of a conventional data driven processor development system. In the figure, 90 is a host personal computer, 91 is a timer, 92 is a memory address generator, and 93 is a memory address generator.
Is a data driven processor, 94 is a graphic display controller, 95 is an image memory, 96 is a CRT, 97
Is a system bus and 98 is an image memory bus.

In this configuration, initialization, setting of breakpoints,
It displays dumps, loads, moves settings, inputs, outputs, loads object programs, etc. in each part of memory.

Next, the operation will be described.

Initialization, object loading, memory setting / loading of each part, etc. are performed by writing data from the host personal computer 90 to each part based on commands from the host personal computer 90. On the contrary, the dump display is performed by reading out the data from each unit to the host personal computer 90, and the movement is performed by a combination of these. Input of calculation data can also be performed from the host personal computer 90.

[Problems to be Solved by the Invention]

The conventional parallel processing device development system is configured as described above, and the above processing is performed by the command from the host personal computer. However, the value in the memory can only be displayed during execution or at the end stage. It is not a development support environment that can trace the processing and the result makes it possible to improve the debugging efficiency in the development of the application system using the data driven type processor, and the efficient development of the application system of the data driven type processor. There was a problem that it could not be done.

The present invention has been made to solve the above problems, and a parallel processing device development system having a development support environment capable of efficiently and rapidly debugging hardware and software in application system development of a data driven processor. Aim to get.

[Means for Solving the Problems]

A parallel processing device development system according to the present invention is a dedicated input for inputting processing input data from a control computer to a parallel processing device including a multiprocessor at a high speed corresponding to the processing speed of the actual application of the parallel processing device. A data input unit equipped with a packet memory and a trace unit equipped with a trace memory for tracing the data transfer status of each functional unit of the parallel processing device in a processing execution state together with a time state are provided by the trace unit. The trace result is made into a file and a data flow graph is created and displayed.

[Action]

According to the present invention, the input data for processing is input at high speed by the data input unit equipped with the dedicated input packet memory, and the data in each function of the processor is added by the tracer equipped with the trace memory. Since the transfer status is traced as it is in the execution state, and the trace result is made into a file and is made into a data flow graph, the hardware and software in the development of the parallel processing device can be debugged efficiently and at high speed.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a parallel processing device development system according to an embodiment of the present invention.

In the figure, 1 is a development support environment, 10 is a processing element (PE) including a data driven processor, 20
Is a data-driven processor main unit, 21 is an extended program store (EPS), 22 is an extended data store (EDS), and 23 is an external color / stack processor (External Color / Stack) Proces
s: ECS), 31 is a control computer such as a personal computer, 40 is an interface section, and 60 is a tracer section.

FIG. 2 is a diagram showing the configuration of the processing element 10,
In the figure, 11 is a cache program memory (Cache Prog
ram Store: CPS), 12 is ignition processing (Firing Control: F)
C), 13 is an arithmetic process (Functional Process: FP), 14 is a junction branch function (Junction & Branch: J & B), and 15 is a queue buffer (Queuing Buffer: QB).

FIG. 3 is a diagram showing a packet of the data driven type processor. In the figure, each field has a function as shown in the figure.

FIG. 4 is a block diagram of the interface unit 40, 41 is a conventional (Neumann) microprocessor unit that manages the interface unit 40 and the tracer unit 60, and 42 is a ROM that stores programs and data of the microprocessor unit 41. And RAM, 43 is a serial I / O controller connected to the control computer 31, 44 is an output port for inputting a data packet to the data driven processor of the processing element 10, and 45 is a write for writing data to the input packet memory. Address counter, 46 is a read address counter for reading data from the input packet memory, and 47 is a data packet output port.
A stop address latch for stopping the packet output used when terminating the output from 44, 48a is an input packet memory address multiplexer, 48b is an input packet memory data multiplexer, 49 is an output port output driver, and 50 is Input packet memory of 4k x 64bits,
51 is an address comparator that compares the address of the input packet memory 50 with the contents of the stop address latch 47 when the data packet is input, 52 is a flip-flop for the data packet input state, 53 is a data packet input start trigger generator, and 54 is a data packet The input interval latch stores the packet interval at the time of input, 55 is an input interval counter for measuring the data packet input interval, and 58 is an output control unit for inputting the data packet.

FIG. 5 is a block diagram of the tracer unit 60. In FIG.
Is a trace port, 62 is a timer, 63 is an input latch, 64 is a synchronizing circuit, 65 is a demultiplexer, 66 is a mode controller, 67 is an address counter, 68 is a 4k × 96bit trace memory, and 69 is a read / write controller. , 70 is a break point latch, 71 is a comparator, and 72 is a break point address latch.

Next, the operation of this embodiment will be described.

The data driven processor 10 has CPS11, FC12 and FP13 as basic elements, and J & B14 and QB15 are combined to form a cyclic pipeline as shown in FIG. EPS21 is a functional unit that stores an external expansion program of CPS11, EDS22 is a functional unit that stores array data, etc., ECS23 is a functional unit for color management and external queue.

An input packet having a format as shown in FIG.
It is input to CPS11 via the confluence part of & B14. CPS11 is EPS
With 21 as the trigger, the next destination of the packet that has passed FC12 is used as a trigger to fetch the next required program data from EPS and store it in CPS11. In the case of the unary operation, it is output as it is, and in the case of the binary operation, the operand pair is formed and then output from the FC12. This operation packet is sent to the FP13 and operated by the instruction code (OPC: Operation Code), and it is judged whether or not it is output by the branch function of the J & B14. repeat.

Assuming that the program is executed from a young node number excluding the loop, the matching memory of FC12 is hashed, and when a hash collision occurs in the matching memory, the one with a small generation and the one with a small node number are saved. And then the other ones
It is possible to send the data to the ECS23, execute the processing in order from the highest priority, and execute the processing without overflowing the cyclic pipeline in the chip.

Further, between the CPS11 and FC12, there are two data paths in the other part of the cyclic pipeline, and the data transfer path has no overflow even during COPY processing in CPS11.

The operation of the development support environment 1 is controlled by the control computer 31. The hardware is interface 40
Also, the tracer unit 60 is included, and the minimum structure is six. Among them, the processing element 10 including the data driven processor is composed of four data driven processor main body 20, extended processor storage unit EPS21, extended data storage unit EDS22, and external color stack processing unit ECS23.

A control computer 31 controls the entire development support environment 1. Data is input and collected by the development support environment control program of the control computer 31. The processing functions of the control program are shown below.

Loading mode Loading of program data, loading of input data packets, setting of the number of input data packets, loading of input data packets, loading of dump packets.

Collection mode Setting the breakpoint comparison value, setting the breakpoint mask value, starting the tracer to start the trace, presetting the trace address counter, writing to the trace memory file, and reading the breakpoint occurrence address.

Memory dump for each PE # of processing element 10
The start address and end address are specified for EDS21, FC12, EPS21, and dump packets output from the respective memories are collected by the tracer. In addition, initialization, waiting for a predetermined time, and returning from the control program can be performed.

4 and 5 are functional block diagrams of the interface unit and the trace unit, respectively. Data transfer between the control computer 31 and the development support environment 1 including a data driven processor is performed via the interface unit 40.

The operation of both functional units will be described in detail below. Interface part
40 has a serial port 43 and is connected to the control computer 31. The MPU 41 executes the functions of the input mode and the collection mode described above by the command from the serial port 43. The interface unit 40 waits for a command from the control computer after initializing the entire development support environment 1 at the same time as supplying power. To load programs and data,
This is performed by collectively writing the tag area and 32 bits of data as shown in FIG. 3 per packet into 2 words of the input packet memory 50 and outputting from the output port 44 for each packet. Since it is indispensable to input the input data packet at high speed, the input packet memory 50
Is used. The input packet memory 50 is loaded up to 4k words using the write address counter 45, and information corresponding to the number of input data packets is set in the stop address latch 47, and then the read address counter 46 is input by the input command specifying the input interval. Stops address latch 47
Input all at once until it matches the value set in.

Further, the address / data bus of the interface unit 40 is connected to the tracer unit 60, and the tracer unit 60 is also controlled.

The tracer unit 60 has a 4k × 96bit trace memory 68,
The trace can be made by connecting to any terminal of the processing element 10. The tracer unit 60 is connected to the address / data bus of the interface unit 40,
It is directly controlled by the interface unit 40. If necessary, it is possible to set the comparison value of the breakpoint and the mask data. After setting the tracer number and the trace mode, the interface unit 40 gives an instruction to start the trace. After that, the tracer unit 60 is connected to the trace port 61.
The data packet coming in from is latched in synchronization with the internal clock and stored in the trace memory 68 together with the time information. When a break point is set in the break point latch 70, it stops after detecting a matched packet in the output of the comparator 71, but when it stops, it stops immediately, after a trace of half the memory capacity, and stops. Three trace modes can be selected: stop after trace of capacity and trace history is effectively stored.

After the end of the trace, the breakpoint occurrence address can be read from the breakpoint address latch 72, and valid data can be determined from the trace mode and the value of the address counter 67.

The trace result in the trace memory 68 can be dumped and made into a file by the interface unit 40, and this file can be displayed in a list.

Multiple trace units 60 can be connected and one interface unit 40
It is possible to measure 15 at the same time by using 15 trace units 60 per hit. It is possible to trace the operation packet and the result packet at the connection point with the functional unit and capture the operation of the entire system together with the trace time information stored at the same time.

In this embodiment, it is possible to display the data of each part of the processing element 10 collected by the tracer part 60. FIG. 6 is a diagram showing an example of how the trace result is displayed. FIG. 6 (a) shows the FP13 output display, and FIG. 6 (b) shows the ECS23 output display.

The data-driven processor is being developed together with the language processing system, but the compiler output format file of the language processing system,
For the object code that is the mapper output and the execution trace result, a tool is provided to graphically express and modify the program. This makes it possible to graphically display the object code and execution trace result for each processor even in a multiprocessor execution environment. By comparing these, an unprocessed node, an unentered data packet, an unaccessed memory, etc. can be found very easily, and debugging of a multiprocessor is easy. The maximum parallelism at execution, average parallelism, number of execution ranks, execution time, etc. can be displayed together with time information, and the operating rate can be easily evaluated as well as the simulator execution result.

In this display, for example, the result of rank analysis required for assigning node numbers in the data exchange method described in Japanese Patent Application No. 62-54406 “Associative memory and data driven computer” is used, and arcs are also overlapped. We have improved the visibility by introducing an algorithm to reduce.

The graphical display of the compiler output format file can be performed on a function-by-function basis, and is generally easier to see than the graphical display of the mapper output (object code) in which a plurality of functions are expanded.

FIG. 7 is a diagram showing a graphic display example of a mapper output of a data flow graph of a third-order polynomial calculation program, and FIG. 8 is a diagram showing a display example of trace results.

As described above, in this embodiment, the data packet for processing execution from the control computer 31 is rapidly input to the processing element 10 of the parallel processing device via the interface unit 40 having the input packet memory 50, and the processing element is also added. The tracer unit 60 having the trace memory 68, which has the trace ports connected to the 10 pins, traces the data packet entering the trace port together with the common time information in synchronization with the internal clock of the system. In addition, since the trace results stored in the trace memory of the plurality of tracer units 60 are collected and made into a file and displayed as a data flow graph, it is possible to debug the hardware or software in the development of the parallel processing device. Extremely easy,
Can be speeded up.

Although the above embodiment has been described as a development support environment for a data-driven processor, it can be implemented in other parallel processing computers or processors in a similar manner.

Further, in the embodiment of FIG. 1, the processor element
Although the connection method of 10 is not particularly specified, various other things such as a shuffle net connection as shown in FIG. 9 and a daisy chain connection as shown in FIG. 10 are possible.

〔The invention's effect〕

As described above, according to the present invention, while inputting the processing input data from the control computer to the processor at a high speed corresponding to the processing speed of the actual application through the data input unit equipped with the dedicated input packet memory, The tracer unit equipped with the trace memory traces the data transfer status in each functional unit of the processor along with the time information in the execution state, and the trace result is filed and displayed as a data flow graph for parallel processing. This has the effect of enabling efficient and high-speed debugging of hardware and software in device development.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a parallel processing device development system according to an embodiment of the present invention, FIG. 2 is a diagram showing a configuration of processing elements, FIG. 3 is a diagram showing packets of a data driven processor, and FIG. Fig. 5 is a block diagram of the interface unit, Fig. 5 is a block diagram of the tracer unit, Fig. 6 is a diagram showing an example of trace results, and Fig. 7 is a diagram showing a graphic display example of mapper output which is a data flow graph. FIG. 8 is a diagram showing a display example of trace results, FIG. 9 is a diagram showing a shuffle net connection of a data driven processor, FIG. 10 is a diagram showing a daisy chain connection of a data driven processor, and FIG. 11 is a conventional diagram. It is a figure which shows the structure of a parallel processing apparatus development system. 1 is a development support environment, 10 is a processing element consisting of a data driven processor, 20 is a data driven processor main body, 40 is an interface section, and 60 is a tracer section. The same reference numerals in the drawings indicate the same or corresponding parts.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kenji Shima, 8-1-1 Tsukaguchihonmachi, Amagasaki City, Hyogo Prefecture Sanryo Electric Co., Ltd. Industrial Systems Research Institute (72) Inventor Takeshi Fukuhara 8-chome, Tsukaguchihonmachi, Amagasaki City, Hyogo Prefecture No. 1-1 Sanryo Electric Co., Ltd. Industrial Systems Research Laboratory (72) Inventor Nobufumi Komori 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSE Research Laboratory (56) References 2-14333 (JP, A)

Claims (1)

[Claims] 1. A parallel processing device comprising a single or a plurality of multiprocessors, a control computer for driving the parallel processing device, and a memory means for storing a plurality of packets for executing processing from the control computer. A data packet input section having a measuring means for inputting the packets stored in the memory means to the multiprocessor of the parallel processing device at settable input intervals, and a plurality of functional sections of the multiprocessor. And a tracer unit having an internal trace memory connected to an input / output port and a data transfer port provided at the port, and the data packet of the port is taken in and stored in synchronization with an internal clock together with common time information. Data that is provided and that is the result of processing execution captured in the trace memory of the tracer unit The ability to display the packet to the processing order,
And a parallel processing device development system having a function of comparing this with an execution program.