JPH06309285A - Communication processing circuit for parallel computer - Google Patents

Abstract

PURPOSE:To reduce the overhead of a processor element accompanied with an inter-processor element communication processing by providing a specific communication processing part, and selectively executing a prescribed communication processing independently of an operation at a calculation processing part. CONSTITUTION:This circuit is constituted of a calculation processing part 10 and a communication processing part 11. Then, the communication processing part 11 is equipped with registers 110-113 which store logic address (1) of a processor element 1, number (2) of entire processors, logical data (5) and (6), and communication data (3) communicated from a communication network 3, buffers 116-117, each kind of arithmetic unit 114 and 115, control sequencer 118 which operates communication control, and communication network interface 119, as a hardware mechanism used exclusively for a global processing. Then, after the circuit is activated by a software instruction executed by the calculation processing part 10, the global communication processing is executed by the hardware mechanism independently of the calculation processing part 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication processing method in a parallel computer provided with a distributed memory, and more particularly to a plurality of all processor elements (P
E1, ...) It relates to the communication processing circuit when performing global processing by referring to the data above.

When designing in all industrial fields and technical development fields, partial differential equations are solved, structures are analyzed, and numerical simulation is performed without experiments.
It is becoming important to predict the characteristics and performance of products. Moreover, this numerical simulation requires a faster computer every year, and the use of parallel computers with a large number of central processing units (CPUs) is being considered as a means of responding to the increasing demand for computational power. It is beginning to be done.

When parallel processing of such a numerical simulation is performed on a distributed memory type parallel computer, an array for data is sent from the host to each processor element (PE1, P1
The data is updated by dividing it into E2, ~).

The communication processing required for such parallel processing is
Local processing that receives a copy of the data to be referenced from the processor elements (PE1, PE2, ...) that have data within the interaction range on the numerical model, and the data on all processor elements (PE1, PE2, ...) There is a global process in which the calculation is performed by referring to.

In such global processing, if the number of processor elements (PE1, PE2, ...) Increases,
Although the processing time becomes long, the communication processing time included in the processing time cannot be ignored, and in the global processing, after receiving data from another processor element and performing a predetermined calculation, another processing is performed. Despite the processing such as sending to the processor element, each time data is received, an interrupt occurs in software (that is, application) in the processor element,
Since the application is disturbed and the processing capacity of the parallel computer as a whole is lowered, a communication processing circuit which has little influence on the application executed in the processor element is required.

[0006]

2. Description of the Related Art FIG. 3 is a diagram for explaining a conventional communication processing method in a parallel computer, FIG. 3 (a) shows a configuration example of a memory distributed parallel computer, and FIG. 3 (b) shows a processor. The format example of the data transmitted / received between elements is shown.

First, in the data format shown in FIG. 3 (b), the header section at the head is the address (SA) of the processor element (PE1, ...) 1 of the communication destination and the processor element (PE1, PE1 of the communication destination). ~) Interrupt for 1 (IN
It is composed of control information such as the presence / absence of T) and the class of data (a class for identifying whether or not the data needs to be preferentially processed by the application).

When an application of the processor element (PEn) 1 on the transmission side, for example, a communication library sends data to the processor element (PE1) 1, after preparing predetermined data on the main storage device 12, By instructing a predetermined condition, for example, the direct memory access mechanism (DMA) 110 in the communication processing unit 11 is activated.

The direct memory access mechanism (DMA) 11
0 is the processor element (P
Data of a predetermined data length is read from a predetermined address of the main memory device 12 of En) 1 and transferred to the processor element (PE1) 1 via the communication network 3.

The communication processing section 11 of the processor element (PE1) 1 refers to the header section of the transmitted communication data, determines that the data is the transmission data for its own processor element (PE1) 1, and the interrupt flag ( When INT) is “1”, it interrupts the operating system (OS) executed in the main unit (calculation processing unit) 10.

When the operating system (OS) executed by the main body unit 10 accepts the interrupt, the header unit of the communication data is fetched, the communication destination is checked, and then the data length is referred to to directly Invokes the Memory Access Facility (DMA) 110.

Direct memory access mechanism activated
The (DMA) 110 reads the data portion of the communication data from the communication network 3 and transfers it to the main storage device 12 under the instructed data transfer condition.

As described above, in the conventional communication processing, every time data is transferred from a predetermined processor element (PEi) 1, the main body of the processor element (PEj) 1 of the communication destination is transmitted.
The operation system (OS) executed in 10 is interrupted, and at least an operation of transferring communication data from the communication processing unit 11 to the main body unit 10 is executed in order to read the header part.

[0014]

Therefore, since the throughput of the communication processing is much slower than the memory access to the main memory 12 in the current parallel computer, the parallel processing can be obtained as much as possible. It is necessary to devise to shorten the time of communication processing and processing related to communication.

The following is an example of global processing that requires communication when parallel processing of the numerical simulation is performed. a) Maximum / minimum value search (size comparison) b) Global logical operation (logical sum, exclusive OR, etc.) c) Total calculation (floating point, addition of integer) d) All data divided into processing elements Sharing (joint) of these complex communication processing is performed by the processor element (P
In Ei) 1, when the message passing (message passing) mechanism as described above, for example, the direct memory access mechanism (DMA) 110, the interrupt mechanism, etc. is performed, the software that activates the communication and the communication data For example, a lot of time is spent on the processing in the processor element (PEi) 1 related to receiving and sending the header part.

In the global processing as described above, the message passing (data transfer) is performed even though the received data is subjected to one operation and then immediately again sent to the communication network 3. ) Is a communication software
It is easy to suffer from overhead such as duplication of processes such as communication destination check in the (communication library) and movement of data between the main unit 10 and the communication processing unit 11. Moreover, in the most effective binary tree algorithm in these global processes (see FIG. 2 described later), it is not all the processor elements (PEi) 1 that require arithmetic processing, but some processor elements. For this reason, in the numerical simulation in which these processes are frequently performed, the other processor elements (PEj) that do not perform the calculation process wait and the operating rate is reduced, and the effect of parallel processing is difficult to be obtained.

In view of the above-mentioned conventional drawbacks, the present invention is necessary for parallel processing such as numerical simulation performed by a parallel computer, but it is possible to perform composite communication processing at a high speed, which reduces the parallel processing effect of numerical simulation. It is intended to provide a communication processing method.

[0018]

FIG. 1 is a diagram schematically showing an embodiment of the present invention, and FIG. 2 is a diagram for explaining global processing by a binary tree. The above problems can be solved by the communication processing method in the parallel computer configured as follows.

(1) A communication processing circuit in a processor element 1 in a parallel computer in which a plurality of processor elements 1 each having a distributed memory (main memory) 12 are connected via a communication network 3. In each processor element 1, apart from the calculation processing unit 10, the logical address of the processor element, the number of all the processor elements, the local data from the calculation processing unit 10, and the communication data received from the communication network 3 are stored. Is provided with a communication processing unit 11 including registers 110, 111, 112, 120, 113, buffers 116, 117 for storing the data, various arithmetic units 114, 115, a control sequencer 118 for communication control, and a communication network interface 119.
After the logical addresses of the processor elements and the number of processor elements are set in the registers 110 and 111 by the instruction from the software executed by the calculation processing unit 10, the set logical address, the number of processor elements, and the A communication process (data transmission, data reception, calculation,
Alternatively, the calculation result is transmitted) selectively
Configured to run independently of the behavior in 10.

(2) As the above communication processing, a global tree procedure is used to perform a global operation.

[0021]

As described above, as an example of global processing that requires communication between processor elements (PEi), which is necessary for parallel processing of a numerical simulation in a distributed memory parallel computer, Maximum / minimum value search (comparison of magnitude), b) Global logical operation (logical sum, exclusive logical sum, etc.)
, C) total sum calculation (floating point, integer addition), d) congruence of data strings (joining), etc., but the binary tree algorithm shown in Fig. 2 is the most effective communication method in this global processing. It has been known.

As is clear from FIG. 2, in the binary tree communication processing, the configuration of the binary tree is determined by the number of processor elements (PE1, PE2, ...) That constitute the parallel computer. In the configuration example of
For example, odd-numbered processor elements (PE1, PE3, PE
5, ~) 1 receives communication data from the communication network 3 and executes a predetermined calculation process (indicated by OPR), or further
Alternatively, two or four younger processor elements (P
Ej) It is formalized to transfer to 1, and which communication process is performed is determined by the number of communication in the above binary tree.

For example, the processor element (PE1) 1
Only receives the data and repeats the predetermined calculation. However, in the processor element (PE3, PE7, ...) 1, the calculation processing is performed in the first communication processing, and the calculation result is stored in another processor element. (PE1) only send to 1,
In the processor element (PE5, ...) 1, only the arithmetic processing is performed in the first communication processing, and in the second communication processing, the calculation result is stored in another processor element (PE1) 1.
To the processor element (PE
The contents of the communication process are formalized by the processor element address (number) of i) and the number of times of the communication process (this is determined by the control sequencer number).

In addition, even-numbered processor elements (PE
2, PE4, 〜) 1 has its own data (that is,
(Data distributed from the host, local data)
To the other processor elements (PE1, PE3, ...) 1 only.

Focusing on this point, the present invention, in addition to the calculation processing section 10 which is the main body, in each processor element 1, the logical address of the processor element, the number of all the processor elements, and its own. Register 110,111,112,120,11 that stores the local data that is being stored and the communication data that is received from the communication network 3.
3, a buffer 116, 117, various computing units 114, 115, a control sequencer 118 for communication control, and a communication processing unit 1 (119)
1 is provided, and the logical address of the processor element and the number of processor elements are set in the registers 110 and 111 by the instruction from the software executed in the calculation processing unit 10, and then the set logical address and the number of processor elements are set. , The communication process (data transmission, data reception, calculation, or calculation result transmission) that is determined by the sequence number of the control sequencer 118 instructing the number of times of communication is selectively performed. The calculation processing unit 10 is configured to be executed independently of the operation.

Therefore, it is possible to reduce the overhead caused by executing communication software for general-purpose message passing (message passing) a large number of times as in the conventional art, and to simplify the binary tree algorithm which is a fixed process. By executing with the hardware mechanism, arithmetic processing can be executed without competing with memory access and input / output processing in the calculation processing unit which is the main body of the processor element (PEi), and communication data of the communication network can be executed. Since it is not necessary to move to the calculation processing unit of each processor element (PEi), the communication processing can be speeded up. As a result, it is possible to shorten the time required for the composite communication process and improve the operating rate of all processor elements (PEi).

[0027]

Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 described above is a diagram schematically showing an embodiment of the present invention, and FIG. 2 is a diagram explaining global processing by a binary tree.

According to the present invention, in each processor element 1, a logical address of the processor element, the number of all processor elements, local data, and a communication network are received in addition to the calculation processing section 10 which is the main body. The communication processing unit 11 including a register 110, 111, 112, 120, 113, a buffer 116, 117 for storing the communication data, a variety of arithmetic units 114, 115, a control sequencer 118 for communication control, and a communication network interface (119) is provided to perform the calculation process. The above register 11 is specified by the instruction from the software executed in part 10.
After setting the logical address of the processor element and the number of processor elements to 0, 111, the set logical address, the number of processor elements, and the sequence number of the control sequencer 118 instructing the number of times of communication are set. Means for selectively executing the communication process (data transmission, or data reception, calculation, or calculation result transmission) determined independently of the operation of the calculation processing unit 10 according to the present invention. It is a necessary means to do. The same reference numerals indicate the same objects throughout the drawings.

The configuration and operation of the communication processing circuit in the distributed memory type parallel computer of the present invention will be described below with reference to FIGS. As shown in FIG. 1, the processor elements (PE1, PE2, ...) 1 of the distributed memory parallel computer are composed of a calculation processing unit 10 and a communication processing unit 11, and the communication processing unit 11 performs global processing. As a dedicated hardware mechanism for performing the logical address of the processor element,
Number of all processor elements and local data,
And registers 110,111,112,120,113 for storing communication data received from the communication network 3 and buffer 1
16, 117, various arithmetic units 114, 115, a control sequencer 118 for communication control, and a communication network interface 119 are provided, and after being activated by software instructions executed by the calculation processing unit 10, all calculations are performed by hardware. Independent of the processing unit 10, global communication processing is executed by the hardware mechanisms 1 and 2 described below.

"Hardware mechanism 1": A register (R1) 110 for setting a logical address of a processor element and a formalization of communication processing by a binary tree as a mechanism for determining a communication destination by a binary tree and controlling transmission / reception. A register (R2) 111 for setting the number of all processor elements involved and a register (R2) for storing the data on the main memory 12, that is, local data.
3) 112, a buffer (BUF) 116, a register (R5) 120 for storing the data length of local data, and a register for storing communication data from the communication network 3
(R3) 113, the buffer (BUF) 117, and the current communication process is the number of times of the communication process in the binary tree, that is, the sequence number is instructed, and a predetermined control signal is given. A control sequencer 118 for outputting the signal is provided in the communication processing unit 11.

The control sequencer 118 is a register
The communication processing is controlled based on the processor element address in (R1) 110 and the number of all processor elements set in the register (R2) 111.

FIG. 2 shows a method of determining a communication destination by using a binary tree. As is clear from FIG. 2, in the communication processing by the binary tree, for example, the odd-numbered processor elements (PE1, PE3, PE5, ...) 1 receive the communication data from the communication network 3 and are determined in advance. Whether or not to execute the operation processing (indicated by OPR) that is present or to transfer the executed operation result to one, two, or four younger processor elements (PEj) 1. The communication process to be performed is determined by the number of communication in the binary tree, that is, the sequence number.

For example, the processor element (PE1) 1
Only receives the data and repeats the predetermined calculation. However, in the processor element (PE3, PE7, ...) 1, the calculation processing is performed in the first communication processing, and the calculation result is stored in another processor element. (PE1) only send to 1,
In the processor element (PE5, ...) 1, only the arithmetic processing is performed in the first communication processing, and in the second communication processing, the calculation result is stored in another processor element (PE1) 1.
To the processor element (PE
The contents of the communication process are formalized by the processor element address (number) of i) and the sequence number indicating the number of times of the communication process.

Further, even-numbered processor elements (PE
2, PE4, 〜) 1 has its own data (that is,
It only sends the local data distributed from the host) to the other processor elements (PE1, PE3, ...) 1.

Therefore, in the present invention, the above register
(R1) The own processor element address (processor element number) set to 110 and the register
(R2) The number of all processor elements that determine the overall configuration of the binary tree set in 111 and the control sequencer that indicates the number of times of the communication processing in the binary tree communication processing 118
The sequence number and the sequence number determine the type of communication processing to be performed by itself.

"Hardware mechanism 2": A floating point adder (FLOA) which operates under the control of the above hardware mechanism 1.
T) 114, integer adder (INT) 115, or the above-mentioned register (R3) 112, register (R
4) 113, register (R5) 120, and buffer (BUF) 116,
117 is provided in the communication processing unit 11.

The register (R4) 113 and the buffer (BU
F) 117 receives the communication data directly from the communication network 3, or the local data directly distributed to the communication network 3 from the host, or the floating point adder (FLOAT) in the communication processing unit 11 of its own. 114,
Sends the calculation result data from the integer adder (INT) 115 to the communication network 3. These hardware features are
It operates as in the following example to perform global processing.

"Stage 1": Software executed by the calculation processing unit 10, for example, the above-mentioned "hardware mechanism 1" starts operating according to an instruction from the above-mentioned communication library.
At this time, the logical address of the processor element is received from the software and set in the register (R1) 110. In addition, the local data to be subjected to the global processing from software is converted into the global processing a), b),
In the case of c), it is received by the register (R3) 112 for local data, and in the case of global processing d), the buffer (BUF) 11
Receive on 6. In the case of the global processing d) described above, the length of the local data is set in the data length register (R5) 1
Receive at 20.

"Stage 2": The processor element (PEi) 1 in charge of the operation receives the communication data from the other processor operation (PEj) 1 according to the binary tree algorithm and performs the following processing.

1) In the case of global processing a), b), c) {size comparison, logical sum, exclusive OR, logical operation, etc.}, local data in register (R3) 112 and communication network 3 Each operation is performed with the communication data transferred and stored in the register (R4) 113, and the result is stored in the local data register (R3) 112 according to the binary tree algorithm, or other Send to processor element (PEj) 1 of.

2) In the case of global processing d) {congruence, that is, data combination}, the communication data transferred from the network 3 and stored in the buffer (BUF) 117 is used as the data length register (R5 ) Refer to 120 for the buffer (BU
F) Add the data to the end of the local data in 116, write it, and write the total data length to the above data length register (R5) 120.

The processing in the above "stages 1 and 2" is repeated until the binary tree converges. "Stage 3": The processor element (for example, PE1 in the binary tree configuration shown in FIG. 1) 1 standing at the top of the binary tree broadcasts the final result to all other processor elements and prepares for the next processing.

As described above, according to the present invention, in the communication processing circuit in the parallel computer, the logical address of the processor element, the number of all processor elements, and
A communication processing unit including a register and a buffer for storing local data and communication data, various arithmetic units, and a control sequencer for performing communication control is provided. After setting the logical address of the processor element and the number of processor elements in the register, the set logical address, the number of processor elements, and the sequence number of the control sequencer instructing the number of times of communication are set. Global communication processing (data transmission, data reception, calculation, or calculation result transmission) by the defined binary tree method is selectively executed independently of the operation in the calculation processing unit (main unit). It is characterized in that it is configured to do.

[0044]

As described in detail above, according to the communication processing circuit in the parallel computer of the present invention, the overhead caused by executing the general-purpose message passing (message passing) communication software many times is avoided. Moreover, by executing the binary tree algorithm, which is a standard process, by the hardware mechanism, the arithmetic processing can be performed without competing with other input / output or memory access of the processor element (PE1, PE2, ...). The control can be performed, and the communication data from the communication network need not be moved to the calculation processing unit (main body) of the processor element (PE1, PE2, ...), so that the processing can be speeded up. As a result, there is an effect that the time of the composite communication processing can be shortened and the operation rates of all the processor elements can be improved.

[Brief description of drawings]

FIG. 1 is a diagram schematically showing an embodiment of the present invention.

FIG. 2 is a diagram illustrating global processing using a binary tree.

FIG. 3 is a diagram illustrating a conventional communication processing method in a parallel computer.

[Explanation of symbols]

1 Processor element (PE1, PE2, ...) 10 Calculation processor (main body) 11 Communication processor 110 Register (R1) 111 Register (R
2) 112 register (R3) 113 register (R
4) 114 Floating point adder (FLOAT) 115 Integer adder (INT) 116,117 Buffer (BUF) 118 Control sequencer 119 Communication network interface 120 Register (R5) 12 Distributed memory (main memory) 3 Communication network Processor element address (Processor element number) Number of processor elements Communication data Sequence number Local data Local data (Data length)

Claims (2)

[Claims] 1. A communication processing circuit in a processor element (1) in a parallel computer, wherein a plurality of processor elements (1) having a distributed memory (12) are connected via a communication network (3). Therefore, in each processor element (1), apart from the calculation processing section (10), the logical address () of the processor element,
Number of all processor elements () and calculation processing unit (10)
Local data from (,) and the communication network
Registers (110,111,112,120,113) for storing communication data () received from (3), buffers (116,117), various arithmetic units (114,115), control sequencer (118) for communication control, and communication network interface
(119) is provided with a communication processing unit (11), and the logical address of the processor element () and the number of processor elements () are stored in the registers (110, 111) according to an instruction from the software executed by the calculation processing unit (10). )
After setting, the communication process is determined by the set logical address (), the number of processor elements (), and the sequence number () of the control sequencer (118) that indicates the number of times of communication. (Sending data,
Or data reception, calculation, or transmission of calculation results)
Is selectively executed independently of the operation of the calculation processing section (10), a communication processing circuit in a parallel computer. 2. The communication processing circuit in a parallel computer according to claim 1, wherein, as the communication processing, a global operation is performed by a binary tree procedure.