JP3144918B2 - Vector processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a scalar, vector
More particularly, the present invention relates to a vector processing device that synchronizes the transfer of instructions and data from a scalar processor to a vector processor to speed up the activation of the vector processor and the processing of vector instructions.

[0002]

2. Description of the Related Art In general, in a vector processing apparatus, a scalar instruction for performing scalar processing and a vector instruction for performing vector processing are divided into respective instruction sequences, and information essential for a vector processor to process the vector instruction sequence is described as follows. A method in which a scalar processor gives a vector processor is used. In order to improve the performance of the vector processing device employing such a method, the processing of the vector instruction sequence by the vector processor and the setup of information necessary for the processing of the next vector instruction sequence by the scalar processor are performed in parallel, and the processing of the vector processor is performed. It is necessary to issue an instruction from the scalar processor to the vector processor without any delay, and to secure a sufficient throughput in information transfer between the scalar and vector processors.

In order to realize these, a copy of a scalar register for holding scalar data and a copy of an address register for holding an address of vector data are provided, as described in Japanese Patent Application Laid-Open No. 61-231664. It is known that a buffer for storing a vector instruction issued from a processor and an address of vector data is provided in a vector processor.

In the processing of a vector instruction sequence by these components, the contents of the scalar register and address register are copied to each copy when a vector processor start instruction (hereinafter referred to as an EXVP instruction) for instructing the start of processing of a preceding vector instruction sequence is executed. When written and the vector instruction is issued from the scalar processor, the instruction and the address are sequentially taken into the instruction buffer and the address buffer in the vector processor. However, reading of the scalar register and the address register to the vector processor is performed from a copy of the scalar register and a copy of the address register. Therefore, in parallel with the preceding vector instruction sequence processing in the vector processor, the scalar processor can perform writing to the scalar register and the address register used in the subsequent vector instruction sequence.

In the execution of the EXVP instruction for instructing the start of the processing of the subsequent vector instruction sequence, the instruction of the preceding vector instruction sequence and the address of the vector data are all fetched into the buffer in the vector processor by the end of issuing the preceding vector instruction. Therefore, if there is no instruction using scalar data in the preceding vector instruction sequence, the instruction can be executed immediately after the issuance of the instruction of the preceding vector instruction sequence.

However, when there is an instruction using scalar data in the preceding vector instruction sequence, execution of the EXVP instruction of the subsequent vector instruction sequence must wait for the vector processor to start the instruction using the scalar data. . That is, the scalar data is taken into the vector processor not at the time of issuing the vector instruction from the scalar processor to the vector processor, but at the start of the vector instruction in the vector processor. Writing of the vector instruction sequence to the copy of the scalar register by the EXVP instruction must wait.

Further, when a vector instruction using scalar data exists in the vector processor, the scalar data is read from the scalar processor at the start of instruction execution in the vector processor. The scalar data transfer overhead between the two vector processors becomes visible.

[0008]

In the above prior art, when a vector instruction using scalar data exists in the preceding vector instruction sequence, the EXVP of the subsequent vector instruction sequence
Instruction execution and instruction issuance from the scalar processor of the subsequent vector instruction sequence to the vector processor are waited until the vector processor starts processing of an instruction using scalar data in the preceding vector instruction sequence. Further, in reading scalar data in a vector processor, there is a problem that a scalar data transfer overhead between the two processors is large and the vector processor cannot be operated efficiently.

An object of the present invention is to improve the scalar data transfer logic from the scalar processor to the vector processor to reduce the vector processor start-up time and the scalar data transfer overhead in the vector instruction processing. An object of the present invention is to provide a processing device.

Another object of the present invention is to provide a one-chip LS
i for processing requests between CPUs and data transfer in a multiprocessor composed of CPUs comprising i.
It is an object of the present invention to provide a multiprocessor capable of improving transfer efficiency between CPUs.

[0011]

Means for Solving the Problems The present invention to achieve the above object, for transferring the scalar data in synchronism with the instruction issue to the vector processor from scalar processor, the scalar processor, a vector instruction, the Vect
Of scalar data or vector data required by
Vector instruction issuing means for synchronously sending a storage address
And the vector processor sends the vector
Memory of instruction and scalar data or vector data.
Instruction buffer to store dresses in corresponding areas
And scalar data buffer and address buffer.
Vector instructions and scalar data or
Read vector data and process each vector instruction
It has a configuration having vector instruction execution means .

Further, in a multiprocessor composed of CPUs each composed of one chip LSi,
Independently have a processing request path and a data path for
The PU includes a buffer for storing a processing request and a data buffer corresponding to the buffer for storing the processing request.

[0013]

According to the configuration of the present invention described above, scalar data is sent to and fetched from the vector processor in synchronization with the issuance of an instruction from the scalar processor to the vector processor. Therefore, the scalar processor executes the EXVP instruction of the subsequent vector instruction sequence and transmits the vector instruction without waiting for the vector processor to start executing the vector instruction .
It is possible to go out .

Further, when a vector instruction using scalar data is executed in the vector processor, the scalar data is read from the scalar data storage buffer in the vector processor, so that the overhead due to the scalar data transfer can be reduced.

In a multiprocessor composed of CPUs composed of one chip LSi, a processing request path for each CPU and a data path are provided independently, and each C
By providing a processing request storage buffer in the PU and a data buffer corresponding to the processing request storage buffer,
The processing request between U and the data required for the processing are transferred synchronously, and the overhead due to the data transfer between CPUs can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a vector processing apparatus according to the present invention will be described below in detail with reference to the drawings by taking the following FORTRAN program processing as an example.

[0017] Compiling the above program yields the following instruction sequence.

Scalar instruction sequence: Address Load: Address setup of vector data B and D Scaiar Load: Loading of scalar data k, l EXVP: Vector processor activation: Vector instruction sequence Vector Load: Loading of vector data B Vector Load: Vector Load of data D Vector Add: B (i) + k → A (i) Vector Add: D (i) + 1 → C (i) Vector Stor: Store of vector data A Vector Stor: Store of vector data C 10 Vector Link: End of vector instruction sequence. However, it indicates that the following vector instruction sequence can be processed even when the vector processor is operating.

Hereinafter, the processing of the instruction sequence will be described with reference to FIG. 1 which shows the configuration of one embodiment of the main part of the vector processing apparatus of the present invention.

When the vector processing device is started, the scalar instruction execution control logic unit 1 reads out a scalar instruction sequence stored in the main memory 2 via the storage control device 3.

The scalar instruction execution control logic unit 1 decodes this instruction sequence and sets the start address of the vector data B and D, which is the processing of the scalar instruction, on the main memory 2 in the address register 4. Similarly, scalar data k and l, which are scalar instruction processes, are set in the scalar register 5.

When the scalar instruction execution control logic unit 1 decodes the scalar instruction EXVP instruction, the contents of the address register 4 and the scalar register 5 are transferred to the work address register 6 and the work scalar register 7 respectively.
Copy to At this time, since the address and scalar data used in the vector instruction sequence are copied on the work, the addresses necessary for the subsequent vector instruction sequence, the scalar data to the address register 4 and the scalar register 5 are stored. Writing is enabled.

At the same time, the scalar instruction execution control logic unit 1 issues a request for reading a vector instruction sequence to the vector instruction issue control logic unit 8. In response to this request, the vector instruction issuance control logic unit 8 makes the scalar instruction EXVP
The vector instruction sequence specified by the instruction is stored in the main memory 2
The information is read from above via the storage controller 3. The vector instruction issuance control logic unit 8 sequentially decodes the vector instruction sequence and sends a vector instruction valid instruction signal to the vector instruction execution control logic unit 9 in the vector processor at one cycle pitch to the vector instruction execution control logic unit 9 via the path 10. Send out. In synchronization with this signal, the vector instruction issuance control logic unit 8 sends the vector instruction code to the vector processor via the data path 11, and further, the scalar data and address required by the instruction are sent to the work scalar register 7 by the selectors 12 and 13. , Selected from the work address register 6 and transmitted to the vector processor in synchronization with the instruction code via the data paths 14 and 15.

The vector instruction execution control logic unit 9 updates the in-pointer 16 in response to the vector instruction valid instruction signal, and stores the instruction codes of the vector instructions to 10 sent from the scalar processor as shown in FIG. Scalar data into the scalar data buffer 18,
Addresses are sequentially set in the address buffer 19. At this time, instructions that do not use scalar data, such as vector instructions,.
Even in the case of an instruction that does not use address data as in the above, some data is set because the in-pointer 16 is updated.

At this point, the scalar data used in the vector instruction has been fetched into the vector processor as well as the instruction code and address.
It becomes possible to execute the VP instruction and issue the vector instruction of the subsequent vector instruction sequence to the vector processor without waiting for the vector processor to start executing the vector instruction.

When the vector instruction execution control logic unit 9 receives the vector instruction valid instruction signal of the vector instruction, the vector instruction execution control logic unit 9 transfers the instruction code via the selector 20 to the vector instruction buffer 17.
Read, vector load / store requester 21
If is not available, a vector instruction execution instruction signal is issued to the vector load / store requester 21. When the vector load / store requester 21 receives the vector instruction execution instruction signal, the vector load / store requester 21
9, the start address of the vector data B on the main memory 2 is fetched, and the vector data B is loaded from the main memory 2 to the vector register 23. At this time, the scalar data is also transmitted to the vector load / store requester 21 via the selector 24, but is not used.

The vector instruction execution control logic unit 9 updates the out pointer 25 at the same time as issuing the vector instruction execution instruction signal of the vector instruction, reads the instruction code of the vector instruction, and sends the scalar data and address to the vector load / store requester 21. Send out. When the processing of the vector instruction is completed, the vector instruction execution control logic unit 9 issues a vector instruction execution instruction signal of the vector instruction to the vector load / store requester 21 and, like the processing of the vector instruction, converts the vector data D. Load into vector register 23.

When the vector instruction execution instruction signal of the vector instruction is issued, the out pointer 25 is updated again, and
The vector instruction execution control logic unit 9 reads the instruction code of the vector instruction, and issues a vector instruction execution instruction signal to the vector arithmetic unit 26 if the vector arithmetic unit 26 is free. At this point, since the scalar data k has been sent from the scalar data buffer 18 to the vector calculator 26 via the selector 24, the overhead due to the transfer of the scalar data between processors is not visible.

The vector calculator 26 adds the scalar data k and the vector data B read from the vector register 23 to obtain vector data A,
Write to 3. The vector instruction execution instruction signal of the vector instruction is issued after the end of the vector instruction in the vector calculator 26, and the vector data C is obtained and written to the vector register 23 in the same manner as the processing of the vector instruction.
Similarly, the instruction code and the address of the vector instruction are sent from each buffer in the vector processor by a vector instruction execution instruction signal, and the vector load / store requester 21 transfers the vector data A, C from the vector register 23 to the main storage memory 2. Is stored.

Vector instruction 10 indicating the end of the instruction sequence
Indicates that the subsequent vector instruction sequence can be processed even while the vector processor is operating. As described above, by having the scalar data buffer 18 corresponding to the instruction buffer 17, even if there is an instruction using scalar data in the preceding vector instruction sequence, the instruction can be issued to the vector processor of the subsequent vector instruction sequence. Therefore, the vector processor can be used efficiently. Further, when a vector instruction execution instruction signal of an instruction using scalar data is issued in the vector processor, since the scalar data is already stored in the scalar data buffer 18, the overhead due to the transfer time of the scalar data between processors is not visible. Thus, the processing time of the vector instruction sequence in the vector processor can be reduced.

Next, one chip C using the present invention is used.
FIG. 3 shows an embodiment of a multiprocessor composed of PUs.
This will be described with reference to FIG. FIG. 3 shows a conceptual diagram thereof.

In FIG. 3, a processing request from CPU0 to CPU1 is sent out via a path 29a and stored in a processing request storage buffer queue 27b in CPU1. Data necessary for the processing is sent from the CPU 0 to the CPU 1 via the path 30a in synchronization with the processing request, and stored in the data buffer queue 28b in the CPU 1. Similarly,
The processing request from the CPU 1 to the CPU 0 is sent out via the path 29b and stored in the processing request storage buffer queue 27a in the CPU 0. Data necessary for the processing is transmitted from the CPU 1 to the CPU 0 via the path 30b in synchronization with the processing request, and stored in the data buffer queue 28a in the CPU 0. Processing request path 2 from CPU0 to CPU1
9a and a processing request path 29b from CPU1 to CPU0,
And data path 30a from CPU0 to CPU1 and CP
Since the data paths 30b from U1 to CPU0 are independent of each other, transfer between the CPUs can operate in parallel.

Further, the CPU which has received the processing request reads out the data necessary for the processing from the data storage buffer queues 28a and 28b in its own CPU. The next processing request and data can be transmitted without waiting for the processing to be completed, and the overhead due to transfer between CPUs can be reduced.

In this embodiment, a CPU comprising one chip LSi
FIG. 4 shows a specific embodiment used for a multi-vector processor composed of. In this figure, as in FIG.
a and 27b are processing request storage buffer queues, 28a and 2
8b shows a data buffer queue.

For example, a case will be considered in which a calculation result such as the sum of vector data obtained by the CPU 0 is used for the calculation by the CPU 1. First, the instruction execution control logic unit 31 in the CPU 0
a reads an instruction sequence from the main storage memory 2. CPU0
The internal instruction execution control logic unit 31a issues an instruction code indicating the sum of vector data to the vector arithmetic unit 26a in the CPU 0 via the selector 32a. The vector computing unit 26a in the CPU0 reads the vector data from the vector register 23a in the CPU0, calculates the sum, and outputs the resulting scalar data to the CPU 33 via the path 33a and the selector 34a.
The value is stored in the scalar register 5a. Next, the instruction execution control logic unit 31a in CPU0 sends out a processing request valid instruction signal to the instruction execution control logic unit 31b in CPU1 via the path 35a. In synchronization with this signal, a processing request is sent from the instruction execution control logic unit 31a in the CPU 0 to the path 29a,
The scalar data of the sum is sent from the scalar register 5a in the PU0 to the path 30a via the selector 36a. The instruction execution control logic unit 31b in the CPU 1 that has received the processing request validity instruction signal processes the processing request transmitted in synchronization with the CPU.
The scalar data is transferred to the processing request storage buffer queue 27b in the CP 1 corresponding to the processing request storage buffer queue 27b.
The data is stored in the U1 data storage buffer queue 28b.

At this point, the scalar register 5a storing the summation result in the CPU 0 can be used by the subsequent instruction. Further, subsequent processing requests from CPU0 to CPU1 and data necessary for the processing are sequentially transmitted without waiting for the completion of execution of the preceding processing request by CPU1, and processing request storage buffer queue 27b and data storage buffer queue 28b of CPU1 are sent. Is stored in

The CPU 1 reads the processing request from the CPU 0 from the processing request storage buffer queue 27b in the CPU 1, and sends it to the vector computing unit 26b in the CPU 1 via the selectors 37b and 32b. At the same time, the scalar data is read from the data storage buffer queue 28b in the CPU 1 and transmitted to the vector calculator 26b via the selector 38b. Similarly, processing requests from the subsequent CPU 0 to the CPU 1 are sequentially processed after the execution of the preceding processing request is completed.
That is, the scalar data required for the subsequent processing request is already stored in the data storage buffer queue 28b in the CPU 1 at the time of executing the processing, so that the overhead due to the data transfer between the CPUs cannot be seen.

Further, the processing request transfer path 29b and the data transfer path 30b from the CPU 1 to the CPU 0
Is independent of the processing request transfer path 29 to the CPU 1 and the data transfer path 30a, so that processing requests from the CPU 1 to the CPU 0 can be operated in parallel, and transfer between CPUs can be performed efficiently. .

[0039]

According to the present invention, scalar, vector 2
In a vector processing device composed of two processors, a scalar data buffer corresponding to a vector instruction buffer is provided in the vector processor, so that an instruction of a subsequent vector instruction sequence is issued without waiting for the vector processor to start processing a scalar data use instruction. Therefore, the vector processor activation time can be reduced, and the overhead of transferring scalar data between processors in processing a vector instruction sequence using scalar data can be reduced.

In a multiprocessor composed of CPUs composed of one chip LSi, processing paths between CPUs and data transfer paths necessary for the processing are independently provided, and a processing request storage buffer queue is provided in each CPU. And a data storage buffer queue corresponding to this, there is an effect that transfer overhead between CPUs is reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a main part of a vector processing device having a scalar data buffer according to the present invention.

FIG. 2 is a diagram showing the correspondence between a vector instruction buffer, a scalar data buffer, and an address buffer according to the present invention.

FIG. 3 shows a CPU comprising one chip LSi using the present invention.
FIG. 1 is a conceptual diagram of a multiprocessor constituted by.

FIG. 4 shows a CPU using one chip LSi according to the present invention.
FIG. 2 is a block diagram showing an embodiment of a main part of a multi-vector processor constituted by.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Scalar instruction execution control logic part, 2 ... Main memory, 3 ... Storage controller, 4 ... Address register, 5 ... Scalar register, 6 ... Work address register, 7 ... Work scalar register, 8 ... Vector instruction issue control logic Part, 9 ... vector instruction execution control logic part, 12, 13, 20, 22, 24, 32a, 32b, 34
a, 34b, 36a, 36b, 37a, 37b, 38
a, 38b selector, 16 in pointer, 17 vector instruction buffer, 18 scalar data buffer, 19 address buffer, 21 vector load / store requester, 23 vector register, 25 out pointer, 26 vector operation 27a, 27b ... processing request storage buffer queue, 28a, 28b ... data storage buffer queue, 29a, 29b ... processing request transfer path, 30a, 30b ... data transfer path, 31a, 31b ... instruction execution control logic section, 35a, 35b ... Processing request valid instruction signal transfer path.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-231664 (JP, A) JP-A-60-250476 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 17/16

Claims (2)

(57) [Claims] 1. A vector processing apparatus for performing an arithmetic operation by combining a scalar processor that executes processing of a scalar instruction sequence and a vector processor that executes processing of a vector instruction sequence, wherein the scalar processor sequentially executes the scalar instruction sequence. Scalar instruction executing means for processing, scalar data holding means for holding a plurality of scalar data, address holding means for holding a main storage address of a plurality of vector data, and a scalar instruction executing means for processing a vector processor start instruction. In response to a request from the scalar instruction executing means, the vector instruction sequence is sequentially sent to the vector processor, and the scalar data or the main storage address of the vector data required for each vector instruction in the vector instruction sequence is stored in the scalar data. Holding means or the address holding means And a vector instruction issuing unit for transmitting the vector instructions to the vector processor in synchronization with the transmission of each vector instruction. The vector processor stores a plurality of vector instructions transmitted from the scalar processor. And a main storage address of scalar data or vector data required for each vector instruction transmitted from the scalar processor in synchronization with each vector instruction, in an area corresponding to a storage area of each vector instruction in the instruction buffer. A scalar data buffer and an address buffer, respectively, and the plurality of vector instructions stored in the instruction buffer are sequentially read, and the scalar data buffer or the address buffer corresponding to a storage area of each vector instruction in the instruction buffer. Vector vectors from the storage area of A vector instruction executing means for extracting a main storage address of scalar data or vector data required by the instruction and processing each vector instruction. 2. The vector processing apparatus according to claim 1, wherein said scalar data holding means holds a plurality of scalar data obtained by processing said scalar instruction sequence by said scalar instruction execution means. Holding means for storing a copy of a plurality of scalar data held by the first scalar holding means in response to a request from the scalar instruction executing means when the scalar instruction executing means processes a vector processor start instruction; A scalar holding unit, wherein the address holding unit is a first address holding unit that holds a main storage address of a plurality of vector data obtained by the scalar instruction execution unit processing a scalar instruction sequence. When the scalar instruction execution means processes the vector processor start instruction, the request from the scalar instruction execution means And a second address holding means for holding a copy of a main storage address of a plurality of vector data held by the first address holding means, wherein the vector instruction issuing means has a scalar required for each vector instruction. A vector processing device, wherein a main storage address of data or vector data is selected from the second scalar holding means or the second address holding means and transmitted to the vector processor.